Category Archives: Semiconductors

GLOBALFOUNDRIES today announced the availability of a new set of enhanced RF SOI process design kits (PDKs) to help designers improve their designs of RF switches and deliver differentiated RF front-end solutions for a wide range of markets including front-end modules for mobile devices, mmWave, 5G and other high-frequency applications.

GF’s advanced RF technology platform, 7SW SOI, is optimized for multi-band RF switching in next-generation smartphones and poised to drive innovation in Internet of Things (IoT) applications. Designed for use with Coupling Wave Solutions’ (CWS) simulation tool, SiPEX™, GF’s 7SW SOI PDK allows designers to integrate RF switches with other critical RF blocks that are essential to the design of complex electronic systems for future RF communication chips. Specifically, this new capability allows designers to improve RF simulation output by simulating a highly-resistive substrate parasitic effect across their entire design.

“GF leads the industry in RFSOI technology, and we are committed to providing our customers with design productivity solutions for our RF processes,” said Bami Bastani, senior vice president of RF at GF. “CWS’ SiPEX™ tool provides our customers with best-in-class correlation between simulated results and real world measurements, further optimizing the design layout to achieve efficiency and deliver differentiated RF front-end solutions.”

“This is great news for the RF design community,” said Brieuc Turluche, chairman of the board of directors and chief executive officer of CWS. “The integration of SiPEX into GF’s RF SOI PDKs is a major milestone to achieve first-time correct complex and optimized RF SOI designs for high-performing cellular, IoT, 5G and Wi-Fi communication chips.”

GF’s RF SOI technologies offer significant performance, integration and area advantages in front-end RF solutions for mobile devices and RF chips for high-frequency, high-bandwidth wireless infrastructure applications. CWS’ SiPEX accelerates the design of RF SOI switches by improving linearity simulation accuracy. It can also be effective in the design of low-noise amplifiers (LNA) and power amplifiers (PA), enabling designers to reduce their size to lower costs.

SiPEX™ is available in the current release of GF’s 7SW SOI PDK. For more information on the company’s RF SOI solutions, contact your GF sales representative or go to www.globalfoundries.com.

Modern life will be almost unthinkable without transistors. They are the ubiquitous building blocks of all electronic devices: each computer chip contains billions of them. However, as the chips become smaller and smaller, the current 3D field-electronic transistors (FETs) are reaching their efficiency limit. A research team at the Center for Artificial Low Dimensional Electronic Systems, within the Institute for Basic Science (IBS), has developed the first 2D electronic circuit (FET) made of a single material. Published on Nature Nanotechnology, this study shows a new method to make metal and semiconductor from the same material in order to manifacture 2D FETs.

In simple terms, FETs can be thought as high-speed switches, comprised of two metal electrodes and a semiconducting channel in between. Electrons (or holes) move from the source electrode to the drain electrode, flowing through the channel. While 3D FETs have been scaled down to nanoscale dimensions successfully, their physical limitations are starting to emerge. Short semiconductor channel lengths lead to a decrease in performance: some electrons (or holes) are able to flow between the electrodes even when they should not, causing heat and efficiency reduction. To overcome this performance degradation, transistor channels have to be made with nanometer-scale thin materials. However, even thin 3D materials are not good enough, as unpaired electrons, part of the so-called “dangling bonds” at the surface interfere with the flowing electrons, leading to scattering.

Passing from thin 3D FETs to 2D FETs can overcome these problems and bring in new attractive properties. “FETs made from 2D semiconductors are free from short-channel effects because all electrons are confined in naturally atomically thin channels, free of dangling bonds at the surface,” explains Ji Ho Sung, first author of the study. Moreover, single- and few-layer form of layered 2D materials have a wide range of electrical and tunable optical properties, atomic-scale thickness, mechanical flexibility and large bandgaps (1~2 eV).

The major issue for 2D FET transistors is the existence of a large contact resistance at the interface between the 2D semiconductor and any bulk metal. To address this, the team devised a new technique to produce 2D transistors with semiconductor and metal made of the same chemical compound, molybdenum telluride (MoTe2). It is a polymorphic material, meaning that it can be used both as metal and as semiconductor. Contact resistance at the interface between the semiconductor and metallic MoTe2 is shown to be very low. Barrier height was lowered by a factor of 7, from 150meV to 22meV.

IBS scientists used the chemical vapor deposition (CVD) technique to build high quality metallic or semiconducting MoTe2 crystals. The polymorphism is controlled by the temperature inside a hot-walled quartz-tube furnace filled with NaCl vapor: 710°C to obtain metal and 670°C for a semiconductor.

The scientists also manufactured larger scale structures using stripes of tungsten diselenide (WSe2) alternated with tungsten ditelluride (WTe2). They first created a thin layer of semiconducting WSe2 with chemical vapor deposition, then scraped out some stripes and grew metallic WTe2 on its place.

It is anticipated that in the future, it would be possible to realize an even smaller contact resistance, reaching the theoretical quantum limit, which is regarded as a major issue in the study of 2D materials, including graphene and other transition metal dichalcogenide materials.

The International Microelectronics And Packaging Society (IMAPS) will celebrate the 50th anniversary of its flagship technical conference – the IMAPS Symposium – from October 9 – 12, 2017, as microelectronics engineers and scientists gather at the Raleigh Convention Center near Research Triangle Park, North Carolina, USA to take part in the electronics industry’s largest technical conference dedicated to advanced microelectronics packaging technology. Researchers and exhibitors will showcase their work during a comprehensive conference program of technical papers, panels, special sessions, short courses/tutorials, and an exhibition that will spotlight premier work in the fields of microelectronics, semiconductor packaging and circuit design.

The 50th International Symposium on Microelectronics is an international technology forum for the presentation of applied research on microelectronics, consisting of more than 180 papers presented by researchers from corporations, universities and government labs worldwide, with five technical tracks: Chip Packaging Interactions; High Performance, Reliability, & Security; Advanced Packaging & Enabling Technologies; Advanced Packaging & System Integration; and Advanced Materials & Processes.

Keynote Presentations Lead Off the IMAPS Technical Program on Tuesday, October 10
Four keynote addresses from leading industry experts include:

“Packaging Challenges for the Next Generation of Mobile Devices,” by Ahmer Syed, Senior director of package engineering, Qualcomm Technologies

“Packaging without the Package – A More Holistic Moore’s Law,” by Subramanian (Subu) S. Iyer, distinguished chancellor’s professor in the Charles P. Reames Endowed Chair of the Electrical Engineering Department at the University of California at Los Angeles (UCLA) and Director of the Center for Heterogeneous Integration and Performance Scaling (CHIPS)

“Electronics Outside the Box: Building a Manufacturing Ecosystem for Flexible Hybrid Electronics,” by Benjamin Leever, senior materials engineer, Air Force Research Laboratory (AFRL) Soft Matter Materials Branch

“Transforming Electronic Interconnect,” by Tim Olson, founder & CTO, Deca Technologies

International Panel Session & Wine Reception on Wednesday, October 11
A panel session on “Global Perspectives on Packaging Requirements & Trends Towards 2025” will be moderated by Jan Vardaman, TechSearch International and Gabriel Pares, CEA-Leti. Panelist will include representatives from Asia (Yasumitsu Orii, NAGASE Group and Ton Schless, SIBCO), Europe (Steffen Kroehnert, Nanium and Eric Bridot, SAFRAN), and North America (David Jandzinski, Qorvo). The 90-minute panel session includes a wine reception.

Diversity Roundtable & Networking Discussions on Monday, October 9
Following the opening reception, IMAPS leaders will conduct a series of roundtable discussions designed to inspire conversations about overcoming diversity barriers, the strengths inherent in a diverse workforce, identifying and collaborating with a mentor, and more.

Posters & Pizza Session on Thursday, October 12
One of the fastest-growing segments of the IMAPS conference is the popular “Posters & Pizza” session held outside the exhibit hall, giving attendees the opportunity to interact one-on-one with presenters in a more informal setting.

Professional Development Courses (Short Courses & Tutorials) on Monday, October 9
Preceding the IMAPS Symposium technical program is a full day of professional development opportunities, presented as a series of 2-hour sessions in four tracks: Intro to Microelectronics Packaging; Next Generation Packaging Challenges; Baseline & Emerging Technologies; and Reliability. These short courses represent a unique opportunity, only available through IMAPS, for participants to personally interact with the instructors, and with each other in small groups from 10 – 30 people, led by industry experts in the field with ample time for questions and networking.

Student Opportunities at IMAPS
As part of its ongoing mission IMAPS invites students to participate in an informal networking event on Tuesday, October 10 with IMAPS industry leaders over lunch in the exhibit hall, giving them an chance to learn about career opportunities, navigating the hiring process, and other topics. In addition, the IMAPS Microelectronics Foundation sponsors a student paper competitionin conjunction with the Symposium that awards more than $3,500 in scholarships for outstanding student papers.

Social Events & an Introduction to the RTP/Raleigh Area’s Technology Community
In addition to the technical program, a variety of social events are planned around the IMAPS Symposia, including the Annual David C. Virissimo Memorial Fall Golf Classic, a charity golf outing scheduled for Monday, October 9 at NCSU’s Lonnie Poole Golf Course. Proceeds from the event benefit the IMAPS Microelectronics Foundation.

Monday evening’s welcome reception will feature NC-themed entertainment from a local bluegrass band, and participants will also be able to view historical photos and other memorabilia spanning 50 years of IMAPS history.

There is also a scheduled tour of the nearby Micross Advanced Interconnect Technology (AIT) facility, one of the premier wafer bumping and wafer level packaging facilities in the U.S., with more than 20 years experience providing leading edge interconnect and 3D integration technologies (TSV, Si interposers, 3D IC) to worldwide customers.

New to the Symposium this year is a unique opportunity for IMAPS attendees to experience the vibrant technology community in the greater RTP/Raleigh area. IMAPS has invited local non-profit organizations that comprise the area’s rapidly-growing technology ecosystem to participate in a special area adjacent to the exhibit hall during the day of October 10, providing an opportunity for IMAPS Symposium attendees to network and interact.

To register for the IMAPS 50th International Symposium on Microelectronics, please visit the online registration site for more information, or contact Brianne Lamm, IMAPS Marketing & Events Manager, at [email protected] or 980-299-9873.

Entegris Inc. (NASDAQ: ENTG), a specialty materials provider, announced at SEMICON Taiwan today the availability of its Oktolex membrane technology for advanced point-of-use photolithography applications. Oktolex’s membranes remove critical photochemical contaminants by enhancing the native retention mechanisms of each membrane type to match the needs of each chemistry. By matching membrane characteristics with specific contaminant-adsorption mechanisms, Oktolex membranes further optimize removal performance with no adverse interactions with the chemical composition.

“Breaking from convention, we’ve developed a cleaner, faster, and more effective way to remove the most challenging contaminants with a tailored approach to the specific contamination control needs of ArF, KrF, and EUV applications for Logic, DRAM, and 3D NAND devices,” noted Entegris Senior Vice President and General Manager of Microcontamination Control, Clint Haris. “The true advantage of this technology is its ability to create membranes that effectively remove the targeted contaminants, while not altering the chemical composition. This combination enables us to collaborate with customers to create precise contaminant removal solutions that meet the needs of advanced nodes and reduce tool downtime.”

Oktolex technology is currently available in Entegris Impact 8G point-of-use photochemical filters.

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that John Wall, corporate vice president of finance and corporate controller of Cadence, has been appointed senior vice president and chief financial officer of Cadence, effective October 1, 2017. Geoff Ribar, current CFO of Cadence, will remain with the company as a senior advisor until his previously announced retirement at the end of March 2018.

Mr. Wall, a 20-year Cadence executive, has been corporate controller for the past year-and-a-half, during which he has worked closely with Mr. Ribar to set and execute the company’s financial goals. He previously served as vice president of finance, where he was responsible for worldwide revenue accounting and sales finance, and was instrumental in development of the ratable revenue model and sales models that Cadence uses. At the beginning of his tenure with Cadence, Mr. Wall established the Cadence office in Dublin, Ireland, was European controller and implemented the company’s international tax structure.

“The Board of Directors and I are excited to appoint John Wall as the next CFO of Cadence,” said Lip-Bu Tan, president and chief executive officer of Cadence. “We are confident that John’s deep financial experience and knowledge about our business will serve us well as we build upon the important progress we have made with our System Design Enablement strategy, further expand Cadence’s position with customers and improve our financial position.”

Mr. Tan continued, “On behalf of the Board and the entire Cadence team, I want to express our deepest gratitude to Geoff Ribar for his significant contributions to Cadence’s excellent financial management over the last seven years as CFO. Geoff played a key role in building the financial foundation through which we steadily increased our operating margin and improved our performance. We look forward to continuing to benefit from his exceptional skill and leadership during the transition and wish him all the best for the future.”

Cadence has also appointed Michelle Quejado as corporate controller, reporting to Mr. Wall. Ms. Quejado was most recently interim CFO at Zynga Inc., where she also served as corporate controller and chief accounting officer. Prior to Zynga, she served in multiple financial executive positions at Lam Research Corporation, including assistant corporate controller.

TowerJazz, the global specialty foundry, today announced the release of its advanced 5V 65nm power process providing customers with multiple advantages over 0.18um 5V technologies. The advanced 5V 65nm technology increases TowerJazz’s footprint in the 5V power market by offering enhanced Rdson efficiency with an attractive die cost advantage over 0.18um 5V processes. This technology is based on TowerJazz’s automotive 300mm 65nm process platform manufactured in its Uozu, Japan facility and supports both best in class quality and manufacturing cycle time.

The advanced 5V 65nm contains a rich portfolio of analog features and many different metal combinations to optimize cost/performance for any application. The first products, for several strategic customers, were already prototyped with outstanding performance. The technology is now fully released and supports Multi-layer Masking (MLM) and an MPW option to reduce engineering costs. The first MPW is targeted for November 2017.

TowerJazz’s 5V 65nm power technology offers high Rdson efficiency using tighter design rules for power devices, and a thick copper top metal for large current applications, enabling the 5V transistors using a 65nm design to achieve dense digital capabilities and a dense analog periphery, with a low number of manufacturing masks. The technology offers an average of 30% area reduction for a given 5V power transistor and typically a 35% die size reduction for a mixed-signal chip. An optimization effort to minimize cost and manufacturing layers needed to support 5V enables highly competitive solutions for many different markets such as automotive, industrial and consumer. The advanced 5V 65nm supports high current power applications such as PMIC, DC/DC converters, load switches and point of load ICs using single and dual 3.3um thick copper metal layers.

“Streamlining our feature rich automotive quality 65nm technology allows TowerJazz to provide very attractive 5V power and mixed-signal solutions with the high quality standard set required for servicing the automotive market,” said Shimon Greenberg, Vice President and General Manager of Mixed-Signal and Power Management Business Unit, TowerJazz. “This technology is utilized for relatively high current power ICs at 5V which have large growth drivers to advanced analog and mixed-signal ICs.”

Lam Research Corp. (Nasdaq: LRCX), a global supplier of wafer fabrication equipment and services to the semiconductor industry, today announced it has recognized seven companies with Supplier Excellence Awards. Selected from among Lam’s extensive list of preferred global suppliers, the 2017 award winners represent partners who have demonstrated a deep commitment to collaboration and strategic operations in an evolving semiconductor industry.

“We are pleased to recognize the critical role our top suppliers play in the delivery of industry-leading products and services to our customers,” said Tim Archer, chief operating officer of Lam Research. “Lam’s business operations continue to grow—in scale, complexity, and geographic footprint. All of the suppliers recognized today demonstrate a commitment to innovation, collaboration, and partnership that will be increasingly important to our future. We are pleased to honor the achievements of these remarkable companies with our 2017 Supplier Excellence Awards.”

Award recipients were announced on September 12 at the company’s 2017 Supplier Day event, during which Lam Research focused on enhancing collaboration and renewing opportunities for mutual success with its customers and suppliers. Executives from suppliers around the world attended the event, where the following seven companies were recognized.

  • Edwards Vacuum
  • HORIBA, Ltd.
  • ILSHIN Precision Co. Ltd.
  • MKS Instruments, Inc.
  • Tokai Carbon Korea Co. Ltd.
  • TOTO, Ltd.
  • Ultra Clean Technology

SPTS Technologies, an Orbotech company and a supplier of advanced wafer processing solutions for the global semiconductor and related industries, today announced that it has been selected by Chipmore Technology Corporation Limited, an LCD driver integrated chip (IC) packaging specialist, to supply physical vapor deposition (PVD) solutions for the under bump metallization (UBM) and redistribution layers (RDL) for their flip-chip packaging line.   Chipmore chose the Sigma® fxP PVD solution for their new copper (Cu) bumping line, as it provides superior results and lowest cost of ownership over competitor systems.

“Consumer demand for high-end smartphones and other mobile devices with higher resolution screens are driving the rapid growth of advanced display driver IC’s,” stated Mr. Kevin Crofton, Corporate Vice President at Orbotech and President of SPTS Technologies. “Our Sigma fxP PVD system provides Chipmore with the most cost effective means to expand their bumping capacity to meet the demand from display-driver IC manufacturers.” 

Mr. Sampus Yang, Vice President at Chipmore stated: “Chipmore offers a range of bumping solutions for our global customers, ranging from high-end gold bumping to cost-effective copper bumping for flip chip packaging. SPTS’s Sigma fxP PVD system produces high quality copper pillars with excellent throughput and low cost of ownership, which allows us to remain competitive in a highly cost-sensitive market. The additional bumping capability will allow us to capitalize on consumers’ growing appetite for higher resolution LCD displays and strengthen our reputation as a top packaging services company.”

Despite a slightly down first quarter, the semiconductor industry achieved near record growth in the second quarter of 2017, posting a 6.1 percent growth from the previous quarter, according to IHS Markit (Nasdaq: INFO). Global revenue came in at $101.4 billion, up from $95.6 billion in the first quarter of 2017. This is the highest growth the industry has seen in the second quarter since 2014.

The memory chip market set records in the second quarter, growing 10.7 percent to a new high of $30.2 billion with DRAM and NOR flash memory leading the charge, growing 14 percent and 12.3 percent quarter-on-quarter, respectively.

“The DRAM market had another quarter of record revenues on the strength of higher prices and growth in shipments,” said Mike Howard, director for DRAM memory and storage at IHS Markit. “Anxiety about product availability in the previous third and fourth quarters weighed on the industry. This led many DRAM buyers to build inventory — putting additional pressure on the already tight market. This year is shaping up to smash all DRAM revenue records and will easily pass the $60 billion mark.”

“For NOR, the supply-demand balance has tightened raising average selling prices and revenue,” said Clifford Leimbach, senior analyst for memory and storage at IHS Markit. “This mature memory technology has been in a steady decline for many years, but some market suppliers are reducing supply or leaving the market, which has tightened supply recently, resulting in the increase of revenue.”

In terms of application, consumer electronics and data processing saw the most growth, increasing in revenue by 7.9 percent and 6.8 percent, respectively, quarter-on-quarter. A lot of this growth can be attributed to the continual growth in memory pricing, as supply still remains tight.

Industrial semiconductors showed the third highest growth rate at 6.4 percent during the same period. This growth can be attributable to multiple segments, such as commercial and military avionics, digital signage, network video surveillance, HVAC, smart meters, traction, PV inverters, LED lighting and medical electronics including cardiac equipment, hearing aids and imaging systems.

Another trend in the industrial market is increasing factory automation, which alone is driving growth for discrete power transistors, thyristors, rectifiers and power diodes. The market for these devices is expected to reach $8 billion in 2021, up from $5.7 billion in 2015.

Intel remains the number one semiconductor supplier in the world, followed by Samsung Electronics by a slight margin. IHS Markit does not include foundry operations and other non-semiconductor revenue in the semiconductor market rankings.

Among the top 20 semiconductor suppliers, Advanced Micro Devices (AMD) and nVidia achieved the highest revenue growth quarter over quarter by 24.7 percent and 14.6 percent, respectively. There was no market share movement in the top 10 semiconductor suppliers. However, seven of the 10 companies in the 11 to 20 market share slots did change market share.

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JoshThe Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced Josh Shiode has joined the association as government affairs director. In this role, Shiode will help advance the U.S. semiconductor industry’s key legislative and regulatory priorities related to semiconductor research and technology, product security, and high-skilled immigration, among others. He also will serve as a senior representative of the industry before Congress, the White House, and federal agencies.

“The U.S. semiconductor industry is a key driver of America’s economic strength, national security, and global technology leadership,” said John Neuffer, SIA president and CEO. “Josh Shiode’s extensive knowledge, skills, and experience will make him an ideal advocate for our industry’s policy priorities in Washington, D.C. We’re thrilled to welcome him to the SIA team and look forward to his help advancing initiatives that promote growth and innovation in our industry and throughout the U.S. economy.”

Shiode most recently served as senior government relations officer at the American Association for the Advancement of Science (AAAS), where he helped guide the association’s science and technology advocacy before the executive and legislative branches. Previously, Shiode was a public policy fellow at the American Astronomical Society (AAS), where he helped develop and implement AAS’s government advocacy strategies. Shiode holds a doctorate in astrophysics from the University of California, Berkeley and a bachelor’s degree in astronomy and physics from Boston University.