Category Archives: Semiconductors

The SEMI Foundation today announced that it will be celebrating its 10th anniversary of partnership with New York State United Teachers (NYSUT) on August 22-23 in Latham, New York at the NYSUT headquarters.  The Foundation and NYSUT will culminate a two-day SEMI High Tech U program for teachers on Wednesday, August 23rd with a reception recognizing industry instructors from Applied Materials and KLA-Tencor for leadership in volunteerism and STEM education.

The SEMI Foundation’s acclaimed STEM program, SEMI High Tech U – Teacher Edition has reached more than 600 teachers in upstate New York since 2007.  The two-day teacher program provides industry led, hands-on activities and curriculum that teachers can take back to the classroom in addition to unique opportunities to network with high-tech industry professionals.  Teachers-turned-students also tour the College of Nanoscale Science and Engineering for a first-hand look at how relevant STEM skills are utilized in a high-tech workplace.  This fall, the teachers’ new knowledge will be passed along to their students in the classroom. A retrospective survey of past SEMI High Tech U teacher participants showed that 95 percent of teachers who attend SEMI High Tech U – Teacher Edition gain an increased understanding of the relevance of STEM skills in today’s workplace.

This year’s program at NYSUT is supported by Applied Materials, GLOBALFOUNDRIES and KLA-Tencor.

Leslie Tugman, executive director of the SEMI Foundation, states, “NYSUT is a premier model of how education and industry partnerships can work together for the benefit of all in their region.  Through NYSUT’s High Tech U programs for teachers, we have exponentially reached thousands of students to help fill the high-tech talent pipeline.”

All SEMI High Tech U modules are taught by industry professionals and two legacy volunteer instructors, Vincent Villaume of Applied Materials and Jeff Barnum of KLA-Tencor, will be honored at a reception at NYSUT on August 23.

The “Global Gallium Arsenide (GaAs) Wafers Market 2017-2021” report has been added to Research and Markets’ offering.

The global gallium arsenide wafer market to decline at a CAGR of 11.9% during the period 2017-2021.

The report, Global Gallium Arsenide Wafer Market 2017-2021, has been prepared based on an in-depth market analysis with inputs from industry experts. The report covers the market landscape and its growth prospects over the coming years. The report also includes a discussion of the key vendors operating in this market.

The latest trend gaining momentum in the market is shutdown of 2G network. High-speed Internet has now become readily available worldwide. The data speed of a 4G connection is 10 times faster 3G data speed. This high-speed connectivity results in faster browsing, uninterrupted streaming of videos, and improved GPS performance. Thus, countries are now focusing on the adoption of 3G or 4G connectivity and shutting down 2G network spectrums.

According to the report, one of the major drivers for this market is the increasing adoption of smartphones. Shipments of smartphones will reach 2.16 billion units by 2021, which is a significant increase from around 1.6 billion units in 2016. The major driving factor responsible for this growth is the rising smartphone penetration in countries with high population density such as China, India, and Brazil. The growth in the shipment volume of smartphones will drive the demand for GaAs wafers used in mobile handsets, particularly for mobile power amplifiers.

Global DRAM revenue reached a new historical high in the second quarter of 2017, reports DRAMeXchange, a division of TrendForce. Compared with the first quarter, the undersupply situation was not as severe, and OEM clients in the downstream were able to gradually extend their inventories. Nevertheless, the global ASPs of PC and server DRAM products rose by more than 10% sequentially in the second quarter, while the global ASP of mobile DRAM products showed a less than 5% gain. The smaller price increase for mobile DRAM was due to Chinese smartphone brands lowering than annual shipment targets.

“The DRAM market benefitted from the upswing in ASPs and continuing progress in suppliers’ technology migrations,” said Avril Wu, research manager of DRAMeXchange. “At the same time, suppliers do not appear to have plans to expand their production capacities in a significant scale between now and the end of the year.” The global DRAM revenue has thus kept growing, registering a 16.9% sequential increase for this second quarter.

In the third quarter, the releases of new flagship devices from first-tier smartphone brands, together with the traditional peak sales season, will trigger another wave of mobile DRAM demand. DRAM prices in general will stay on an upward trend for the remainder of 2017.

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The second-quarter revenue ranking shows Samsung firmly in its first place position. Samsung’s revenue for the second quarter came to another historical high, growing by 20.7% sequentially to US$7.6 billion. Second-place SK Hynix also posted an impressive sequential increase of 11.2%, totaling US$4.5 billion. Samsung’s and SK Hynix’s global market shares for the second quarter were 46.2% and 27.3%, respectively. Together, the two South Korean suppliers accounted for 73.5% of the world’s DRAM market. Third-place Micron’s second-quarter revenue totaled US$3.6 billion, an increase of 20.2% versus the first quarter and representing 21.6% of the global market.

In terms of operating margins, Samsung had the highest in the industry for the second quarter at 59%. Samsung benefitted from rising DRAM prices and its lead in manufacturing technology. Likewise, SK Hynix raised its operating margin from 47% in the first quarter to 54% in the second. Micron too increased its operating margin from 32.5% to 44.3% between the quarters. Since DRAM prices will keep rising and the production capacity expansion will be limited in the second half of 2017, suppliers can expect further increases in their operating margins.

In the aspect of technology migration, Samsung remains focused on developing its 18nm process. With the increase and stabilization of the yield rate, Samsung expects the 18nm to represent nearly half of its total DRAM output by the end of 2017. As for SK Hynix, the supplier is raising the yield rate and output share of its 21nm process. However, SK Hynix has also arranged for the mass production its 18nm process at the end of 2017. By the first half of 2018, SK Hynix wants to significant expand the DRAM production based on its 18nm technology.

Micron’s Taiwanese subsidiaries Micron Memory Taiwan and Micron Technology Taiwan (formerly known as Inotera) are respectively on the 17nm and the 20nm technology. Micron Memory Taiwan has steadily increased the yield rate for its 17nm process and expects at least 80% of its total DRAM output by the end of this year will be based on this technology. Micron Technology Taiwan, on the other hand, has no plan to transition to a more cutting edge technology this year. However, this subsidiary has set the target of attaining at least 50% output share for the 17nm process in 2018.

Regarding the Taiwanese DRAM suppliers, Nanya’s second-quarter revenue grew by 5.9% sequentially on the back of rising prices for specialty DRAM products. Nanya has formally begun mass producing DRAM on its 20nm process and is on track to achieve a total DRAM capacity of 30,000 wafer starts per month by the end of 2017.

Powerchip’s DRAM revenue for the second quarter fell by 2.5% compared with the prior quarter because of wafer loss caused by the moving of its 25nm processing equipment.

Winbond’s second-quarter DRAM revenue rose by 3.7% sequentially as the supplier also profited from rising prices for specialty DRAM products. Winbond has no immediate plan to increase DRAM wafer starts as it is focused on meeting the strong NOR Flash demand. However, the supplier has scheduled the mass production of DRAM on its 38nm technology for the second half of 2017. The increase in output due to the ramp-up of the 38nm process will make a positive contribution to Winbond’s future DRAM revenue results.

Chipmakers want every part of the wafer to produce, or yield, good die. Advances in process technologies over the years have just about made this a reality, even as feature dimensions continue to shrink and devices grow ever more complex. Now, the last frontier is improving yields at the edge of the wafer – the outer 10 mm or so – where chemical, physical, and even thermal discontinuities are simply much harder to control. Complicating matters, current strategies used to manage these edge issues involve tradeoffs between yield and manufacturing costs that result in less than ideal fab economics. At Lam, our technologists have been working on solutions to this challenge, and today, we released the new Corvus™ edge control technology for our Kiyo® conductor etch products to address these very issues and enhance edge yield.

Edge Challenges

Taking a closer look at the wafer’s edge, where up to ~10% of the die may be located, there are several issues at play that can impact yield. In all plasma etch reactors, the abrupt end of the wafer surface creates inherent electrical discontinuities at the edge region, forming voltage gradients that bend the plasma sheath. This, in turn, changes the direction of the plasma’s components (ions and neutrals), which impacts etch results and causes unwanted variability. In the case of 3D NAND devices, for example, this change in the plasma conditions at the wafer’s edge can cause tilted etch profiles or prevent features from being completely etched. In addition to affecting tilt angle, these edge effects can result in non-uniform critical dimensions (CDs) or changes in local overlay metrics.

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Another challenge is that process drift creates CD uniformity and selectivity problems over time. As a way to manage this, chipmakers often add more chamber wet cleans to restore the equipment to a standard condition. However, this approach significantly reduces productivity because the chamber is not available for processing wafers during this maintenance. In addition, as process margins get tighter, more frequent wet cleans are required, which increases operational costs.

Corvus Solution

Lam’s new Corvus technology provides a novel capability to smooth out extreme edge discontinuities and enhance edge performance. It offers the ability to tune the plasma sheath at the edge to produce a constant, user-defined etch rate and ion angle. For example, etch rate can be tuned to be faster or slower at the edge relative to the rate over the rest of the wafer. With 3D NAND applications, Corvus technology has demonstrated the ability to minimize plasma sheath drift, preventing detrimental feature tilting at the wafer’s edge. Tuning to within 1.5 mm of the edge, the new technology can correct for inherent process variation in the edge region as well as for incoming film variations to optimize die yield. Furthermore, with Corvus, every wafer sees the same edge conditions for optimal yield, eliminating previously seen systematic wafer-to-wafer yield variability.

Corvus technology not only improves across-wafer uniformity, it also greatly reduces wafer-to-wafer and chamber-to-chamber variability and eliminates the historical tradeoffs among yield, operational flexibility, and cost. Customers have reported die yield improvements of 0.5-2% per wafer, which can be a significant advantage – especially when you consider how many thousands of wafers chipmakers process every day. Additionally, Corvus has demonstrated the ability to provide higher and more consistent yield over a longer period. It also greatly enhances productivity and lowers overall fab operating costs for high-volume manufacturing by requiring fewer chamber wet cleans. The new technology is being used for advanced patterning, mask open, and other challenging conductor etch applications where reducing variation in CD, profile, or selectivity and improving productivity helps enable continued scaling.

The new capability provided by Corvus complements Lam’s Hydra® technology, which enables fine tuning of within-wafer uniformity and actively compensates for incoming variation. Together, these advanced process control technologies are reducing variability across the entire wafer surface, improving yield, and enabling the production of next-generation logic and memory devices.

Welch Foundation, the Army Research Office and the National Science Foundation supported the research.

The Rice laboratory of materials scientist Jun Lou has made a semiconducting transition-metal dichalcogenide (TMD) that starts as a monolayer of molybdenum diselenide. They then strip the top layer of the lattice and replace precisely half the selenium atoms with sulfur.

The new material they call Janus sulfur molybdenum selenium (SMoSe) has a crystalline construction the researchers said can host an intrinsic electric field and that also shows promise for catalytic production of hydrogen.

The work is detailed this month in the American Chemical Society journal ACS Nano.

The two-faced material is technically two-dimensional, but like molybdenum diselenide it consists of three stacked layers of atoms arranged in a grid. From the top, they look like hexagonal rings a la graphene, but from any other angle, the grid is more like a nanoscale jungle gym.

Tight control of the conditions in a typical chemical vapor deposition furnace — 800 degrees Celsius (1,872 degrees Fahrenheit) at atmospheric pressure — allowed the sulfur to interact with only the top layer of selenium atoms and leave the bottom untouched, the researchers said. If the temperature drifts above 850, all the selenium is replaced.

“Like the intercalation of many other molecules demonstrated to have the ability to diffuse into the layered materials, diffusion of gaseous sulfur molecules in between the layers of these Van der Waals crystals, as well as the space between them and the substrates, requires sufficient driving force,” said Rice postdoctoral researcher Jing Zhang, co-lead author of the paper with graduate student Shuai Jia. “And the driving force in our experiments is controlled by the reaction temperature.”

Close examination showed the presence of sulfur gave the material a larger band gap than molybdenum diselenide, the researchers said.

“This type of two-faced structure has long been predicted theoretically but very rarely realized in the 2-D research community,” Lou said. “The break of symmetry in the out-of-plane direction of 2-D TMDs could lead to many applications, such as a basal-plane active 2-D catalyst, robust piezoelectricity-enabled sensors and actuators at the 2-D limit.”

He said preparation of the Janus material should be universal to layered materials with similar structures. “It will be quite interesting to look at the properties of the Janus configuration of other 2-D materials,” Lou said.

 

The next generation of feature-filled and energy-efficient electronics will require computer chips just a few atoms thick. For all its positive attributes, trusty silicon can’t take us to these ultrathin extremes.

Now, electrical engineers at Stanford have identified two semiconductors – hafnium diselenide and zirconium diselenide – that share or even exceed some of silicon’s desirable traits, starting with the fact that all three materials can “rust.”

“It’s a bit like rust, but a very desirable rust,” said Eric Pop, an associate professor of electrical engineering, who co-authored with post-doctoral scholar Michal Mleczko a paper that appears in the journal Science Advances.

The new materials can also be shrunk to functional circuits just three atoms thick and they require less energy than silicon circuits. Although still experimental, the researchers said the materials could be a step toward the kinds of thinner, more energy-efficient chips demanded by devices of the future.

Silicon’s Strengths

Silicon has several qualities that have led it to become the bedrock of electronics, Pop explained. One is that it is blessed with a very good “native” insulator, silicon dioxide or, in plain English, silicon rust. Exposing silicon to oxygen during manufacturing gives chip-makers an easy way to isolate their circuitry. Other semiconductors do not “rust” into good insulators when exposed to oxygen, so they must be layered with additional insulators, a step that introduces engineering challenges. Both of the diselenides the Stanford group tested formed this elusive, yet high-quality insulating rust layer when exposed to oxygen.

Not only do both ultrathin semiconductors rust, they do so in a way that is even more desirable than silicon. They form what are called “high-K” insulators, which enable lower power operation than is possible with silicon and its silicon oxide insulator.

As the Stanford researchers started shrinking the diselenides to atomic thinness, they realized that these ultrathin semiconductors share another of silicon’s secret advantages: the energy needed to switch transistors on – a critical step in computing, called the band gap – is in a just-right range. Too low and the circuits leak and become unreliable. Too high and the chip takes too much energy to operate and becomes inefficient. Both materials were in the same optimal range as silicon.

All this and the diselenides can also be fashioned into circuits just three atoms thick, or about two-thirds of a nanometer, something silicon cannot do.

“Engineers have been unable to make silicon transistors thinner than about five nanometers, before the material properties begin to change in undesirable ways,” Pop said.

The combination of thinner circuits and desirable high-K insulation means that these ultrathin semiconductors could be made into transistors 10 times smaller than anything possible with silicon today.

“Silicon won’t go away. But for consumers this could mean much longer battery life and much more complex functionality if these semiconductors can be integrated with silicon,” Pop said.

More to do

There is much work ahead. First, Mleczko and Pop must refine the electrical contacts between transistors on their ultrathin diselenide circuits. “These connections have always proved a challenge for any new semiconductor, and the difficulty becomes greater as we shrink circuits to the atomic scale,” Mleczko said.

They are also working to better control the oxidized insulators to ensure they remain as thin and stable as possible. Last, but not least, only when these things are in order will they begin to integrate with other materials and then to scale up to working wafers, complex circuits and, eventually, complete systems.

“There’s more research to do, but a new path to thinner, smaller circuits – and more energy-efficient electronics – is within reach,” Pop said.

Additional Stanford contributors to this research include: Chaofan Zhang, Hye Ryoung Lee, Hsueh-Hui Kuo, Blanka Magyari-Köpe, Robert G. Moore, Zhi-Xun Shen, Ian R. Fisher, and Professor Yoshio Nishi.

The work was supported by the Air Force Office of Scientific Research (AFOSR), the National Science Foundation, Stanford Initiative for Novel Materials and Processes (INMP), the Department of Energy (DOE) Office of Basic Energy Sciences, Division of Material Sciences, and an NSERC PGS-D fellowship.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today released the following statement from President & CEO John Neuffer in response to the Trump Administration’s decision to set in motion a process led by the United States Trade Representative to investigate China’s unfair trade practices.

“The U.S. semiconductor industry stands ready to work with the Trump Administration to protect American intellectual property and critical technology from theft or forced transfer in foreign markets.

“Intellectual property is the lifeblood of the semiconductor industry. Semiconductors are America’s fourth-largest export and underpin the entire economy. U.S. semiconductor companies invest nearly one-fifth of their revenue in research and development to stay at the forefront of innovation, and they should be able to compete in foreign markets without putting their critical IP at risk.

“While China is an important part of the global semiconductor value chain, SIA has long raised concerns about market-distorting aspects of its state-led industrial policy – such as forced technology transfer practices – that disadvantage U.S. companies and imperil their IP. A balanced, fair, objective, and thorough investigation aimed at ensuring that China meets its global trading obligations and that market forces determine competitive outcomes will be helpful to address these market-access issues.  

“The U.S. semiconductor industry looks forward to working with the Administration to address these challenges. Further, we expect this review will seek to find solutions consistent with international trading obligations and help ensure lasting American leadership in semiconductor technology.”

Top five product segments driving the first annual double-digit IC market upturn since 2010.

IC Insights has revised its outlook and analysis of the IC industry and presented its new findings in the Mid-Year Update to The McClean Report 2017, which originally was published in January 2017. Among the revisions is a complete update of forecast growth rates of the 33 main product categories classified by the World Semiconductor Trade Statistics organization (WSTS).

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Figure 1 shows the complete ranking of IC products by forecasted growth rate for 2017. Topping the chart of fastest-growing products is DRAM, which comes as no surprise given the strong rise of average selling prices in this segment throughout the first half of 2017.  IC Insights now expects the DRAM market to increase 55% in 2017 and lay claim as the fastest-growing IC product segment this year. This is not unfamiliar territory for the DRAM market.  It was also the fastest-growing IC segment in 2013 and 2014. Remarkably, DRAM has been at the top and near the bottom of this list over the past five years, demonstrating its extremely volatile nature (Figure 2).

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The Industrial/Other Special Purpose Logic segment is projected to grow 32% and two automotive-related IC categories—Automotive Special Purpose Logic (48%) and Automotive Application Specific Analog (18%)—are also on course for growth that will exceed the 16% expected of the total IC market. There are more IC categories that are forecast to show positive growth in 2017 (29) compared to 2016 (21), but only the top five market segments mentioned above are forecast to exceed the total IC market growth in 2017, indicating top-heavy market growth. Another five segments (two analog categories, two MCU segments, and Computer and Peripherals—Special Purpose Logic) are forecast to show double-digit growth in 2017, though less than the 16% forecast for the total IC market this year.

Additional details and discussion regarding the updated IC forecasts for the 2017-2021 timeperiod are covered in IC Insights’ Mid-Year Update to The McClean Report 2017.

The global semiconductor advanced packaging market is expected to grow at a CAGR of 8.45% during the period 2017-2021, according to the “Global Semiconductor Advanced Packaging Market 2017-2021” report by Research and Markets.

The latest trend gaining momentum in the market is changes in wafer size. The semiconductor industry has seen a drastic transition in wafer size over the last five decades (1910-2016). The industry is focusing on producing larger diameter wafers, which is expected to cut down the manufacturing cost by 20%-25%.

According to the report, one of the other major drivers for this market is complex semiconductor IC designs. The number of features and functionalities offered by consumer electronic devices is on the rise as electronic device manufacturers look to differentiate their offerings from those of competitors.

Further, the report states that one of the major factors hindering the growth of this market is rapid technological changes. The rapid technological advancements in wafer processing have always been a major challenge faced by vendors in the semiconductor advanced packaging market. The semiconductor industry is continuously seeing transitions, such as the miniaturization of nodes and the increase in wafer sizes with respect to ultra-large-scale integration (ULSI) fabrication technology.

Vacuum pumps, pressure gauges and vacuum valves combined make up the biggest expense on the bill of materials for semiconductor OEMs. In 2016, just over $1.9 billion of vacuum subsystems were consumed by the semiconductor industry and more than half were supplied by European vendors, according to VLI Research.

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Vacuum subsystems sales account for one third of expenditures on all critical subsystems used on semiconductor manufacturing equipment (excluding optical subsystems). The increase in vacuum process intensity of the semiconductor industry means that by 2022, the market for vacuum subsystems could be up to 62 percent higher than today’s value of $1.9 billion, reaching a market size of $3.1 billion.

The growing number of vacuum process steps has been driven by multiple patterning and the successful introduction of 3D NAND. Both require additional deposition and etch steps and, in the case of 3D NAND, longer and more difficult etch processes. On the negative side, this has increased costs for chipmakers and is driving the adoption of Extreme Ultraviolet lithography (EUV) which reduces the reliance on multiple patterning. However, even with EUV (which is a vacuum process), the number of deposition and etch steps are still expected to increase, albeit at a lower rate. This explains why the forecast is for sales of vacuum subsystems to outgrow the market over the next five years.

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The top five vacuum subsystem suppliers account for 68 percent of the market and is dominated by four European based vendors. In 2016, over 58 percent of all vacuum subsystems were sold by European companies and is a reflection of the European origins of vacuum technology. The Japanese vendors as a group make up 21 percent of the total while North American vendors supply 16 percent.

There is a push for more localisation of vacuum subsystem supply especially in Korea and China but to date this has not resulted in a serious local supplier emerging to challenge the incumbents. The strong hold that Europeans and Japanese have on the technology mean that we are unlikely to see any meaningful regional shifts in supply in the foreseeable future.

The expectation is that vacuum subsystems suppliers will continue to make a valuable contribution to semiconductor manufacturing over the long-term as the trend for more vacuum process steps continues.