Category Archives: Semiconductors

By Paul Trio

SCIS is a SEMI Technology Community that tackles critical component defectivity for the semiconductor manufacturing industry. The organization develops test methods for measuring defects in these critical components. Originally, this SEMI community was looking at challenges surrounding sub-10nm process nodes, but our constituents – Integrated Device Manufacturers (IDMs), capital equipment OEMs, and (sub)component suppliers – felt that the immediate need was for standards that would apply to process nodes that are already being used for volume semiconductor device manufacturing.

IDMs need ways to tell their supply chain how defects attributable to these critical components factor into the overall process-node defect budgets and wafer-contamination limits. Chipmakers and IDMs needed to start with a baseline: How problematic are existing critical components in the overall fab systems and how do these contaminants contribute to defects and how do they affect overall process yields?

These questions must be answered for every component in the fab’s process line including the drums that hold the fab chemistries, fluid delivery systems, and components used in the wafer-processing chamber. All of these critical fab-line components come into contact with each manufactured wafer, in one way or another, and each is a suspect with respect to contamination, defects, and yield problems. SCIS develops test methods for these fab-line critical components testing that are used to identify the defects caused by these components and for establishing baselines.

SCIS has seven working groups dealing with various critical components. Each is developing various test methods for many critical fab-line components. There are many facets with respect to testing each of these critical components.

Take something as simple as a seal, such as an FFKM (perfluoroelastomer, made from polymers) seal. These seals are ubiquitous in fab lines. In harsher environments, such as inside of a processing chamber, these seals are exposed to high temperatures and harsh chemistries. Different FFKM seals will have different characteristics such as thermal resistivity and chemical resistance, depending on customer specifications, and can also vary from one manufacturer to another. In addition, these characteristics can change depending on environmental conditions – or just the passage of time.

SCIS looks at defect traits from the perspective of each component in the fab line and decides which of the components’ parameters contribute most to process defects. Initially, the SCIS Seals & Valves Group collected a list of seal-related issues or parameters. The working group then cross-checked these parameters against different manufacturing processes used in the fab including ALD (atomic layer deposition) and CVD (chemical vapor deposition). Some processes are harder on seals than others. Then the working group prioritized these various parameters according to their contribution to the overall process defect budget. IDMs provided important input during these steps because they work with these seals on a daily basis. At this point, the SCIS working group had a prioritized list of parameters, vetted by various stakeholders in the semiconductor manufacturing industry. The group then set to develop standardized measurement methods for these critical parameters.

Based on this work, the SCIS Seals & Valves Group has already published two documents. The first is a standard that specifies methods for testing seal-induced impurities such as ashing (analysis of metals content of the ash) and TOC (total organic content).

The second document published by the Seals & Valves Group is a guide that documents BKMs (best known methods) for handling seals – from the moment they’re cured in an oven to packaging, shipping, handling in a fab, and installation – a to reduce contamination problems during use. For example, some seals are sensitive to light. Some polymer seals degrade when they come into contact with IPA (isopropyl alcohol), which is often used for prepping. A degraded seal can emit contamination particles during processing, which will cause yields to fall. (This latter bit of information came directly from a major IDM, which demonstrates the invaluable role that users of these components can play in the development of testing standards.)

The Seals & Valves Group’s current work focuses on developing a standard for measuring seal leak rates. This standard will define test methods for evaluating a seal’s ability to maintain pressure under vacuum. Although there are well-established standard for testing seal CSR (compressive stress relaxation) in the aerospace industry, there’s no such standard for the semiconductor industry. So originally, the Seals & Valves Group tried to tackle that challenge by developing a similar standard for SEMI’s constituents. However, a more practical and immediate parametric challenge turned out to be seal leakage rates.

Installed seals are exposed to high temperatures and harsh chemistries in the semiconductor fabrication process. The Seals & Valves Group decided to develop a test method that would determine how well seals perform over time with respect to leakage rates as the seals are exposed to cyclic harsh conditions. The goal is to simulate the working conditions for these seals, as closely as possible and in a repeatable manner.

There are, of course, some challenges associated with this work. For example, IDMs and equipment OEMs don’t want to reveal their exact process conditions as they are proprietary. So the Seals & Valves Group took a step back and focused on developing a test method based solely on exposure to elevated temperatures.

Development of this thermal test requires the design of a standardized test jig to help ensure consistent, repeatable tests, shown in Figure 1.

Figure 1: Elastomer seal test jig developed by the SCIS Seals & Valves Group.

The seal under test, shown in red in Figure 1, sits at the center of the jig. A second seal, shown in green, is used to seal the actual test environment. Two thermocouples in the jig’s top and bottom monitor of the temperature inside of the jig. There are gas and purge lines for controlling the ambient pressures on either side of the seal under test.

Figure 2 illustrates how the jig is connected to the gas sources.

Figure 2: The Seals Test Jig is connected to helium and nitrogen gas sources and to a calibrated leak (vacuum) line.

The seals leak test is based on a helium leak test. Helium is one of the smallest atoms so it will leak through just about any small gap and, with time, permeate through the material as well. In addition, helium is inert, and testing for helium using a mass spectrometer is a well-established technique for leak testing. Helium leak testing can be one thousand to one million times more sensitive than using mechanical, pressure-decay test techniques. The jig’s nitrogen lines serve to purge the test chambers of helium between leak tests.

Developing just a test jig is not sufficient. The Seals & Valves Group also developed a test sequence for using the jig. There were no existing standard, so the group needed to use its knowledge of the seals’ composition and operating conditions to develop certain test parameters. For example, the group elected to use 200°C as the maximum temperature for the high-temperature portion of the test because FFKM seals start to degrade at 250°C.

At this point, the Seals & Valves Group has gone through several iterations of a proposed test sequence. There was some initial reluctance to provide detailed inputs, but after a few iterations of the proposed method (and an understanding that this would become an industry standard to hold suppliers accountable), inputs have become more forthcoming.

This is an excellent example that demonstrates why it’s so important for SCIS working groups to get chipmakers, IDMs, component vendors, and even feedstock materials vendors to participate in these standardization efforts. Standards are far more useful if they’re based on real-world conditions.

Currently, the SCIS Seals & Valves Group is working towards finalizing the seals-leak test sequence. The jig has been designed in AutoCAD and a prototype will soon be manufactured. Although the test and jig have been developed with significant industry participation, the validity of the test has yet to be determined. The validity will be verified though Alpha testing before the jig design and test method are incorporated into a standard.

However, SEMI is not a test house. It’s a facilitator. The testing will therefore be performed by a neutral third party capable of carrying out the test under fab-like conditions. SEMI’s role is to work with different testing entities such as SUNY Polytechnic Institute in Utica, New York or IMEC in Belgium.

SEMI will solicit bids for this work through its SCIS Executive Advisory Committee, which consists of C-level executives from device makers, semiconductor capital equipment OEMs, and major critical component suppliers. This project has leveraged many of the relationships that SEMI has developed over the years and has broken new ground in standards making for SCIS and for SEMI.

For those looking to learn more about SCIS or engage in ongoing efforts, please contact Paul Trio, senior manager of Strategic Initiatives at SEMI, at [email protected].

IC Insights is in the process of completing its forecast and analysis of the IC industry and will present its new findings in The McClean Report 2019, which will be published later this month.  Among the semiconductor industry data included in the new 400+ page report is an in-depth analysis of the IC foundry market and its suppliers.

With the recent rise of the fabless IC companies in China, the demand for foundry services has also risen in that country.  In total, pure-play foundry sales in China jumped by 30% in 2017 to $7.6 billion, triple the 9% increase for the total pure-play foundry market that year.  Moreover, in 2018, pure-play foundry sales to China surged by an amazing 41%, over 8x the 5% increase for the total pure-play foundry market last year.

As a result of a 41% increase in the China pure-play foundry market last year, China’s total share of the 2018 pure-play foundry market jumped by five percentage points to 19% as compared to 2017, exceeding the share held by the rest of the Asia-Pacific region (Figure 1).  Overall, China was responsible for essentially all of the total pure-play foundry market increase in 2018!

All of the major pure-play foundries registered double-digit sales increases to China last year, but the biggest increase by far came from pure-play foundry giant TSMC.  Following a 44% jump in 2017, TSMC’s sales into China surged by another 61% in 2018 to $6.0 billion.  The China market was responsible for essentially all of TSMC’s sales increase last year with China’s share of the company’s sales doubling from 9% in 2016 to 18% in 2018.

A great deal of TSMC’s sales surge into China in 2018 was driven by increased demand for custom devices going into the cryptocurrency market.  While TSMC enjoyed a great ramp up in sales for its cryptocurrency business through 2Q18, the company encountered a slowdown for this business in the second half of last year, which was apparent in its slower sales to China in 3Q18 and 4Q18.  The 2018 plunge in the price of Bitcoins (from over $15K per Bitcoin in January of 2018 to less than $4K in December of 2018) and other cryptocurrencies lowered the demand for these ICs.

Figure 1

With China’s share of the pure-play foundry market quickly growing (going from representing 11% of the total pure-play foundry market in 2015 to a 19% share in 2018) it comes as no surprise that many of the pure-play foundries are planning to locate or expand IC production in Mainland China.  Notably, each of the top seven pure-play foundries has plans for increasing China-based wafer fabrication production, including the five non-Chinese foundries of TSMC, GlobalFoundries, UMC, Powerchip, and TowerJazz

SEMI and imec are joining forces to drive innovation and deepen industry alignment on technology roadmaps and international standards while adding technology depth to SEMI’s five vertical application platforms including Smart Transportation, Smart MedTech and Smart Data.

Under a Memorandum of Understanding announced today at ISS 2019, the two organizations have set their sights on bringing together key industry players to advance cutting-edge technologies including Internet of Things (IoT), artificial intelligence (AI) and machine learning that enable new capabilities across healthcare, automotive and semiconductor manufacturing. The partnership also aims to speed the time to better business results for SEMI and imec members and partners.

SEMI brings to the partnership access to the $2 trillion global electronics manufacturing supply chain and imec its global research and development (R&D) and innovation leadership in nanoelectronics and digital technologies.

Under the MOU, the two organizations will co-produce SEMI Think Tanks, extend SEMI’s International Standards platform to non-CMOS technologies, identify and fill gaps in technology roadmaps, and tighten imec’s engagement with SEMI in European workforce development efforts.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $41.4 billion for the month of November 2018, an increase of 9.8 percent from the November 2017 total of $37.7 billionand 1.1 percent less than the October 2018 total of $41.8 billion. Monthly sales are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“The global semiconductor industry continues to post solid year-to-year sales increases, and year-to-date revenue through November has surpassed annual sales from all of 2017, but growth has slowed somewhat in recent months,” said John Neuffer, SIA president and CEO. “Year-to-year sales increased in November across all major regional markets, with the China market standing out with growth of 17 percent. Double-digit annual growth is expected for 2018 once December’s sales are tallied, with more modest growth projected for 2019.”

Regionally, year-to-year sales increased in China (17.4 percent), the Americas (8.8 percent), Europe (5.8 percent), Japan(5.6 percent), and Asia Pacific/All Other (4.4 percent). Compared with last month, sales were up in Asia Pacific/All Other (1.1 percent), Europe (0.5 percent), and Japan (0.4 percent), but down slightly in the Americas (-2.2 percent) and China(-2.7 percent).

UNSW researchers at the Centre of Excellence for Quantum Computation and Communication Technology (CQC2T) have shown for the first time that they can build atomic precision qubits in a 3D device – another major step towards a universal quantum computer.

The team of researchers, led by 2018 Australian of the Year and Director of CQC2T Professor Michelle Simmons, have demonstrated that they can extend their atomic qubit fabrication technique to multiple layers of a silicon crystal – achieving a critical component of the 3D chip architecture that they introduced to the world in 2015. This new research was published today in Nature Nanotechnology.

The group is the first to demonstrate the feasibility of an architecture that uses atomic-scale qubits aligned to control lines – which are essentially very narrow wires – inside a 3D design.

What’s more, the team was able to align the different layers in their 3D device with nanometer precision – and showed they could read out qubit states single shot, i.e. within one single measurement, with very high fidelity.

“This 3D device architecture is a significant advancement for atomic qubits in silicon,” says Professor Simmons. “To be able to constantly correct for errors in quantum calculations – an important milestone in our field – you have to be able to control many qubits in parallel.

“The only way to do this is to use a 3D architecture, so in 2015 we developed and patented a vertical crisscross architecture. However, there were still a series of challenges related to the fabrication of this multi-layered device. With this result we have now shown that engineering our approach in 3D is possible in the way we envisioned it a few years ago.”

In this paper, the team has demonstrated how to build a second control plane or layer on top of the first layer of qubits.

“It’s a highly complicated process, but in very simple terms, we built the first plane, and then optimized a technique to grow the second layer without impacting the structures in first layer,” explains CQC2T researcher and co-author, Dr Joris Keizer.

“In the past, critics would say that that’s not possible because the surface of the second layer gets very rough, and you wouldn’t be able to use our precision technique anymore – however, in this paper, we have shown that we can do it, contrary to expectations.”

The team also demonstrated that they can then align these multiple layers with nanometer precision.

“If you write something on the first silicon layer and then put a silicon layer on top, you still need to identify your location to align components on both layers. We have shown a technique that can achieve alignment within under 5 nanometers, which is quite extraordinary,” Dr Keizer says.

Lastly, the researchers were able to measure the qubit output of the 3D device with what’s called single shot – i.e. with one single, accurate measurement, rather than having to rely on averaging out millions of experiments. “This will further help us scale up faster,” Dr Keizer explains.

Towards commercialisation

Professor Simmons says that this research is a major milestone in the field.

“We are working systematically towards a large-scale architecture that will lead us to the eventual commercialisation of the technology.

“This is an important development in the field of quantum computing, but it’s also quite exciting for SQC,” says Professor Simmons, who is also the founder and a director of SQC.

Since May 2017, Australia’s first quantum computing company, Silicon Quantum Computing Pty Limited (SQC), has been working to create and commercialise a quantum computer based on a suite of intellectual property developed at CQC2T and its own proprietary intellectual property.

“While we are still at least a decade away from a large-scale quantum computer, the work of CQC2T remains at the forefront of innovation in this space. Concrete results such as these reaffirm our strong position internationally,” she concludes.

Unwavering in its drive to build a strong, self-sufficient semiconductor supply chain, China plans more new fab projects than any other region in the world from 2017 to 2020, and its expansion of fab capacity recently picked up pace on the strength of new foundry and memory projects from both domestic and foreign companies, according to SEMI’s 2018 China Semiconductor Silicon Wafer Outlook report. China’s installed fab capacity is forecast to grow at a 12 percent CAGR from 2.3 million wafers per month (wpm) in 2015 to 4 million wpm in 2020, faster than all other regions.

Well known for its semiconductor packaging prowess, China in recent years shifted its focus to front-end semiconductor fabs and a few key material markets. In 2018, the region’s surge in fab investment thrust it past Taiwan as the second largest capital equipment market in the world, behind only Korea.

However, China’s semiconductor manufacturing growth faces strong headwinds. Chief among them is the tight supply of silicon wafers over the past two years due in large part to the sector oligopoly’s firm control of global production, with the top five wafer manufacturers accounting for over 90 percent of market revenue. In response, China’s central and local governments has made the development of its domestic silicon wafer supply chain a key initiative, funding multiple silicon wafer manufacturing projects.

According to the 2018 China Semiconductor Silicon Wafer Outlook report, many of China’s domestic silicon suppliers capably provide wafers 150mm in size and smaller. And the while the region lags peers in 200m and 300mm processing technology and capacity, strong domestic demand and favorable policies have fueled progress in 200mm and 300mm silicon manufacturing with some Chinese suppliers having reached key large-diameter manufacturing milestones.

However, it will take these new suppliers several years before they can meet capacity and yield requirements of the larger-diameter silicon wafer market. Company plans and announcements indicate that by the end of 2020, total silicon supply capacity in China will reach 1.3 million wpm for 200mm, possibly leading to a slight oversupply, and 750,000 wpm for 300mm.

China’s equipment suppliers, particularly crystal furnace vendors, are also investing in the development of 300mm wafer manufacturing, and domestic tool suppliers have developed most of the necessary tools for wafer manufacturing, except for inspection.

While China’s silicon wafer suppliers continue to lag international peers in manufacturing capabilities, the region’s silicon manufacturing ecosystem is maturing and becoming better integrated. The sector’s growth is driven and accelerated by significant domestic market demand and favorable policies.

MagnaChip Semiconductor Corporation (“MagnaChip” or the “Company”) (NYSE: MX), a designer and manufacturer of analog and mixed-signal semiconductor products, announced today it now offers foundry customers its third generation 0.18 micron Bipolar-CMOS-DMOS (BCD) process technology. The technology is highly suitable for PMIC, DC-DC converters, battery charger ICs, protection ICs, motor driver ICs, LED driver ICs and audio amplifiers. The third generation 0.18 micron BCD process technology offers improved specific on-resistance (Rsp) of power LDMOS (Laterally Diffused Metal Oxide Semiconductor) that operates up to 40V with simplified manufacturing steps.

Demand is increasing for high-performance and power-efficient Power ICs processed in BCD technology in order to reduce the number of components in power modules by having multiple functions in one chip. In BCD technologies, the Rsp characteristics of power LDMOS is a key performance parameter because BCD technology with lower Rsp LDMOS helps reduce chip size and power loss of power ICs. MagnaChip has been improving the Rsp of power LDMOS for last ten years. Now, by process and device architecture optimization, MagnaChip’s third generation 0.18 micron BCD process technology reduces the Rsp by approximately 30%, as compared to the previous generation.

BCD technology requirements vary for different applications and IC design schemes. To cover various requirements, MagnaChip adopted the modular process concept that can generate diverse combinations of 1.8V, 5V, and 12~40V transistors. In addition to the current device combinations, MagnaChip intends to release new devices in 2019, such as:  tailored LDMOS devices optimized for a specific range of operational voltages and LDMOS devices with low Vgs (bias between gate to source) that are suitable for power ICs with strict operational voltage limits and other operating at high frequencies.

The third generation BCD process technology offers various optional devices to enhance design integration and flexibility. The optional devices include a high performance bipolar transistor, Zener diode, high resistance poly resistor with no additional photo layer, tantalum nitride resistor with low temperature coefficient, metal-insulator-metal capacitor, metal-oxide-metal capacitor, electrical fuse, and multi-time programmable memory.

To support power ICs for more stringent reliability requirements, as in automotive applications, this third generation BCD process technology was qualified based on the automotive grade qualification specification of AEC-Q100 with Grade1 temperature conditions between -40 to 125 °C.

YJ Kim, Chief Executive Officer of MagnaChip, commented, “Our third generation 0.18 micron BCD process technology with low specific on-resistance is highly suitable for many power IC applications because it helps  reduce  chip size and improve power efficiency. And we will continue to improve the performance of our BCD technology, as it will help our customers increase the competitiveness of their products.”

Today, Mobile Semiconductor announced their new 22nm FDX ULP (Ultra Low Power) Memory Compiler complete with a comprehensive set of features that cement their leadership position in FDX Memory Compiler offerings.

This new Memory Compiler offers an Ultra-Low Power mode at 0.65V that is useful to a wide range of wearable and battery powered devices.  The 22nm FDX ULP joins their expanding 22nm FDX Memory Compiler family that currently covers a wide range of speeds, power requirements, and ultra-low leakage offerings.  The 22nm ULP product draws from the expertise developed over the past three years with our successful 28nm and 55nm Memory Compilers.

Cameron Fisher, CEO and Founder of Mobile Semiconductor, said, “We believe our approach to anticipating the needs of engineers, and building in industry leading features, set us apart.  Examples mentioned by current customers includes low power level shifters and isolation cells.  Without these features, the designer cannot power off the memory entirely resulting in wasted energy and a substandard product.  Mobile Semiconductor Memory Compilers truly allow for complete power down and rapid start-up.”

The Mobile Semiconductor / GlobalFoundries 22FDX platform include 100% of what a design team demands:

  • 0.65V and 0.5V Logic Support
  • Integrated Power Solutions
  • Output Isolation
  • Multiple Power Modes
  • Single Port and Register File Compilers
  • Pseudo Dual Port Support
  • Flexible Reverse Body Bias Support

Fisher continued, “Mobile Semiconductor remains the leader in providing low power memory complier solutions.  But it’s not enough to have a feature rich offering on one product like the 22nm FDX ULP, we also believe that it’s our obligation to provide a range of other products such as 28nm and 55nm AND to design them with the features that best support the demands of the market segments.”

IBM (NYSE:  IBM) today announced an agreement with Samsung to manufacture 7-nanometer (nm) microprocessors for IBM Power Systems, IBM Z and LinuxONE, high-performance computing (HPC) systems, and cloud offerings.

The agreement combines Samsung’s industry-leading semiconductor manufacturing with IBM’s high-performance CPU designs. This combination is being designed to drive unmatched systems performance, including acceleration, memory and I/O bandwidth, encryption and compression speed, as well as system scaling. It positions IBM and Samsung as strategic partners leading the new era of high-performance computing specifically designed for AI.

“At IBM, our first priority is our clients,” said John Acocella, Vice President of Enterprise Systems and Technology Development for IBM Systems. “IBM selected Samsung to build our next generation of microprocessors because they share our level of commitment to the performance, reliability, security, and innovation that will position our clients for continued success on the next generation of IBM hardware.”

Today’s announcement also expands and extends the 15-year strategic process technology R&D partnership between the two companies which, as part of IBM’s Research Alliance, includes many industry firsts such as the first NanoSheet Device innovation for sub 5nm, the production of the industry’s first 7nm test chip and the first High-K Metal Gate foundry manufacturing. IBM’s Research Alliance ecosystem continues to define the leadership roadmap for the semiconductor industry.

“We are excited to expand our decade-long strategic relationship with IBM with our 7nm EUV process technology,” said Ryan Lee, Vice President of Foundry Marketing at Samsung Electronics. “This collaboration is an important milestone for Samsung’s foundry business as it signifies confidence in Samsung’s cutting-edge high performance EUV process technology.”

Samsung is a member of the OpenPOWER Foundation, a vendor ecosystem facilitating the development of IBM Power architecture-based customized servers, networking and storage for future data centers and cloud computing. Samsung is also a member of the Q Network to help advance the understanding of applications software in quantum computing for the industry.

By Lynnette Reese, Editor-in-Chief, Embedded Intel® Solutions

According to SEMI (semi.org), the global semiconductor revenue forecast for the second half of 2018 was doubled from 7.5 to 15 percent, a substantial growth. The semiconductor industry has seen cycles of growth and stagnation before, as innovative new products peak and decline before new technologies come out to drive growth from another direction. The wide adoption of personal computers marked great growth in semiconductors; a market that has been dominated by Intel for decades. When the PC market began to mature, a period of stagnation was followed by the mobile computing era. Companies like Qualcomm and MediaTek emerged as key players in the mobile industry. However, both computer and mobile sectors are now sustainable, but not growing appreciably.

Figure 1: Entegris works with automakers and mainstream fabs to investigate reducing contaminants and particles that don’t affect yield yet cause critical problems in long-term reliability. (Image courtesy of Entegris, ©2018).

Recently, multiple growth engines have kicked in for semiconductors, driving a new era of growth. Growth drivers include data centers, a growing “economy of data,” artificial intelligence, virtual reality, autonomous vehicles, and increasing automation in industrial applications, particularly in the Internet of Things (IoT) and robotics. The concurrent emergence of several new markets and applications has prompted a high demand; from leading edge chips on down to some of the legacy nodes. In turn, growth in semiconductors is driving the need for materials and better technologies for Integrated Chips (ICs).

Companies feeding the boom with materials and chemicals for making ICs are seeing growth that shows no signs of abating. One materials company, Entegris (ENTG), has recently expanded its Kulim manufacturing capacity and capabilities, adding new tooling, molding machines, and numerous updates to the assembly area so that Entegris can meet the demand for wafer handling products. Entegris is a 52-year-old company that, for context, was founded two years before Intel Corporation. Entegris provides materials and material solutions to semiconductor companies (semis). Currently, the company has about 4,000 employees with sales revenue of approximately $1.5 billion. Entegris has been expanding rapidly in recent years, achieving growth by about two to three percent above the market. The company is now viewed by most investors as a growth company than as an industrial, “cyclical business” type of company. Entegris is assisting the semiconductor industry in two ways: by helping the semis realize more advanced technologies and by providing materials for making chips.

Figure 2: Robotic handling equipment in a clean room. (Image courtesy of Entegris, ©2018)

Entegris has three divisions that address three different elements of semiconductor manufacturing. The first division provides advanced materials such as specialty chemicals, specialty gas mixtures, cleaning chemicals, deposition chemicals, specialty coatings, graphite, silicon carbide (SiC), and many other materials that fabrication plants (fabs) use to make chips. The second group at Entegris is involved in benefiting materials handling with carriers for handling wafers and photomasks, wafer and reticle handling, fluid management, sensing, control, and supply and delivery of chemicals to fabs. It is chip growth that primarily drives the growth of all Entegris’ divisions, with some growth influenced by advances in technology. The third division focuses on microcontamination control and primarily handles leading edge filtration and purification (at levels measured in parts per trillion). Microcontamination control is presently the fastest growing division at Entegris. Anything that touches the semiconductor wafer must go through a filter and purifier, whether gas, liquid, photo-resist, slurries, or other chemicals.

Figure 3: Entegris provides solutions to eliminate some of the random inferences impacting reliability. (Image courtesy of Entegris, © 2018)

Why is microcontamination control important?

Technologies continue to improve such that the industry is now producing Systems-on-chip (SoCs) at the 7 nm node and is headed to 5 nm. At such a scale, any particle or contaminants can make a chip fail. Enterprises like Entegris’ microcontamination control group are the last line of defense against contaminants for all chipmakers. Entegris works with automakers and mainstream fabs to investigate reducing some of the contaminants and particles that are not affecting yield yet are causing critical problems in long-term chip reliability.

According to Wenge Yang, Vice President of Marketing Strategy at Entegris, “Many existing and mainstream fabs are yielding high 90 percent range. However, we recently found that particles that are small enough to not cause a reduction in chip yield – can still cause reliability issues down the road. This has triggered Entegris to become an industry advocate on a new effort to reduce contaminants even further than has been practiced up to now.”

A Hot Topic

Entegris spotted a trend emerging about a year or two ago as semis began rooting out causes affecting long-term chip reliability that included microcontamination that did not affect yield but could affect a chips’ long-term reliability. There’s no greater concern for reliability than in autonomous cars; it’s become a hot topic.

The Society of Automotive Engineers (SAE) International issued a standard (J3016) that defines six levels of automation for self-driving cars. Level zero has no automation whatsoever. Adaptive cruise control is a Level one feature. Level two specifies partial automation. Level three defines conditional automation, such as Tesla’s Autopilot. Level four demonstrates a high level of automation where the car can operate without human oversight under certain conditions. Level five is full automation with no human involvement.

“One of the most interesting things we have seen is that with the growth of some specific sectors, the design and manufacturing challenge is changing,” Wenge affirms. “One example is in the automotive industry. If an automobile used only two or 300 chips total, the failure rate is not causing that much of a headache as it does if you have 10,000 chips in one car.”

Level Five autonomous cars may have as many as 10 LiDAR systems around the car, gathering data and processing signals and images in real-time, with low latencies. A fully autonomous car might have 10,000 ICs with 50 percent of the cost of the car sunk into the electronics. With that many chips in one autonomous vehicle, automakers begin to parallel NASA-level care in design and manufacturing, but without the added safety of redundant systems due to cost and size constraints. Add to this pressurized scenario the harsh automotive environment with extreme temperatures and constant, heavy vibration.

Figure 4: Autonomous Waymo Chrysler Pacifica Hybrid minivan undergoing testing in Los Altos, California, November 2017. Credit: Dllu, CC BY-SA 4.0.

“With these many chips in each car, if you have a failure rate of one chip out of one million, then several hundred cars might fail on the roads every single day,” states Wenge. The resulting repairs, medical bills, and lawsuits would be costlier than fixing the reliability issue at the outset. “For Entegris, the intrinsic need for increased reliability is an excellent opportunity.”

The military, aerospace, and avionics industries commonly employ redundant systems. However, the automotive industry cannot afford redundant systems, which means that we must improve the single systems’ reliability. The Level Five autonomous car sends processed data feeds into a central computer that decides whether the car should brake, slow down, accelerate, and so forth. If any component in any autonomous automotive systems fails, the car may not collect crucial data.  If the car has made a decision, it may be unable to execute on it. The possibility for failure is multiplied as automakers load thousands of ICs in a single car.

As Wenge points out, “Autonomous car makers start to realize, ‘If I put that many chips into the car, I run the risk of reliability everywhere.’ Of greater concern are chips that have passed on down the line as ‘good’ in a 100 percent yield batch…but can still fail in the field. This is how the topic of detailed reliability gets triggered.”  The design process for automotive applications must be accompanied by very high awareness of the reliability consequences. States Wenge, “Entegris is providing solutions to eliminate some of the random inferences impacting reliability.

Wenge Yang, Ph.D. Vice President, Market Strategy Dr. Yang joined Entegris in 2012 to serve as the Vice President of Market Strategy. In his role, he is responsible for Entegris product and market strategy, market research and market trend analysis, strategic marketing, and the company’s strategic technology roadmap. Before joining Entegris, Dr. Yang was an equity research analyst at Citigroup covering the semiconductor equipment and materials sector. He also served in various executive roles at Advanced Micro Devices, Tokyo Electron, and two start-up companies. Dr. Yang received a Ph.D. in Materials Science and Engineering and an MBA from Rensselaer Polytechnic Institute. Master of Science degree in Mechanical Engineering from the New Jersey Institute of Technology, and a Bachelor of Science degree in Materials Science and Engineering from Shanghai Jiao Tong University.