Category Archives: Semiconductors

Leti, a research institute of CEA-Tech, and Silvaco Inc., a global provider of software, IP and services for designing chips and electronic systems for semiconductor companies, today announced during the IEDM 2018 conference a project to create innovative and unified SPICE compact models for the design of advanced circuits using nanowire and nanosheet technologies.

The new predictive and physical compact model under development, Leti-NSP, builds on Leti’s 15 years of model development, including the popular Leti-UTSOI model for FD-SOI technology. The Leti-NSP compact model uses a novel methodology for the calculation of the surface potential, including quantum confinement. The model is able to handle arbitrary cross-section shapes of stacked planar and vertical GAA MOSFETs (circular, square, rectangular). It provides an excellent tool for design exploration of nanowire and nanosheet device architectures.

This three-year collaboration will make the new device models available to designers through SmartSpiceTM, Silvaco’s high-performance parallel SPICE simulator for use by circuit designers. The corresponding model-parameters extraction flow will be implemented in Utmost IVTM, Silvaco’s database-driven environment for characterizing semiconductor devices, to ensure an accurate fit between simulated and measured device characteristics.

Accuracy of analysis at the nanometer scale is essential for co-optimization of silicon process technology and circuit performance. Besides accurate device characterization and simulation, a complete solution includes TCAD simulation, and 3D parasitic extraction. Silvaco’s partnership with leading research institutions for atomistic TCAD, and its proven in-house extraction solver technology, will provide the most accurate Design Technology Co-Optimization (DTCO) solution for nanometer technologies.

“Over two decades, CEA-Leti and Silvaco have collaborated on design-technology co-optimization, ranging from innovative TCAD simulation to the design of advanced nanoelectronics, and thus expanded and strengthened Silvaco’s suite of tools for designers,” said Emmanuel Sabonnadière, CEA-Leti CEO. “This project continues that partnership, andwhen these physics-based compact models are made available to designers worldwide, they will be able to evaluate the potential of advanced nanowire-based CMOS technologies under development at CEA-Leti.”

“DTCO, including circuit simulation, is fundamental to the development of electronic devices, and shrinking silicon geometries are placing an even greater premium on accuracy to capture and evaluate all the new physical effects in nanometer design,” said Eric Guichard, vice president of Silvaco’s TCAD Division. “Building on past successes of Leti and Silvaco’s collaboration, this project will provide circuit designers and technologists with powerful, advanced design flows that combine CEA-Leti’s physical, predictive, and easy-to-use models with Silvaco’s high-accuracy EDA tools.”

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today introduced the all new BONDSCALE™ automated production fusion bonding system. BONDSCALE is designed to fulfill a wide range of fusion/molecular wafer bonding applications, including engineered substrate manufacturing and 3D integration approaches that use layer-transfer processing, such as monolithic 3D (M3D). With BONDSCALE, EVG is bringing wafer bonding to front-end semiconductor processing and helping to address long-term challenges for “More Moore” logic device scaling identified in the International Roadmap for Devices and Systems (IRDS). Incorporating an enhanced edge alignment technology, BONDSCALE provides a significant boost in wafer bond productivity and lower cost of ownership (CoO) compared to existing fusion bonding platforms. It is already being shipped to customers.

BONDSCALE is being sold alongside EVG’s industry benchmark GEMINI® FB XT automated fusion bonding system, with each platform targeting different applications. While BONDSCALE will primarily focus on engineered substrate bonding and layer-transfer processing, the GEMINI FB XT will support applications requiring higher alignment accuracies, such as memory stacking, 3D systems on chip (SoC), backside illuminated CMOS image sensor stacking, and die partitioning.

Direct wafer bonding key to driving semiconductor performance scaling

According to the IRDS Roadmap, parasitic scaling will become a dominant driver of logic device performance in the coming years, requiring new transistor architectures and materials. The IRDS Roadmap also notes that new 3D integration approaches such as M3D will be necessary to support the long-term transition from 2D to 3D VLSI, including backside power distribution, N&P stacking, logic-on-memory, clustered functional stacks and beyond-CMOS adoption. Layer-transfer processes and engineered substrates are enabling technologies for logic scaling by helping to deliver significant improvements in device performance, functionality and power consumption. Direct wafer bonding with plasma activation is a proven solution for enabling heterogeneous integration of different materials, high-quality engineered substrates as well as thin-silicon-layer-transfer applications.

“As a pioneer and market leader in wafer bonding, EVG has been at the forefront in helping customers bring new semiconductor technologies from early R&D to full-scale manufacturing,” stated Paul Lindner, executive technology director at EV Group. “Nearly 25 years ago, EVG introduced the industry’s first silicon-on-insulator (SOI) wafer bonder to support the production of high-frequency and radiation-hard devices for niche applications. Since then, we have continuously enhanced the performance and CoO of our direct bonding platforms to help our customers bring the benefits of engineered substrates to a wider range of applications. Our new BONDSCALE solution takes this to the next level, boosting productivity to fulfill the growing need for engineered substrates and layer-transfer processing to enable continued performance, power and area scaling of next-generation logic and memory devices in the ‘More Moore’ era.”

BONDSCALE is a high-volume production system for fusion/direct wafer bonding needed for front-end-of-line applications. Featuring EVG’s LowTemp™ plasma activation technology, the BONDSCALE system combines all essential steps for fusion bonding — including cleaning, plasma activation, alignment, pre-bonding and IR inspection — in a single platform that is suitable for a wide range of fusion/molecular wafer bonding applications. Capable of processing both 200-mm and 300-mm wafers, the system ensures a void-free, high-throughput, and high-yield production process.

BONDSCALE incorporates next-generation fusion/direct bonding modules, a new wafer handling system and optical edge alignment to provide significantly higher throughput and productivity to support the needs of its customers to ramp up engineered substrate wafer production and M3D integration.

SEMI, the global industry association representing the electronics manufacturing supply chain, today reported that third quarter 2018 worldwide semiconductor manufacturing equipment billings dropped 5 percent from the previous quarter to US$15.8 billion but are 11 percent higher than the same quarter a year ago.

The data are gathered jointly with the Semiconductor Equipment Association of Japan (SEAJ) from over 95 global equipment companies that provide data on a monthly basis.

The quarterly billings data by region in billions of U.S. dollars, quarter-over-quarter growth and year-over-year rates by region are as follows:

 
3Q2018
2Q2018
3Q2017
3Q18/2Q18
(Qtr-over-Qtr)
3Q18/3Q17
(Year-over-Year)
China
3.98
3.79
1.93
5%
106%
Korea
3.45
4.86
4.99
-29%
-31%
Taiwan
2.90
2.19
2.37
33%
23%
Japan
2.41
2.28
1.73
6%
40%
North America
1.27
1.47
1.50
-14%
-15%
Rest of World
0.98
0.96
0.74
2%
32%
Europe
0.85
1.18
1.06
-29%
-20%
Total
15.84
16.74
14.33
-5%
11%

Source: SEMI (www.semi.org) and SEAJ, December 2018

 

The Equipment Market Data Subscription (EMDS) from SEMI provides comprehensive market data for the global semiconductor equipment market.

Covalent Metrology, a provider of analytical services to advanced materials innovation companies, is pleased to announce a new partnership with Rigaku Corporation, a global leader in X-ray analytical instrumentation.

In a joint declaration, Covalent and Rigaku reveal a first-of-its-kind collaboration agreement demonstrating a mutual commitment to support American high-tech industries with the most advanced metrology capabilities in the world.

Under the terms of this agreement, Rigaku, “The world’s leading supplier of X-ray metrology technology,” will be supplying Covalent with several state-of-the-art instruments for their new facility in Sunnyvale, California. This collaboration agreement provides Covalent with exceptional analytical service capabilities and Rigaku a North American demonstration facility located in the heart of Silicon Valley.

“This partnership will significantly expand Covalent’s product offering.  Rigaku is a proven leader in this field and has earned its outstanding reputation over many decades of technology innovation.  Working together, our respective customers will benefit from being able to access the most advanced technology, staffed by world-class experts and delivered with unprecedented customer service,” said Craig Hunter, Covalent’s Founder and CEO.

The Rigaku Semiconductor Metrology Division designs and manufactures X-ray based measurement tools to solve semiconductor manufacturing challenges. With over 35 years of global market leadership in the semiconductor industry, Rigaku metrology tools employ X-ray fluorescence (XRF), X-ray diffraction (XRD), X-ray reflectometry (XRR) and Critical-Dimension Small-Angle X-ray Scattering (CD-SAXS) techniques, enabling everything from in-fab process control metrology to R&D for thin film and materials characterization.

Products include in-line, high-throughput X-ray monitoring tools for measuring critical process parameters such as film thickness, density and roughness, XRF spectrometers for thickness and composition determination, and total-reflection XRF spectrometers (TXRF) with integrated vapor phase decomposition (VPD) for trace contamination monitoring.

“We believe deeply in the power of American ingenuity, and we are focusing our investments in areas where we can have a direct impact on innovation. Rigaku is committed to advancing cutting-edge technologies that deliver solutions for yield enhancement and process development,” said Kiyoshi Ogata, Rigaku Senior Vice President. “Covalent Metrology’s experienced leadership, top-notch technical team and business model innovations altogether make them the ideal partner for our Silicon Valley Semiconductor Lab. We are proud to be a part of this collaboration and look forward to enabling new customer designs.”

Covalent Metrology provides imaging and characterization services to support R&D, defect analysis, and quality control for companies in semiconductors, solar, medical devices, MEMS and other industries.  Covalent’s analytical services include atomic force microscopy (AFM), X-ray XRD/XRR, high-resolution X-ray diffraction (HR-XRD), scanning electron microscopy (SEM), spectral ellipsometry, optical profilometry, UV-VIS-NIR spectrophotometry, TEM, XPS, TOF-SIMS and many others.

Sanjay Mehrotra, President and CEO, Micron Technology, 2019 SIA Chair

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced the SIA Board of Directors has elected Sanjay Mehrotra, President and CEO of Micron Technology, Inc. (NASDAQ: MU), as its 2019 Chair and Keith Jackson, President, CEO, and Director of ON Semiconductor (NASDAQ: ON), as its 2019 Vice Chair.

“It is a great pleasure to welcome Sanjay Mehrotra as SIA’s 2019 Chair and Keith Jackson as SIA’s Vice Chair,” said John Neuffer, SIA President and CEO. “A design engineer by trade, Sanjay is a highly accomplished industry veteran and a leading voice on semiconductor technology. With more than 30 years of experience, Keith is a mainstay in our industry and a devoted champion for semiconductor priorities. Their combined skills and experience will be a tremendous asset to SIA as we pursue our industry’s interests in Washington and around the world.”

A 39-year veteran of the semiconductor industry, Mehrotra joined Micron in May 2017 after a long and distinguished career at SanDisk Corporation, where he led the company from a start-up in 1988 until its eventual sale in 2016. In addition to being a SanDisk co-founder, Mehrotra served as its President and CEO from 2011 to 2016, overseeing its growth to an industry-leading Fortune 500 company.

Prior to SanDisk, Mehrotra held design engineering positions at Integrated Device Technology, Inc., SEEQ Technology, and Intel Corporation. Mehrotra earned both bachelor’s and master’s degrees in electrical engineering and computer science from the University of California, Berkeley. He holds more than 70 patents and has published articles in the areas of non-volatile memory design and flash memory systems.

“The semiconductor industry is leading the greatest period of technological advancement in human history, making the seemingly impossible possible and opening up tremendous opportunities for economic growth,” said Mehrotra. “Driving innovation requires our industry to speak with one voice and promote policies that support our industry vision, and I look forward to helping lead that effort as 2019 SIA Chair.”

Jackson began serving as President, CEO, and Director of ON Semiconductor in November 2002. Before joining ON Semiconductor, he was with Fairchild, serving as Executive Vice President and General Manager, Analog, Mixed Signal, and Configurable Products Groups, and was head of its Integrated Circuits Group.

Previously, Jackson served as President and a Member of the Board of Directors of Tritech Microelectronics in Singapore and worked for National Semiconductor Corporation, most recently as Vice President and General Manager of the Analog and Mixed Signal division. He also held various positions at Texas Instruments Incorporated, including engineering and management positions, from 1973 to 1986. Mr. Jackson earned his bachelor’s and master’s degrees from Southern Methodist University.

“It is an honor to serve as 2019 SIA Vice Chair,” Jackson said. “Many issues of great importance to the semiconductor industry are being debated in Washington and around the world. We look forward to promoting policies that advance semiconductor technology and move our industry forward.”

 

By David W. Price, Jay Rathert and Douglas G. Sutherland

Author’s Note:The Process Watch series explores key concepts about process control—defect inspection, metrology and data analytics—for the semiconductor industry. This article is the fourth in a series on process control strategies for automotive semiconductor devices.

The first three articles1-3 in this series discussed methods that automotive semiconductor manufacturers can use to better meet the challenging quality requirements of their customers. The first paper addressed the impact of automotive IC reliability failures and the idea that combating them requires a “Zero Defect” mentality. The second paper discussed continuous improvement programs and strategies that automotive fabs implement to reduce the process defects that can become chip reliability problems. The third paper focused on the additional process control sensitivity requirements needed to capture potential latent (reliability) defects. This installment discusses excursion monitoring strategies across the entire automotive fab process so that non-conforming material can be quickly found and partitioned.

Semiconductor fabs that make automotive ICs typically offer automotive service packages (ASPs). These ASPs provide differentiated process flows – with elements such as more process control and process monitoring, or guaranteed use of golden process tools. The goal of ASPs is to help ensure that the chips produced meet the stringent reliability requirements of the automotive industry.

But even with the use of an automotive service package, excursions are inevitable, as they are with any controlled process. Recognizing this, automotive semiconductor fabs pay special attention to creating a comprehensive control plan for their critical process layers as part of their Process Failure Mode and Effects Analysis (PFMEA). The control plan details the process steps to be monitored and how they are monitored – specifying details such as the inspection sensitivity, sampling frequency and the exact process control systems to be used. A well-designed control plan will detect all excursions and keep “maverick” wafers from escaping the fab due to undersampling. Additionally, it will clearly indicate which wafers are affected by each excursion so that they can be quarantined and more fully dispositioned – thereby ensuring that non-conforming devices will not inadvertently ship.

To meet these objectives, the control plan of an automotive service package will invariably require much more extensive inspection and metrology coverage than the control plan for production of ICs for consumer products. An analysis of process control benchmarking data from fabs running both automotive and non-automotive products at the same design rule have shown that the fabs implement more defect inspection steps and more types of process control (inspection and metrology) for the automotive products. The data reveals that on average:

  • Automotive flows use approximately 1.5 to 2 times more defect inspection steps
  • Automotive flows employ more frequent sampling, both as a percentage of lots and number of wafers per lot
  • Automotive flows use additional sensitivity to capture the smaller defects that may affect reliability

The combined impact of these factors results in the typical automotive fab requiring 50% more process control capacity than their consumer product peers. A closer look reveals exactly how this capacity is deployed.

Figure 1 below shows an example of the number of lots between inspection points for both an automotive and a non-automotive process flow in the same fab. As a result of the increased number of inspection steps, if there is a defect excursion, it will be found much more quickly in the automotive flow. Finding the excursion sooner limits the lots at risk: a smaller and more clearly defined population of lots are exposed to the higher defect count, thereby helping serve the automotive traceability requirement. These excursion lots are then quarantined for high-sensitivity inspection of 100% of the wafers to disposition them for release, scrap, or when applicable, a downgrade to a non-automotive application.

Figure 1. Example demonstrating the lots at risk between inspection points for an automotive process flow (blue) and a non-automotive (baseline) process blow (pink). The automotive process flow has many more inspection points in the FEOL and therefore fewer lots at risk when a defect excursion does occur.

The additional inspection points in the automotive service package have the added benefit of simplifying the search for the root cause of the excursion by reducing the range of potential sources. Fewer potential sources helps speed effective 8D investigations4 to find and fix the problem. Counterintuitively, the increased number of inspection points also tends to reduce production cycle time due to reduced variability in the line.5

While increasing inspection capacity helps monitor and contain process excursions, there remains risk to automotive IC quality. Because each wafer may take a unique path through the multitude of processing chambers available in the fab, the sum of minor variations and marginalities across hundreds of process steps can create “maverick” wafers. These wafers can easily slip through a control plan that relies heavily on sub-sampling, allowing at-risk die into the supply chain. To address this issue, many automotive fabs are adding high-speed macro defect inspection tools to their fleet to scan more wafers per lot. This significantly improves the probability of catching maverick wafers and preventing them from entering the automotive supply chain.

Newer generation macro defect inspection tools6 can combine the sensitivity and defect capture of many older generation brightfield and darkfield wafer defect inspection tools into a single platform that can operate at nearly 150 wafers per hour, keeping cost of ownership low. In larger design rule 200mm fabs, the additional capacity often reveals multiple low-level excursions that had previously gone undetected, as shown in Figure 2.

Figure 2. The legacy sample plan of 5 wafers per lot (yellow circles) would have allowed the single maverick wafer excursion (red square) to go undetected. High capacity macro defect inspection tools can stop escapes by reducing undersampling and the associated risks.

In advanced, smaller design rule fabs, macro defect inspection tools lack the needed sensitivity to replace the traditional line monitoring and patterned wafer excursion monitoring roles occupied by broadband plasma and laser scanning wafer defect inspection tools. However, their high capacity has found an important role in augmenting the existing sample plan to find wafer-level signatures that indicate a maverick wafer.

A recent development in automotive control strategies is the use of defect inspection for die-level screening. One such technique, known as Inline Defect Part Average Testing (I-PAT™), uses outlier detection techniques to further enhance the fab’s ability to recognize die that may pass electrical test but become reliability failures later due to latent defects. This method will be discussed in detail in the next installment of this series.

About the authors:

Dr. David W. Price and Jay Rathert are Senior Directors at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 15 years, they have worked directly with over 50 semiconductor IC manufacturers to help them optimize their overall process control strategy for a variety of specific markets, including implementation of strategies for automotive reliability, legacy fab cost and risk optimization, and advanced design rule time-to-market. The Process Watch series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

References:

  1. Price, Sutherland and Rathert, “Process Watch: The (Automotive) Problem With Semiconductors,” Solid State Technology, January 2018.
  2. Price, Sutherland and Rathert, “Process Watch: Baseline Yield Predicts Baseline Reliability,” Solid State Technology, March 2018.
  3. Price, Sutherland, Rathert, McCormack and Saville, “Process Watch: Automotive Defect Sensitivity Requirements,” Solid State Technology, August 2018.
  4. 8D investigations involve a systematic approach to solving problems. https://en.wikipedia.org/wiki/Eight_disciplines_problem_solving
  5. Sutherland and Price, “Process Watch: Process Control and Production Cycle Time,” Solid State Technology, June 2016.
  6. For example, see: https://www.kla-tencor.com/products/chip-manufacturing/defect-inspection-review.html#product-8-series

 

Thermal Engineering Associates, Inc. (TEA) announces that its Thermal Test Chip (TTC) will soon be available in 8″ (200mm) diameter wafers. This conversion is taking place because –

  • Industry is better able to handle 8″ wafers for bumping, thinning, and sawing
  • Number of available Unit Cells per wafer is more than doubled
  • Wafers can be offered up to 725µm thick to better simulate application chips
  • The larger wafer produces more large cell array chips
  • Cost per Unit Cell is lowered

For a limited time, TEA is accepting preorders for the 8″ wafer products – both TTC-1001 (1mm x 1mm Unit Cell) and TTC-1002 (2.54mm x 2.54mm Unit Cell) versions – and is offering a price discount on orders of 5 or more wafers of either version. Both versions will be available in Wire Bond or Flip Chip (Bumped) types. Initial delivery is scheduled for February 2019.

IC Insights revised its outlook for total semiconductor industry capital spending and presented its forecast of semiconductor capex spending for individual companies in its November Update to The McClean Report 2018, which was released earlier this month.

Samsung is expected to have the largest capex budget of any IC supplier again in 2018.  After spending $24.2 billion for semiconductor capex in 2017, IC Insights forecasts that Samsung’s spending will edge slightly downward, but remain at a very strong level of $22.6 billion in 2018 (Figure 1).  If it comes in at this amount, Samsung’s two-year semiconductor capital spending will be an astounding $46.8 billion.

Figure 1

As seen in Figure 1, Samsung’s semiconductor capital outlays from 2010, the first year the company spent more than $10 billion in semiconductor capex, through 2016 averaged $12.0 billion per year. However, after spending $11.3 billion in 2016, the company more than doubled its 2017 capex budget. The fact that Samsung’s continued its strong capex spending in 2018 is just as impressive.

IC Insights believes that Samsung’s massive spending outlays in 2017 and 2018 will have repercussions far into the future.  One effect that has already begun is a period of overcapacity in the 3D NAND flash market.  This overcapacity situation is due not only to Samsung’s huge spending for 3D NAND flash, but also from spending by competitors (e.g., SK Hynix, Micron, Toshiba, Intel, etc.) that attempt to keep pace in this market segment.

With the DRAM and NAND flash memory markets showing strong growth through the first three quarters of 2018, SK Hynix ramped up its capital spending this year.  In 1Q18, SK Hynix said that it intended to increase its capex spending by “at least 30%” this year. In the November Update, IC Insights forecasts that SK Hynix will see a 58% surge in its semi capex spending.  The increased spending by SK Hynix this year is focused primarily on bringing new capacity online at two of its large memory fabs—M15, a 3D NAND flash fab in Cheongju, South Korea, and the expansion of its huge DRAM fab in Wuxi, China. The Cheongju fab is being pushed to open before the end of this year.  The Wuxi fab is also targeted to open by the end of this year, a few months earlier than its original start date of early 2019.

Overall, IC Insights’ now forecasts total semiconductor industry capital spending will climb 15% to $107.1 billion this year, the first time that annual industry capex is expected to top $100.0 billion. Following the industry-wide growth this year, semiconductor capex is expected to decline 12% in 2019 (Figure 2).

Figure 2

Given that the current softness in the memory market is expected to extend into at least the first half of next year, the combined capital spending by the three largest memory suppliers—Samsung, SK Hynix, and Micron—is forecast to drop from $45.4 billion in 2018 to $37.5 billion in 2019, a decline of 17%.

In total, the top five spenders, which are expected to represent 66% of total outlays this year, are forecast to cut their capital spending by 14% in 2019 with the remaining semiconductor industry companies registering a 7% decline.

GLOBALFOUNDRIES today announced its advanced silicon germanium (SiGe) offering, 9HP, is now available for prototyping on the company’s 300mm wafer manufacturing platform. The move signifies the strong growth in data center and high-speed wired/wireless applications that can leverage the scale advantages of a 300mm manufacturing footprint. By tapping into GF’s 300mm manufacturing expertise, clients can take advantage of increased production efficiency and reproducibility for high-speed applications such as optical networks, 5G millimeter-wave wireless communications and automotive radar.

GF is the industry leader in the manufacturing of high-performance SiGe solutions on its 200mm production line in Burlington, Vermont. The migration of 9HP, a 90nm SiGe process, to 300mm wafers manufactured at GF’s Fab 10 facility in East Fishkill, N.Y., continues this leadership and establishes a 300mm foothold for further roadmap development, ensuring continued technology performance enhancements and scaling.

“The increasing complexity and performance demands of high-bandwidth communication systems have created the need for higher performance silicon solutions,” said Christine Dunbar, vice president of RF business unit at GF. “GF’s 9HP is specifically designed to provide outstanding performance, and in 300mm manufacturing will support our client’s requirements for high-speed wired and wireless components that will shape future data communications.”

GF’s 9HP extends a rich history of high-performance SiGe BiCMOS technologies designed to support the massive growth in extremely high data rates at microwave and millimeter-wave frequencies for the next generation of wireless networks and communications infrastructure, such asterabit-level optical networks, 5G mmWave and satellite communications (SATCOM) and instrumentation and defense systems. The technology offers superior low-current/high-frequency performance with improved heterojunction bipolar transistor (HBT) performance and up to a 35 percent increase in maximum oscillation frequency (Fmax) to 370GHz compared to its predecessors, SiGe 8XP and 8HP.

Client prototyping of 9HP on 300mm at Fab 10 in East Fishkill, N.Y. on multi-project wafers (MPWs) is underway now, with qualified process and design kits scheduled in 2Q 2019.

Human skin contains sensitive nerve cells that detect pressure, temperature and other sensations that allow tactile interactions with the environment. To help robots and prosthetic devices attain these abilities, scientists are trying to develop electronic skins. Now researchers report a new method in ACS Applied Materials & Interfacesthat creates an ultrathin, stretchable electronic skin, which could be used for a variety of human-machine interactions. See a video of the e-skin here.

Electronic skin could be used for many applications, including prosthetic devices, wearable health monitors, robotics and virtual reality. A major challenge is transferring ultrathin electrical circuits onto complex 3D surfaces and then having the electronics be bendable and stretchable enough to allow movement. Some scientists have developed flexible “electronic tattoos” for this purpose, but their production is typically slow, expensive and requires clean-room fabrication methods such as photolithography. Mahmoud Tavakoli, Carmel Majidi and colleagues wanted to develop a fast, simple and inexpensive method for producing thin-film circuits with integrated microelectronics.

In the new approach, the researchers patterned a circuit template onto a sheet of transfer tattoo paper with an ordinary desktop laser printer. They then coated the template with silver paste, which adhered only to the printed toner ink. On top of the silver paste, the team deposited a gallium-indium liquid metal alloy that increased the electrical conductivity and flexibility of the circuit. Finally, they added external electronics, such as microchips, with a conductive “glue” made of vertically aligned magnetic particles embedded in a polyvinyl alcohol gel. The researchers transferred the electronic tattoo to various objects and demonstrated several applications of the new method, such as controlling a robot prosthetic arm, monitoring human skeletal muscle activity and incorporating proximity sensors into a 3D model of a hand.