Category Archives: Semiconductors

MagnaChip Semiconductor Corporation (“MagnaChip”) (NYSE: MX), a designer and manufacturer of analog and mixed-signal semiconductor platform solutions, today announced the appointment of Jeong Ki Min to the newly created position of Chief of Strategic Planning. Mr. Min, a seasoned semiconductor executive with 33 years of global business experience, previously held senior positions at Samsung Semiconductor, Samsung Electronics, Samsung Display, and SK Telecom. He reports directly to YJ Kim, MagnaChip’s Chief Executive Officer.

During his more than three decades in the high-tech industry, Mr. Min has initiated and negotiated high-profile joint venture agreements, strategic alliances and acquisitions. Among his other accomplishments, Mr. Min also has led new business planning teams, managed R&D operations, led Foundry marketing teams, and helped develop semiconductor growth strategies.

Most recently, Mr. Min was Senior Vice President, Office of the Vice Chairman of SK Telecom. Prior to that, Mr. Min held various leadership roles at several divisions of Samsung during a 25-year career.

At MagnaChip, Mr. Min will have a variety of responsibilities, including strategic planning related to semiconductor technologies, products, and markets. He also will play a key role in activities related to potential alliances, joint ventures and other transactions.

“Mr. Min brings to MagnaChip a wealth of semiconductor experience as well as a strong track record of business success,” said YJ Kim, MagnaChip CEO. “Mr. Min will drive the strategic planning process across MagnaChip and help the management team set the future direction of our company.”

Mr. Min said,  “Over the past three years, MagnaChip has been transformed into a powerhouse in the Display and Power standard products businesses and become an industry leader in the analog and mixed signal Foundry business. I’m excited to join MagnaChip and look forward to working with the management team on strategic issues to help MagnaChip achieve the next level of success.”

GLOBALFOUNDRIES today announced the establishment of Avera Semiconductor LLC, a wholly owned subsidiary dedicated to providing custom silicon solutions for a broad range of applications. Avera Semi will leverage deep ties with GF to deliver ASIC offerings on 14/12nm and more mature technologies while providing clients new capabilities and access to alternate foundry processes at 7nm and beyond.

Avera Semi is built upon an unrivaled legacy of ASIC expertise, tapping into a world-class team that has executed more than 2,000 complex designs in its 25-year history. With more than 850 employees, annual revenues in excess of $500 million, and over $3 billion in 14nm designs in execution, Avera Semi is well positioned to serve clients developing products across a wide range of markets, including wired and wireless networking, data centers and storage, artificial intelligence and machine learning, and aerospace and defense.

The new company is led by Kevin O’Buckley, a leader in the ASIC business since joining GF as part of the acquisition of IBM Microelectronics in 2015. Previously, he spent nearly 20 years at IBM in a variety of roles spanning both technical and executive leadership positions.

“I couldn’t imagine a better time to launch a new venture focused on delivering custom ASIC solutions,” O’Buckley said. “Data traffic and bandwidth demands have exploded, and next-generation systems for cloud and communications must deliver more performance and handle more complexity than ever before. Avera Semi has the right combination of expertise and technology to help our clients design and build high-performance, highly optimized semiconductor solutions.”

“Arm has a long history of collaborating with the team building Avera Semi to enhance PPA and bring innovative solutions to market,” said Drew Henry, senior vice president and general manager, Infrastructure Line of Business, Arm. “As the needs for compute requirements continue to evolve and diversify, we look forward to joining Avera’s capabilities and technologies with Arm Neoverse solutions and physical design IP to deliver unique value to a broad customer base.”

“Synopsys’ long history of collaboration with GF has enabled us to deliver a broad portfolio of high-quality DesignWare IP on a range of GF processes,” said John Koeter, vice president of marketing for IP at Synopsys. “We look forward to continuing this success with Avera Semi to provide designers with the necessary IP for their next-generation, high-performance SoC designs on advanced FinFET processes.”

Avera Semi offers clients a range of capabilities to enable end-to-end silicon solutions:

●      ASIC offerings on both leading-edge and proven process technologies, including a newly established foundry partnership on 7nm
●      A rich IP portfolio, including high-speed SerDes, high-performance embedded TCAMs, ARM® cores and performance and density-optimized embedded SRAMs
●      A comprehensive, production-proven design methodology that builds on a strong record of first-time-right results to help reduce development costs and time-to-market
●      Advanced packaging options to increase bandwidth, eliminate I/O bottlenecks, and reduce memory area, latency and power
●      Flexible ASIC business engagement models that give clients the ability to supplement in-house resources with the level of support needed from experienced chip design, methodology, test and packaging teams

The Global Semiconductor Alliance (GSA) Board of Directors has appointed Dr. Lisa Su, President and Chief Executive Officer of Advanced Micro Devices, Inc. (AMD), as Chair of GSA Board of Directors and Simon Segars, Chief Executive Officer of Arm, as the Vice Chair. These leaders will help drive the GSA vision to establish an efficient, profitable and sustainable global ecosystem as well as broaden the scope of GSA to represent an extended value chain to include systems, software, solutions and services, in addition to semiconductors. Under the direction of the new leadership, GSA will be launching several initiatives that support this expanded vision, including Interest Groups and Working Groups for rapidly emerging but fragmented markets like automotive, artificial intelligence and internet-of-things (IoT). The GSA has also created a Women’s Leadership Initiative and “Rising Women of Influence Award” dedicated to highlighting and honoring key female executive leaders within the industry. The award will be presented at the GSA Annual Awards Dinner on December 6.

“I’m very honored to be named as Chair of GSA Board of Directors and look forward to working with my fellow Board members to execute the expanded GSA vision,” said Dr. Lisa Su. “Semiconductors are crucial drivers for a variety of industries and rapidly growing markets such as AI, IoT, automotive, big data, cloud computing and 5G. This industry is going through radical growth and transformation which demands new and different thinking, including an emphasis on stronger collaboration across the entire ecosystem to increase our pace of innovation.”

GSA will execute its vision with several new initiatives including strategically planned Interest Groups, that will convene the value chain in rapidly growing market segments like IoT and Automotive to collaborate on programs and projects important to the industry. Simon Segars outlined one of these collaborative programs. “We have established a GSA IoT Security Working Group within the IoT Interest Group to address end-to-end issues in IoT Security. It is comprised of various IoT ecosystem security stakeholders including chipset vendors, platform companies, cloud vendors and service providers. The goal is to promote best practices on IoT Security, share information on threats and attacks, define security requirements and inform standards bodies. It is also an opportunity for GSA members and partners to influence the requirements for security that get passed to all participants in the value and supply chains.”

“The GSA Board of Directors is comprised of a literal “Who’s Who” of leaders within the semiconductor ecosystem,” said Jodi Shelton, Co-founder and President of GSA. “They represent some of the most influential companies in the industry providing a comprehensive global perspective. As the CEO of AMD, Lisa understands the value of collaboration. We are confident Lisa and Simon will advance the GSA commitment to being a meaningful platform fostering collaboration, innovation and integration for this industry and across the value chain.”

Dr. Lisa Su is AMD president and chief executive officer and serves on the company’s board of directors. Previously, Dr. Su held executive leadership and engineering positions with AMD, Freescale Semiconductor, Inc. and IBM after receiving her bachelor’s, master’s and doctorate degrees in electrical engineering from the Massachusetts Institute of Technology (MIT). In 2017, Dr. Su was named one of the “World’s 50 Greatest Leaders” by Fortune Magazine and the “Top Ranked Semiconductor CEO” by Institutional Investor Magazine. Under Dr. Su’s leadership, AMD has introduced two completely new chip architectures and more than ten different product families, resulting in double-digit annual revenue growth in 2017.

Simon Segars is chief executive officer of Arm. Since joining Arm as one of its first employees, Simon has driven technical and business innovations to help transform the company into the leading architect of the most pervasive compute technology the world has ever seen. He was named CEO in July 2013 after successfully expanding the company’s U.S. business and strengthening its leadership and relationships in Silicon Valley, where he still lives with his family. Simon earned his BEng in electronic engineering from the University of Sussex and an MSc in computer science from the University of Manchester.

3D NAND is poised to become the dominant NAND flash technology and promises both enhanced performance and capacity. The Innodisk 3D NAND solid state drive (SSD) series is designed to fulfill the more stringent requirements for ruggedness and endurance seen in the industrial market.

The series uses pure industrial-grade Toshiba 3D TLC NAND flash with a rated P/E cycle number of 3000, ensuring solid longevity, while the fully in-house designed firmware is geared towards industrial usage. The SSDs uses direct write, and avoids using SLC cache which eventually causes an SSD performance drop and bloated P/E cycle numbers. Furthermore, the firmware can be customized to a large degree to suit any specialized requirement.

The series includes two product lines: the DRAM-less 3TE7 and the 3TG6-P with integrated DRAM using a Marvell controller. The product lines are available in capacities up to 1TB and 2TB respectively. They can both be fitted with Innodisk’s trio of power stabilizing technologies iCell™, iPower Guard™ and iData Guard™ to further strengthen data integrity in areas susceptible to power fluctuations.

The 3D NAND SSDs also use End-to-End Power Path Protection that ensures error correction at every data transfer point with the host and within the drives themselves. For more sensitive data, drives that utilize AES encryption are available with in-house designed software for easier deployment and management.

Netronome today announced an open architecture for domain-specific accelerators designed to significantly reduce the burgeoning cost of silicon development as demanded by modern data center server, edge computing and automotive applications. Decades of progress with general-purpose CPUs has slowed while performance requirements of workloads have catapulted, driving significant demand in domain-specific accelerators. With current approaches applied to developing and manufacturing domain-specific accelerator silicon, only the largest companies serving the highest volume markets can sustain the needed investment. Netronome is collaborating with six leading silicon companies, Achronix, GLOBALFOUNDRIES, Kandou, NXP, Sarcina and SiFive, to develop an open architecture and related specifications for developing chiplets that promise to reduce silicon development and manufacturing costs.

The silicon industry is undergoing a sea change as a result of multiple forces. Firstly, the demise of Moore’s Law and secondly, the growth of compute-intensive specialized applications (e.g., machine learning, security, networking) are driving the need for domain-specific architectures that drastically impact the economics of silicon development and ROI. Thirdly, the increasing size and complexity of silicon adversely impact development costs and manufacturing yields, and finally, requirements such as significantly reduced latency, form factor and power requirements are becoming critical (e.g., with edge computing).

The open domain-specific accelerator architecture being developed in the ODSA Workgroup enables the chiplet-based silicon design to be composed using best-of-breed components such as processors, accelerators, and memory and I/O peripherals using optimal process nodes. The open architecture will provide a complete stack of components (known good die, packaging, interconnect network, software integration stack) that lowers the hardware and software costs of developing and deploying domain-specific accelerator solutions. Implementing open specifications contributed by participating companies, any vendor’s silicon die can become a building block that can be utilized in a chiplet-based SoC design.

“The end of Moore’s Law will increase the use of domain-specific accelerators to meet power-performance requirements in cloud infrastructure, network infrastructure and IoT/wireless edge applications,” said Bob Wheeler, principal analyst, The Linley Group. “With its modular approach, the open domain-specific accelerator architecture could change the chiplet paradigm from single-vendor solutions to a world of choice, thereby enabling OEMs and operators to develop and deploy advanced SoC solutions.”

“Netronome’s domain-specific architecture as used in its Network Flow Processor (NFP) products has been designed from the ground up keeping modularity, and economies of silicon development and manufacturing costs as top of mind,” said Niel Viljoen, founder and CEO at Netronome. “We are extremely excited to collaborate with industry leaders and contribute significant intellectual property and related open specifications derived from the proven NFP products and apply that effectively to the open and composable chiplet-based architecture being developed in the ODSA Workgroup.”

“The use of AI and the need for power-efficient, high-throughput parallelism is driving the growth of accelerators. However, the high cost and complexity of accelerator development is a major factor restraining growth,” said Steve Mensor, vice president of marketing at Achronix. “We are delighted to join and bring our embedded FPGA technology to the ODSA Workgroup to enable customers to bring open, cost-efficient accelerator products to market.”

“To meet current and future growth demands, network providers need a more efficient approach to satisfy the needs of a wide range of data center applications,” said Kevin O’Buckley, general manager ASIC Business Unit at GLOBALFOUNDRIES. “Our collaboration efforts with the ODSA Workgroup ensure an additional option to enable data center SoC accelerator technology supporting applications from deep learning for artificial intelligence to next-generation 5G networks.”

“Kandou’s Glasswing USR SerDes was designed to be the enabling interface for heterogeneous chiplet architectures in a shared MCM package,” said Amin Shokrollahi, founder and CEO at Kandou. “With unprecedented bandwidth and ultra-low power, Glasswing enables companies to quickly and efficiently build flexible yet optimized solutions for workload-specific applications. Kandou supports the ODSA Workgroup and delivering Glasswing as a critical component.”

“NXP strongly supports development of chiplet technology in support of domain-specific acceleration for multiple markets,” said Sam Fuller, director of marketing at NXP. “NXP is pleased to join the ODSA Workgroup and provide its Multicore Arm® SoC solutions to enable low-power, low-latency, open accelerator solutions that deliver greater cost and performance efficiencies.”

“Sarcina provides complex high-speed and high pin-count packaging solutions for leading fabless semiconductor companies,” said Larry Zu, Ph.D., president at Sarcina Technology LLC. “We are pleased to join the ODSA Workgroup and offer a packaging service for the open data center accelerator prototype that can accelerate the time-to-package while lowering the total cost.”

“A ‘one size fits all’ architecture approach to data center workloads will not deliver the required performance and efficiency,” said Dr. Naveed Sherwani, president and CEO at SiFive. “We are pleased to be a member of the ODSA Workgroup and look forward to SiFive’s leading RISC-V Core IP being available in chiplet form, potentially via our silicon capabilities, to enable customers to create open, heterogeneous, best-in-class accelerators at low cost.”

Quantum computers that are capable of solving complex problems, like drug design or machine learning, will require millions of quantum bits – or qubits – connected in an integrated way and designed to correct errors that inevitably occur in fragile quantum systems.

Now, an Australian research team has experimentally realised a crucial combination of these capabilities on a silicon chip, bringing the dream of a universal quantum computer closer to reality.

They have demonstrated an integrated silicon qubit platform that combines both single-spin addressability – the ability to ‘write’ information on a single spin qubit without disturbing its neighbours – and a qubit ‘read-out’ process that will be vital for quantum error correction.

Moreover, their new integrated design can be manufactured using well-established technology used in the existing computer industry.

The team is led by Scientia Professor Andrew Dzurak of the University of New South Wales in Sydney, a program leader at the Centre of Excellence for Quantum Computation and Communication Technology (CQC2T) and Director of the NSW node of the Australian National Fabrication Facility.

Last year, Dzurak and colleagues published a design for a novel chip architecture that could allow quantum calculations to be performed using silicon CMOS (complementary metal-oxide-semiconductor) components – the basis of all modern computer chips.

In their new study, published today in the journal Nature Communications, the team combine two fundamental quantum techniques for the first time, confirming the promise of their approach.

Dzurak’s team had also previously shown that an integrated silicon qubit platform can operate with single-spin addressability – the ability to rotate a single spin without disturbing its neighbours.

They have now shown that they can combine this with a special type of quantum readout process known as Pauli spin blockade, a key requirement for quantum error correcting codes that will be necessary to ensure accuracy in large spin-based quantum computers. This new combination of qubit readout and control techniques is a central feature of their quantum chip design.

“We’ve demonstrated the ability to do Pauli spin readout in our silicon qubit device but, for the first time, we’ve also combined it with spin resonance to control the spin,” says Dzurak.

“This is an important milestone for us on the path to performing quantum error correction with spin qubits, which is going to be essential for any universal quantum computer.”

“Quantum error correction is a key requirement in creating large-scale useful quantum computing because all qubits are fragile, and you need to correct for errors as they crop up,” says lead author, Michael Fogarty, who performed the experiments as part of his PhD research with Professor Dzurak at UNSW.

“But this creates significant overhead in the number of physical qubits you need in order to make the system work,” notes Fogarty.

Dzurak says, “By using silicon CMOS technology we have the ideal platform to scale to the millions of qubits we will need, and our recent results provide us with the tools to achieve spin qubit error-correction in the near future.”

“It’s another confirmation that we’re on the right track. And it also shows that the architecture we’ve developed at UNSW has, so far, shown no roadblocks to the development of a working quantum computer chip.”

“And, what’s more, one that can be manufactured using well-established industry processes and components.”

CQC2T’S UNIQUE APPROACH USING SILICON

Working in silicon is important not just because the element is cheap and abundant, but because it has been at the heart of the global computer industry for almost 60 years. The properties of silicon are well understood and chips containing billions of conventional transistors are routinely manufactured in big production facilities.

Three years ago, Dzurak’s team published in the journal Nature the first demonstration of quantum logic calculations in a real silicon device with the creation of a two-qubit logic gate – the central building block of a quantum computer.

“Those were the first baby steps, the first demonstrations of how to turn this radical quantum computing concept into a practical device using components that underpin all modern computing,” says Professor Mark Hoffman, UNSW’s Dean of Engineering.

“Our team now has a blueprint for scaling that up dramatically.

“We’ve been testing elements of this design in the lab, with very positive results. We just need to keep building on that – which is still a hell of a challenge, but the groundwork is there, and it’s very encouraging.

“It will still take great engineering to bring quantum computing to commercial reality, but clearly the work we see from this extraordinary team at CQC2T puts Australia in the driver’s seat,” he added.

Other authors of the new Nature Communications paper are UNSW researchers Kok Wai Chan, Bas Hensen, Wister Huang, Tuomo Tanttu, Henry Yang, Arne Laucht, Fay Hudson and Andrea Morello, as well as Menno Veldhorst of QuTech and TU Delft, Thaddeus Ladd of HRL Laboratories and Kohei Itoh of Japan’s Keio University.

COMMERCIALISING CQC2T’S INTELLECTUAL PROPERTY

In 2017, a consortium of Australian governments, industry and universities established Australia’s first quantum computing company to commercialise CQC2T’s world-leading intellectual property.

Operating out of new laboratories at UNSW, Silicon Quantum Computing Pty Ltd (SQC) has the target of producing a 10-qubit demonstration device in silicon by 2022, as the forerunner to creating a silicon-based quantum computer.

The work of Dzurak and his team will be one component of SQC realising that ambition. UNSW scientists and engineers at CQC2T are developing parallel patented approaches using single atom and quantum dot qubits.

In May 2018, the then Prime Minister of Australia, Malcolm Turnbull, and the President of France, Emmanuel Macron, announced the signing of a Memorandum of Understanding (MoU) addressing a new collaboration between SQC and the world-leading French research and development organisation, Commissariat à l’Energie Atomique et aux Energies Alternatives (CEA).

The MoU outlined plans to form a joint venture in silicon-CMOS quantum computing technology to accelerate and focus technology development, as well as to capture commercialisation opportunities – bringing together French and Australian efforts to develop a quantum computer.

The proposed Australian-French joint venture would bring together Dzurak’s team, located at UNSW, with a team led by Dr Maud Vinet from CEA, who are experts in advanced CMOS manufacturing technology, and who have also recently demonstrated a silicon qubit made using their industrial-scale prototyping facility in Grenoble.

It is estimated that industries comprising approximately 40% of Australia’s current economy could be significantly impacted by quantum computing.

Possible applications include software design, machine learning, scheduling and logistical planning, financial analysis, stock market modelling, software and hardware verification, climate modelling, rapid drug design and testing, and early disease detection and prevention.

pSemiTM Corporation (formerly Peregrine Semiconductor), a Murata company focused on semiconductor integration, announces volume production of the PE43508 digital step attenuator (DSA). This mmWave product is the world’s first single-chip silicon-on-insulator (SOI) DSA to support the entire 9 kHz to 55 GHz frequency range. Ideal for 5G test and measurement applications, the PE43508 exemplifies pSemi’s high-performance capabilities at mmWave frequencies. The 55 GHz DSA maintains a monotonic response across the entire frequency range and features low insertion loss, low attenuation error and good return loss.

“At the IMS 2018 exhibition in June, we introduced the newest product in the pSemi high-frequency portfolio—a mmWave digital step attenuator,” says Jim Cable, CEO at pSemi. “As we announce volume production, I am excited to share that we are extending the operating frequency range of the PE43508 to 55 GHz. After additional testing, we concluded the original 50 GHz DSA name was selling this impressive product short. The PE43508 delivers exceptional performance beyond 50 GHz, further supporting pSemi’s claim that RF SOI can deliver a high-performing and reliable solution at high frequencies. It also demonstrates pSemi’s superior engineering talents and process capabilities in mmWave design.”

The 55 GHz DSA joins pSemi’s high-frequency portfolio which includes a 40 GHz switch (PE42524) and two 60 GHz switches (PE42525 and PE426525) based on the same UltraCMOS® technology platform. These monolithic ICs are ideal for applications, such as test and measurement and 5G wireless infrastructure, and can be used in more traditional high-frequency applications, such as very small aperture satellite terminals.

Features, Packaging, Pricing and Availability
The PE43508 is a 6-bit, 50-ohm DSA that offers wideband support from 9 kHz to 55 GHz. The PE43508 covers a 31.5 dB attenuation range in 0.5 dB and 1 dB steps, and it is capable of maintaining 0.5 dB and 1 dB monotonicity through 55 GHz. The PE43508 also delivers glitch-safe attenuation state transitions, meaning no increased power spike during a state transition.

The PE43508 has an extended temperature range from −40°C to +105°C, an HBM ESD rating of 1 kV and an easy-to-use digital control interface supporting both serial addressable and parallel programming. The DSA supports 1.8 V control signals and has an optional VSS_EXT bypass mode.

Offered as a flip-chip die, volume-production parts, evaluation kits and samples are available now. For 1K-quantity orders, each PE43508 is $50 USD.

In the quest for abundant, renewable alternatives to fossil fuels, scientists have sought to harvest the sun’s energy through “water splitting,” an artificial photosynthesis technique that uses sunlight to generate hydrogen fuel from water. But water-splitting devices have yet to live up to their potential because there still isn’t a design for materials with the right mix of optical, electronic, and chemical properties needed for them to work efficiently.

The HPEV cell’s extra back outlet allows the current to be split into two, so that one part of the current contributes to solar fuels generation, and the rest can be extracted as electrical power. Credit: Credit: Berkeley Lab, JCAP

Now researchers at the U.S. Department of Energy’s Lawrence Berkeley National Laboratory (Berkeley Lab) and the Joint Center for Artificial Photosynthesis (JCAP), a DOE Energy Innovation Hub, have come up with a new recipe for renewable fuels that could bypass the limitations in current materials: an artificial photosynthesis device called a “hybrid photoelectrochemical and voltaic (HPEV) cell” that turns sunlight and water into not just one, but two types of energy – hydrogen fuel and electricity. The paper describing this work was published on Oct. 29 in Nature Materials.

Finding a way out for electrons

Most water-splitting devices are made of a stack of light-absorbing materials. Depending on its makeup, each layer absorbs different parts or “wavelengths” of the solar spectrum, ranging from less-energetic wavelengths of infrared light to more-energetic wavelengths of visible or ultraviolet light.

When each layer absorbs light it builds an electrical voltage. These individual voltages combine into one voltage large enough to split water into oxygen and hydrogen fuel. But according to Gideon Segev, a postdoctoral researcher at JCAP in Berkeley Lab’s Chemical Sciences Division and the study’s lead author, the problem with this configuration is that even though silicon solar cells can generate electricity very close to their limit, their high-performance potential is compromised when they are part of a water-splitting device.

The current passing through the device is limited by other materials in the stack that don’t perform as well as silicon, and as a result, the system produces much less current than it could – and the less current it generates, the less solar fuel it can produce.

“It’s like always running a car in first gear,” said Segev. “This is energy that you could harvest, but because silicon isn’t acting at its maximum power point, most of the excited electrons in the silicon have nowhere to go, so they lose their energy before they are utilized to do useful work.”

Getting out of first gear

So Segev and his co-authors – Jeffrey W. Beeman, a JCAP researcher in Berkeley Lab’s Chemical Sciences Division, and former Berkeley Lab and JCAP researchers Jeffery Greenblatt, who now heads the Bay Area-based technology consultancy Emerging Futures LLC, and Ian Sharp, now a professor of experimental semiconductor physics at the Technical University of Munich in Germany – proposed a surprisingly simple solution to a complex problem.

“We thought, ‘What if we just let the electrons out?'” said Segev.

In water-splitting devices, the front surface is usually dedicated to solar fuels production, and the back surface serves as an electrical outlet. To work around the conventional system’s limitations, they added an additional electrical contact to the silicon component’s back surface, resulting in an HPEV device with two contacts in the back instead of just one. The extra back outlet would allow the current to be split into two, so that one part of the current contributes to solar fuels generation, and the rest can be extracted as electrical power.

When what you see is what you get

After running a simulation to predict whether the HPEC would function as designed, they made a prototype to test their theory. “And to our surprise, it worked!” Segev said. “In science, you’re never really sure if everything’s going to work even if your computer simulations say they will. But that’s also what makes it fun. It was great to see our experiments validate our simulations’ predictions.”

According to their calculations, a conventional solar hydrogen generator based on a combination of silicon and bismuth vanadate, a material that is widely studied for solar water splitting, would generate hydrogen at a solar to hydrogen efficiency of 6.8 percent. In other words, out of all of the incident solar energy striking the surface of a cell, 6.8 percent will be stored in the form of hydrogen fuel, and all the rest is lost.

In contrast, the HPEV cells harvest leftover electrons that do not contribute to fuel generation. These residual electrons are instead used to generate electrical power, resulting in a dramatic increase in the overall solar energy conversion efficiency, said Segev. For example, according to the same calculations, the same 6.8 percent of the solar energy can be stored as hydrogen fuel in an HPEV cell made of bismuth vanadate and silicon, and another 13.4 percent of the solar energy can be converted to electricity. This enables a combined efficiency of 20.2 percent, three times better than conventional solar hydrogen cells.

The researchers plan to continue their collaboration so they can look into using the HPEV concept for other applications such as reducing carbon dioxide emissions. “This was truly a group effort where people with a lot of experience were able to contribute,” added Segev. “After a year and a half of working together on a pretty tedious process, it was great to see our experiments finally come together.”

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $122.7 billion during the third quarter of 2018, an increase of 4.1 percent over the previous quarter and 13.8 percent more than the third quarter of 2017. Global sales for the month of September 2018 reached $40.9 billion, an uptick of 2.0 percent over last month’s total and 13.8 percent more than sales from June 2017. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Three-quarters of the way through 2018, the global semiconductor industry is on pace to post its highest-ever annual sales, comfortably topping last year’s record total of $412 billion,” said John Neuffer, president and CEO, Semiconductor Industry Association. “While year-to-year growth has tapered in recent months, September marked the global industry’s highest-ever monthly sales, and Q3 was its top-grossing quarter on record. Year-to-year sales in September were up across every major product category and regional market, with sales into China and the Americas continuing to lead the way.”

Regionally, sales increased compared to September 2017 in China (26.3 percent), the Americas (15.1 percent), Europe (8.8 percent), Japan (7.2 percent), and Asia Pacific/All Other (2.4 percent). Sales were up compared to last month in the Americas (6.0 percent), China (1.8 percent), and Europe (1.2 percent), but down slightly in Asia Pacific/All Other (-0.1 percent) and Japan (-0.6 percent).

For comprehensive monthly semiconductor sales data and detailed WSTS Forecasts, consider purchasing the WSTS Subscription Package. For detailed data on the global and U.S. semiconductor industry and market, consider purchasing the 2018 SIA Databook.

September 2018
Billions
Month-to-Month Sales
Market Last Month Current Month % Change
Americas 8.68 9.20 6.0%
Europe 3.53 3.57 1.2%
Japan 3.39 3.37 -0.6%
China 14.10 14.35 1.8%
Asia Pacific/All Other 10.43 10.42 -0.1%
Total 40.12 40.91 2.0%
Year-to-Year Sales
Market Last Year Current Month % Change
Americas 7.99 9.20 15.1%
Europe 3.28 3.57 8.8%
Japan 3.14 3.37 7.2%
China 11.36 14.35 26.3%
Asia Pacific/All Other 10.18 10.42 2.4%
Total 35.95 40.91 13.8%
Three-Month-Moving Average Sales
Market Apr/May/Jun Jul/Aug/Sept % Change
Americas 8.34 9.20 10.2%
Europe 3.67 3.57 -2.7%
Japan 3.39 3.37 -0.8%
China 13.59 14.35 5.6%
Asia Pacific/All Other 10.32 10.42 1.0%
Total 39.31 40.91 4.1%

Synopsys, Inc. (Nasdaq: SNPS) today announced the availability of Test Fusion technology with new test point functionality, providing design teams with powerful design-for-test (DFT) circuit modifications to reduce silicon test costs by an average of forty percent and increase defect detection while meeting design targets for power, performance, and area. Test Fusion ensures the test points avoid introducing routing congestion and minimize area impact, in contrast to traditional test point implementation techniques. RTL designers can easily deploy test points with a single step that automatically combines Synopsys’ SpyGlass® DFT ADV testability analysis, DFTMAX™ design-for-test, and Synopsys synthesis products, then run TetraMAX® II automatic test pattern generation (ATPG) to create efficient silicon manufacturing tests. The solution is fully certified to comply with the ISO 26262 automotive functional safety standard and is widely deployed among semiconductor manufacturers.

To meet lower cost and increasing quality requirements, semiconductor manufacturers seek new technologies to improve detecting defective silicon prior to shipment. Several industry segments, such as automotive, are challenged to meet manufacturing test cost goals while achieving quality levels for their integrated circuits (ICs) of less than one defective part per million. Synopsys test points assist meeting these requirements by modifying the design to improve the ability of TetraMAX II to generate silicon test programs. SpyGlass DFT ADV analyzes designs and determines the most optimal and effective locations for test points that both decrease test pattern volume and increase defect coverage. Test Fusion technology ensures DFTMAX and Synopsys synthesis tools work in combination to implement the test points at the selected locations while minimizing routing using physical design data. Furthermore, Test Fusion provides an unprecedented reduction of area and congestion by enabling multiple test points to share a single test register based on physical proximity.

“Semiconductor companies are increasingly concerned about meeting manufacturing test quality and cost goals while achieving IC area, power, and performance goals within predictable design schedules,” said Steve Pateras, senior director of marketing for Test Automation in Synopsys’ Design Group. “Physically-aware test points are just one of several innovative Test Fusion technologies we are bringing to market to address this growing challenge.”