Category Archives: Semiconductors

Total wafer shipments in 2018 year are expected to eclipse the all-time market high set in 2017 and continue to reach record levels through 2021, according to SEMI’s recent semiconductor industry annual silicon shipment forecast. The forecast of demand for silicon units for the period 2018 through 2021 shows polished and epitaxial silicon shipments totaling 12,445 million square inches in 2018; 13,090 million square inches in 2019; 13,440 million square inches in 2020, and 13,778 million square inches in 2021 (see table below).

“As new greenfield fab projects continue to emerge for memory and foundry, silicon shipments are expected to remain strong for 2019 and through 2021,” said Clark Tseng, director of Industry Research & Statistics at SEMI. “Silicon demand will continue to grow as semiconductor content increases in mobile, high-performance computing, automotive, and Internet of Things applications.”

2018 Silicon* Shipment Forecast (MSI = Millions of Square Inches)
Actual
Forecast
2016
2017
2018
2019
2020
2021
MSI
10,577
11,617
12,445
13,090
13,440
13,778
Annual Growth
3.0%
9.8%
7.1%
5.2%
2.7%
2.5%

*Total Electronic Grade Silicon Slices – Excludes Non-Polished Wafers

*Shipments are for semiconductor applications only and do not include solar applications

Source: SEMI (www.semi.org), October 2018

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or chips are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers shipped by the wafer manufacturers to the end-users. Data do not include non-polished or reclaimed wafers.

Gartner, Inc. today highlighted the top strategic technology trends that organizations need to explore in 2019. Analysts presented their findings during Gartner Symposium/ITxpo, which is taking place here through Thursday.

Gartner defines a strategic technology trend as one with substantial disruptive potential that is beginning to break out of an emerging state into broader impact and use, or which are rapidly growing trends with a high degree of volatility reaching tipping points over the next five years.

“The Intelligent Digital Mesh has been a consistent theme for the past two years and continues as a major driver through 2019. Trends under each of these three themes are a key ingredient in driving a continuous innovation process as part of a ContinuousNEXT strategy,” said David Cearley, vice president and Gartner Fellow. “For example, artificial intelligence (AI) in the form of automated things and augmented intelligence is being used together with IoT, edge computing and digital twins to deliver highly integrated smart spaces. This combinatorial effect of multiple trends coalescing to produce new opportunities and drive new disruption is a hallmark of the Gartner top 10 strategic technology trends for 2019.”

The top 10 strategic technology trends for 2019 are:

Autonomous Things

Autonomous things, such as robots, drones and autonomous vehicles, use AI to automate functions previously performed by humans. Their automation goes beyond the automation provided by rigid programing models and they exploit AI to deliver advanced behaviors that interact more naturally with their surroundings and with people.

“As autonomous things proliferate, we expect a shift from stand-alone intelligent things to a swarm of collaborative intelligent things, with multiple devices working together, either independently of people or with human input,” said Mr. Cearley. “For example, if a drone examined a large field and found that it was ready for harvesting, it could dispatch an “autonomous harvester.” Or in the delivery market, the most effective solution may be to use an autonomous vehicle to move packages to the target area. Robots and drones on board the vehicle could then ensure final delivery of the package.”

Augmented Analytics

Augmented analytics focuses on a specific area of augmented intelligence, using machine learning (ML) to transform how analytics content is developed, consumed and shared. Augmented analytics capabilities will advance rapidly to mainstream adoption, as a key feature of data preparation, data management, modern analytics, business process management, process mining and data science platforms. Automated insights from augmented analytics will also be embedded in enterprise applications — for example, those of the HR, finance, sales, marketing, customer service, procurement and asset management departments — to optimize the decisions and actions of all employees within their context, not just those of analysts and data scientists. Augmented analytics automates the process of data preparation, insight generation and insight visualization, eliminating the need for professional data scientists in many situations.

“This will lead to citizen data science, an emerging set of capabilities and practices that enables users whose main job is outside the field of statistics and analytics to extract predictive and prescriptive insights from data,” said Mr. Cearley. “Through 2020, the number of citizen data scientists will grow five times faster than the number of expert data scientists. Organizations can use citizen data scientists to fill the data science and machine learning talent gap caused by the shortage and high cost of data scientists.”

AI-Driven Development

The market is rapidly shifting from an approach in which professional data scientists must partner with application developers to create most AI-enhanced solutions to a model in which the professional developer can operate alone using predefined models delivered as a service. This provides the developer with an ecosystem of AI algorithms and models, as well as development tools tailored to integrating AI capabilities and models into a solution. Another level of opportunity for professional application development arises as AI is applied to the development process itself to automate various data science, application development and testing functions. By 2022, at least 40 percent of new application development projects will have AI co-developers on their team.

“Ultimately, highly advanced AI-powered development environments automating both functional and nonfunctional aspects of applications will give rise to a new age of the ‘citizen application developer’ where nonprofessionals will be able to use AI-driven tools to automatically generate new solutions. Tools that enable nonprofessionals to generate applications without coding are not new, but we expect that AI-powered systems will drive a new level of flexibility,” said Mr. Cearley.

Digital Twins

A digital twin refers to the digital representation of a real-world entity or system. By 2020, Gartner estimates there will be more than 20 billion connected sensors and endpoints and digital twins will exist for potentially billions of things. Organizations will implement digital twins simply at first. They will evolve them over time, improving their ability to collect and visualize the right data, apply the right analytics and rules, and respond effectively to business objectives.

“One aspect of the digital twin evolution that moves beyond IoT will be enterprises implementing digital twins of their organizations (DTOs). A DTO is a dynamic software model that relies on operational or other data to understand how an organization operationalizes its business model, connects with its current state, deploys resources and responds to changes to deliver expected customer value,” said Mr. Cearley. “DTOs help drive efficiencies in business processes, as well as create more flexible, dynamic and responsive processes that can potentially react to changing conditions automatically.”

Empowered Edge

The edge refers to endpoint devices used by people or embedded in the world around us. Edge computing describes a computing topology in which information processing, and content collection and delivery, are placed closer to these endpoints. It tries to keep the traffic and processing local, with the goal being to reduce traffic and latency.

In the near term, edge is being driven by IoT and the need keep the processing close to the end rather than on a centralized cloud server. However, rather than create a new architecture, cloud computing and edge computing will evolve as complementary models with cloud services being managed as a centralized service executing, not only on centralized servers, but in distributed servers on-premises and on the edge devices themselves.

Over the next five years, specialized AI chips, along with greater processing power, storage and other advanced capabilities, will be added to a wider array of edge devices. The extreme heterogeneity of this embedded IoT world and the long life cycles of assets such as industrial systems will create significant management challenges. Longer term, as 5G matures, the expanding edge computing environment will have more robust communication back to centralized services. 5G provides lower latency, higher bandwidth, and (very importantly for edge) a dramatic increase in the number of nodes (edge endoints) per square km.

Immersive Experience

Conversational platforms are changing the way in which people interact with the digital world. Virtual reality (VR), augmented reality (AR) and mixed reality (MR) are changing the way in which people perceive the digital world. This combined shift in perception and interaction models leads to the future immersive user experience.

“Over time, we will shift from thinking about individual devices and fragmented user interface (UI) technologies to a multichannel and multimodal experience. The multimodal experience will connect people with the digital world across hundreds of edge devices that surround them, including traditional computing devices, wearables, automobiles, environmental sensors and consumer appliances,” said Mr. Cearley. “The multichannel experience will use all human senses as well as advanced computer senses (such as heat, humidity and radar) across these multimodal devices. This multiexperience environment will create an ambient experience in which the spaces that surround us define “the computer” rather than the individual devices. In effect, the environment is the computer.”

Blockchain

Blockchain, a type of distributed ledger, promises to reshape industries by enabling trust, providing transparency and reducing friction across business ecosystems potentially lowering costs, reducing transaction settlement times and improving cash flow. Today, trust is placed in banks, clearinghouses, governments and many other institutions as central authorities with the “single version of the truth” maintained securely in their databases. The centralized trust model adds delays and friction costs (commissions, fees and the time value of money) to transactions. Blockchain provides an alternative trust mode and removes the need for central authorities in arbitrating transactions.

”Current blockchain technologies and concepts are immature, poorly understood and unproven in mission-critical, at-scale business operations. This is particularly so with the complex elements that support more sophisticated scenarios,” said Mr. Cearley. “Despite the challenges, the significant potential for disruption means CIOs and IT leaders should begin evaluating blockchain, even if they don’t aggressively adopt the technologies in the next few years.”

Many blockchain initiatives today do not implement all of the attributes of blockchain — for example, a highly distributed database. These blockchain-inspired solutions are positioned as a means to achieve operational efficiency by automating business processes, or by digitizing records. They have the potential to enhance sharing of information among known entities, as well as improving opportunities for tracking and tracing physical and digital assets. However, these approaches miss the value of true blockchain disruption and may increase vendor lock-in. Organizations choosing this option should understand the limitations and be prepared to move to complete blockchain solutions over time and that the same outcomes may be achieved with more efficient and tuned use of existing nonblockchain technologies.

Smart Spaces

A smart space is a physical or digital environment in which humans and technology-enabled systems interact in increasingly open, connected, coordinated and intelligent ecosystems. Multiple elements — including people, processes, services and things — come together in a smart space to create a more immersive, interactive and automated experience for a target set of people and industry scenarios.

“This trend has been coalescing for some time around elements such as smart cities, digital workplaces, smart homes and connected factories. We believe the market is entering a period of accelerated delivery of robust smart spaces with technology becoming an integral part of our daily lives, whether as employees, customers, consumers, community members or citizens,” said Mr. Cearley.

Digital Ethics and Privacy

Digital ethics and privacy is a growing concern for individuals, organizations and governments. People are increasingly concerned about how their personal information is being used by organizations in both the public and private sector, and the backlash will only increase for organizations that are not proactively addressing these concerns.

“Any discussion on privacy must be grounded in the broader topic of digital ethics and the trust of your customers, constituents and employees. While privacy and security are foundational components in building trust, trust is actually about more than just these components,” said Mr. Cearley. “Trust is the acceptance of the truth of a statement without evidence or investigation. Ultimately an organization’s position on privacy must be driven by its broader position on ethics and trust. Shifting from privacy to ethics moves the conversation beyond ‘are we compliant’ toward ‘are we doing the right thing.’”

Quantum Computing

Quantum computing (QC) is a type of nonclassical computing that operates on the quantum state of subatomic particles (for example, electrons and ions) that represent information as elements denoted as quantum bits (qubits). The parallel execution and exponential scalability of quantum computers means they excel with problems too complex for a traditional approach or where a traditional algorithms would take too long to find a solution. Industries such as automotive, financial, insurance, pharmaceuticals, military and research organizations have the most to gain from the advancements in QC. In the pharmaceutical industry, for example, QC could be used to model molecular interactions at atomic levels to accelerate time to market for new cancer-treating drugs or QC could accelerate and more accurately predict the interaction of proteins leading to new pharmaceutical methodologies.

“CIOs and IT leaders should start planning for QC by increasing understanding and how it can apply to real-world business problems. Learn while the technology is still in the emerging state. Identify real-world problems where QC has potential and consider the possible impact on security,” said Mr. Cearley. “But don’t believe the hype that it will revolutionize things in the next few years. Most organizations should learn about and monitor QC through 2022 and perhaps exploit it from 2023 or 2025.”

Gartner clients can learn more in the Gartner Special Report “Top 10 Strategic Technology Trends for 2019.” Additional detailed analysis on each tech trend can be found in the Gartner YouTube video “Gartner Top 10 Strategic Technology Trends 2019.”

A new approach in Fault Detection and Classification (FDC) allows engineers to uncover issues more thoroughly and accurately by taking advantage of full sensor traces.

By Tom Ho and Stewart Chalmers, BISTel, Santa Clara, CA

Traditional FDC systems collect data from production equipment, summarize it, and compare it to control limits that were previously set up by engineers. Software alarms are triggered when any of the summarized data fall outside of the control limits. While this method has been effective and widely deployed, it does create a few challenges for the engineers:

  • The use of summary data means that (1) subtle changes in the process may not be noticed and (2) the unmonitored section of the process will be overlooked by a typical FDC system. These subtle changes or the missed anomalies in unmonitored section may result in critical problems.
  • Modeling control limits for fault detection is a manual process, prone to human error and process drift. With hundreds of thousandssensors in a complex manufacturing process, the task of modeling control limits is extremely time consuming and requires a deep understanding of the particular manufacturing process on the part of the engineer. Non-optimized control limits result in misdetection: false alarms or missed alarms.
  • As equipment ages, processes change. Meticulously set control limit ranges must be adjusted, requiring engineers to constantly monitor equipment and sensor data to avoid false alarms or missed real alarm.

Full sensor trace detection

A new approach, Dynamic Fault Detection (DFD) was developed to address the shortcomings of traditional FDC systems and save both production time and engineer time. DFD takes advantage of the full trace from each and every sensor to detect any issues during a manufacturing process. By analyzing each trace in its entirety, and running them through intelligent software, the system is able to comprehensively identify potential issues and errors as they occur. As the Adaptive Intelligence behind Dynamic Fault Detection learns each unique production environment, it will be able to identify process anomalies in real time without the need for manual adjustment from engineers. Great savings can be realized by early detection, increased engineer productivity, and containment of malfunctions.

DFD’s strength is its ability to analyze full trace data. As shown in FIGURE 1, there are many subtle details on a trace, such as spikes, shifts, and ramp rate changes, which are typically ignored or go undetected by a traditional FDC systems, because they only examine a segment of the trace- summary data. By analyzing the full trace using DFD, these details can easily be identified to provide a more thorough analysis than ever before.

Figure 1

Dynamic referencing

Unlike traditional FDC deployments, DFD does not require control limit modeling. The novel solution adapts machine learning techniques to take advantage of neighboring traces as references, so control limits are dynamically defined in real time.  Not only does this substantially reduce set up and deployment time of a fault detection system, it also eliminates the need for an engineer to continuously maintain the model. Since the analysis is done in real time, the model evolves and adapts to any process shifts as new reference traces are added.

DFD has multiple reference configurations available for engineers to choose from to fine tune detection accuracy. For example, DFD can 1) use traces within a wafer lot as reference, 2) use traces from the last N wafers as reference, 3) use “golden” traces as reference, or 4) a combination of the above.

As more sensors are added to the Internet of Things network of a production plant, DFD can integrate their data into its decision-making process.

Optimized alarming

Thousands of process alarms inundate engineers each day, only a small percentage of which are valid. In today’s FDC systems, one of the main causes for false alarms is improperly configured Statistical Process Control (SPC) limits. Also, typical FDC may generate one alarm for each limit violation resulting in many alarms for each wafer process. DFD implementations require no control limits, greatly reducing the potential for false alarms.  In addition, DFD is designed to only issues one alarm per wafer, further streamlining the alarming system and providing better focus for the engineers.

Dynamic fault detection use cases

The following examples illustrate actual use cases to show the benefits of utilizing DFD for fault detection.

Use case #1– End Point Abnormal Etching

In this example, both the upper and lower control limits in SPC were not set at the optimum levels, preventing the traditional FDC system from detecting several abnormally etched wafers (FIGURE 2).  No SPC alarms were issued to notify the engineer.

Figure 2

On the other hand, DFD full trace comparison easily detects the abnormality by comparing to neighboring traces (FIGURE 3).  This was accomplished without having to set up any control limits.

Figure 3

Use case #2 – Resist Bake Plate Temperature

The SPC chart in Figure 4 clearly shows that the Resist bake plate temperature pattern changed significantly; however, since the temperature range during the process never exceeded the control limits, SPC did not issue any alarms.

Figure 4

When the same parameter was analyzed using DFD, the temperature profile abnormality was easily identified, and the software notified an engineer (FIGURE 5).

Figure 5

Use case #3 – Full Trace Coverage

Engineers select only a segment of sensor trace data to monitor because setting up SPC limits is so arduous. In this specific case, the SPC system was set up to monitor only the He_Flow parameter in recipe step 3 and step 4.  Since no unusual events occurred during those steps in the process, no SPC alarms were triggered.

However, in that same production run, a DFD alarm was issued for one of the wafers. Upon examination of the trace summary chart shown in FIGURE 6, it is clear that while the parameter behaved normally during recipe step 3 and step 4, there was a noticeable issue from one of the wafers during recipe step 1 and step 2.  The trace in red represents the offending trace versus the rest of the (normal) population in blue. DFD full trace analysis caught the abnormality.

Figure 6

Use case #4 – DFD Alarm Accuracy

When setting up SPC limits in a conventional FDC system, the method of calculation taken by an engineer can yield vastly different results. In this example, the engineer used multiple SPC approaches to monitor parameter Match_LoadCap in an etcher. When the control limits were set using Standard Deviation (FIGURE 7), a large number of false alarms were triggered.  On the other hand, zero alarms were triggered using the Meanapproach (FIGURE 8).

Figure 7

Figure 8

Using DFD full trace detection eliminates the discrepancy between calculation methods. In the above example, DFD was able to identify an issue with one of the wafers in recipe step 3 and trigger only one alarm.

Dynamic fault detection scope of use

DFD is designed to be used in production environments of many types, ranging from semiconductor manufacturing to automotive plants and everything in between. As long as the manufacturing equipment being monitored generates systematic and consistent trace patterns, such as gas flow, temperature, pressure, power etc., proper referencing can be established by the Adaptive Intelligence (AI) to identify abnormalities. Sensor traces from Process of Record (POR) runs may be used as starting references.

Conclusion

The DFD solution reduces risk in manufacturing by protecting against events that impact yield.  It also provides engineers with an innovative new tool that addresses several limitations of today’s traditional FDC systems.  As shown in TABLE 1, the solution greatly reduces the time required for deployment and maintenance, while providing a more thorough and accurate detection of issues.

 

TABLE 1
FDC

(Per Recipe/Tool Type)

 DFD

(Per Recipe/Tool Type)
FDC model creation 1 – 2 weeks < 1 day
FDC model validation and fine tuning 2 – 3 weeks < 1 week
Model Maintenance Ongoing Minimal
Typical Alarm Rate 100-500/chamber-day < 50/chamber-day
% Coverage of Number of Sensors 50-60% 100% as default
Trace Segment Coverage 20-40% 100%
Adaptive to Systematic Behavior Changes No Yes

 

 

TOM HO is President of BISTel America where he leads global product engineer and development efforts for BISTel.  [email protected].   STEWART CHALMERS is President & CEO of Hill + Kincaid, a technical marketing firm. [email protected]. 

The average revenue generated from processed wafers among the four biggest pure-play foundries (TSMC, GlobalFoundries, UMC, and SMIC) is expected to be $1,138 in 2018, when expressed in 200mm-equivalent wafers, which is essentially flat from $1,136 in 2017, according to a new analysis by IC Insights (Figure 1).  The average revenue per wafer among the Big 4 foundries peaked in 2014 at $1,149 and then slowly declined through last year, based on IC Insights’ extensive part-two analysis of the integrated circuit foundry business in the September Update to The 2018 McClean Report.

Figure 1

TSMC’s average revenue per wafer in 2018 is forecast to be $1,382, which is 36% higher than GlobalFoundries’ $1,014.  UMC’s average revenue per wafer in 2018 is expected to be only $715, about half of the projected amount at TSMC this year.  Furthermore, TSMC is the only foundry among the Big 4 that is expected to generate higher revenue per wafer (9% more) in 2018 than in 2013.  In contrast, GlobalFoundries, UMC, and SMIC’s 2018 revenue per wafer averages are forecast to decline by 1%, 10%, and 16%, respectively, compared to 2013.

Although the average revenue per wafer of the Big 4 foundries is forecast to be $1,138 this year, the amount generated is highly dependent upon the minimum feature size of the IC processing technology. Figure 2 shows the typical 2Q18 revenue per wafer for some of the major technology nodes and wafer sizes produced by pure-play foundries.  In 2Q18, there was more than a 16x difference between the 0.5µ 200mm revenue per wafer ($370) and the ≤20nm 300mm revenue per wafer ($6,050).  Even when using revenue per square inch, the difference is dramatic ($7.41 for the 0.5µ technology versus $53.86 for the ≤20nm technology).  Since TSMC gets such a large percentage of its sales from ≤45nm production, its revenue per wafer is expected to increase by a compound annual growth rate (CAGR) of 2% from 2013 through 2018 as compared to a -2% CAGR for the total revenue per wafer average of GlobalFoundries, UMC, and SMIC during this same timeperiod.

Figure 2

There will probably be only three foundries able to offer high-volume leading-edge production over the next five years (i.e., TSMC, Samsung, and Intel).  IC Insights believes these companies are likely to be fierce competitors among themselves—especially TSMC and Samsung—and as a result, pricing will likely be under pressure through 2022.

When chemists from the Institute of Physical Chemistry of the Polish Academy of Sciences in Warsaw were starting work on yet another material designed for the efficient production of nanocrystalline zinc oxide, they didn’t expect any surprises. They were greatly astonished when the electrical properties of the changing material turned out to be extremely exotic.

The exotic transformations causes that one of the precursors of zinc oxide, initially an insulator, at approx. 300 degrees Celsius goes to a state with electrical properties typical of metals, and at ~400 degrees Celsius it becomes a semiconductor. Credit: IPC PAS

The single source precursor (SSP) approach is widely regarded as one of the most promising of the various strategies employed for the preparation of semiconductor nanocrystalline materials. However, one of the key obstacles hampering both the rational design of SSPs and their controlled transformation to the desired nanomaterials with highly controlled physicochemical properties is the scarcity of mechanistic insights during the transformation process. Scientists from the Institute of Physical Chemistry of the Polish Academy of Sciences (IPC PAS) and the Faculty of Chemistry of Warsaw University of Technology (WUT) have revealed that in the thermal decomposition process of a pre-organized zinc alkoxide precursor the nucleation and growth of the semiconducting zinc oxide (ZnO) phase is preceded by cascade transformations involving the formation of previously unreported intermediate radical zinc oxo-alkoxide clusters with gapless electronic states. Up to now, these types of clusters have not been considered either as intermediate structures on the path to the semiconductor ZnO phase or as a potential species accounting for the various defect states of ZnO nanocrystals.

“We discovered that one of the groups of ZnO precursors that have been studied for decades, zinc alkoxide compounds, undergo previously unobserved physicochemical transformations upon thermal decomposition. Originally, the starting compound is an insulator, when heated it rapidly transforms into a material with conductor-like properties, and a further increase in temperature equally rapidly leads to its conversion into a semiconductor,” says Dr. Kamil Soko?owski (IPC PAS).

The design and preparation of well-defined nanomaterials in a controlled manner remains a tremendous challenge and is acknowledged to be the biggest obstacle for the exploitation of many nanoscale phenomena. Professor Lewiski’s (IPC PAS, PW) group has for many years been engaged in the development of effective methods of producing nanocrystalline forms of zinc oxide, a semiconductor with wide applications in electronics, industrial catalysis, photovoltaics and photocatalysis. One of the studied approaches is based on the single source precursors. The precursor molecules contain all components of the target material in their structure and only temperature is required to trigger the chemical transformation.

“We dealt with a group of chemical compounds with the general formula RZnOR, as single source pre-designed ZnO precursors. A common feature of their structure is the presence of the cubic [Zn4O4] core with alternating zinc and oxygen atoms terminated by organic groups R. When the precursor is heated, the organic parts are degraded, and the inorganic cores self-assemble, forming the final form of the nanomaterial,” explains Dr. Soko?owski.

The tested precursor had the properties of an insulator, with an energy gap of about five electronvolts. When heated, it eventually transformed into a semiconductor with an energy gap of approximately 3 eV.

“An exceptional result of our research was the discovery that at a temperature close to 300 degrees Celsius the compound suddenly transforms into almost gap-less electronic state, showing electrical properties rather more typical of metals. When the temperature rises to approximately 400 degrees, the energy gap suddenly expands to a width characteristic of semiconductor materials. Ultimately, thanks to the combination of advanced synchrotron experiments with quantum-chemical calculations, we have established all the details of these unique transformations,” says Dr. Adam Kubas (IPC PAS), who carried out the quantum-chemical calculations.

The spectroscopic measurements were carried out using methods developed by Dr. Jakub Szlachetko (Institute of Nuclear Physics PAS, Cracow) and Dr. Jacinto Sa (IPC PAS and Uppsala University) at the Swiss Light Source synchrotron facility at the Paul Scherrer Institute in Villigen, Switzerland. The material was heated in a reaction chamber, and then its electron structure was sampled using an X-ray synchrotron beam. The set-up allowed for real-time monitoring of the transformations taking place.

This detailed in situ study of the decomposition process of the zinc alkoxide precursor, supported by computer simulations, revealed that any nucleation or growth of a semiconducting ZnO phase is preceded by cascade transformations involving the formation of previously unreported intermediate radical zinc oxo-alkoxide clusters with gapless electronic states.

“In this process homolytic cleavage of the R-Zn bond is responsible for the initial thermal decomposition process. Computer simulations revealed that the intermediate radical clusters tend to dimerise though an uncommon bimetallic Zn-Zn-bond formation. The following homolytic O-R bond cleavage then leads to sub-nano ZnO clusters which further self-organise to the ZnO nanocrystalline phase,” says Dr. Kubas.

Up to now, the radical zinc oxo clusters formed have not been considered either as intermediate structures on the way to the semiconductor ZnO phase or as potential species accounting for various defect states of ZnO nanocrystals. In a broader context, a deeper understanding of the origin and character of the defects is crucial for structure-property relationships in semiconducting materials.

The research, funded by the National Science Centre and the TEAM grant of the Foundation for Polish Science co-financed by the European Union, will contribute to the development of more precise methods of controlling the properties of nanocrystalline zinc oxide. So far, with greater or lesser success, these properties have been explained with the help of various types of material defects. For obvious reasons, however, the analyses have not taken into account the possibility of forming the specific radical zinc-oxo clusters discovered by the Warsaw-based scientists in the material.

Since the 2003 discovery of the single-atom-thick carbon material known as graphene, there has been significant interest in other types of 2-D materials as well.

These materials could be stacked together like Lego bricks to form a range of devices with different functions, including operating as semiconductors. In this way, they could be used to create ultra-thin, flexible, transparent and wearable electronic devices.

However, separating a bulk crystal material into 2-D flakes for use in electronics has proven difficult to do on a commercial scale.

The existing process, in which individual flakes are split off from the bulk crystals by repeatedly stamping the crystals onto an adhesive tape, is unreliable and time-consuming, requiring many hours to harvest enough material and form a device.

Now researchers in the Department of Mechanical Engineering at MIT have developed a technique to harvest 2-inch diameter wafers of 2-D material within just a few minutes. They can then be stacked together to form an electronic device within an hour.

The technique, which they describe in a paper published in the journal Science, could open up the possibility of commercializing electronic devices based on a variety of 2-D materials, according to Jeehwan Kim, an associate professor in the Department of Mechanical Engineering, who led the research.

The paper’s co-first authors were Sanghoon Bae, who was involved in flexible device fabrication, and Jaewoo Shim, who worked on the stacking of the 2-D material monolayers. Both are postdocs in Kim’s group.

The paper’s co-authors also included students and postdocs from within Kim’s group, as well as collaborators at Georgia Tech, the University of Texas, Yonsei University in South Korea, and the University of Virginia. Sang-Hoon Bae, Jaewoo Shim, Wei Kong, and Doyoon Lee in Kim’s research group equally contributed to this work.

“We have shown that we can do monolayer-by-monolayer isolation of 2-D materials at the wafer scale,” Kim says. “Secondly, we have demonstrated a way to easily stack up these wafer-scale monolayers of 2-D material.”

The researchers first grew a thick stack of 2-D material on top of a sapphire wafer. They then applied a 600-nanometer-thick nickel film to the top of the stack.

Since 2-D materials adhere much more strongly to nickel than to sapphire, lifting off this film allowed the researchers to separate the entire stack from the wafer.

What’s more, the adhesion between the nickel and the individual layers of 2-D material is also greater than that between each of the layers themselves.

As a result, when a second nickel film was then added to the bottom of the stack, the researchers were able to peel off individual, single-atom thick monolayers of 2-D material.

That is because peeling off the first nickel film generates cracks in the material that propagate right through to the bottom of the stack, Kim says.

Once the first monolayer collected by the nickel film has been transferred to a substrate, the process can be repeated for each layer.

“We use very simple mechanics, and by using this controlled crack propagation concept we are able to isolate monolayer 2-D material at the wafer scale,” he says.

The universal technique can be used with a range of different 2-D materials, including hexagonal boron nitride, tungsten disulfide, and molybdenum disulfide.

In this way it can be used to produce different types of monolayer 2-D materials, such as semiconductors, metals, and insulators, which can then be stacked together to form the 2-D heterostructures needed for an electronic device.

“If you fabricate electronic and photonic devices using 2-D materials, the devices will be just a few monolayers thick,” Kim says. “They will be extremely flexible, and can be stamped on to anything,” he says.

The process is fast and low-cost, making it suitable for commercial operations, he adds.

The researchers have also demonstrated the technique by successfully fabricating arrays of field-effect transistors at the wafer scale, with a thickness of just a few atoms.

“The work has a lot of potential to bring 2-D materials and their heterostructures towards real-world applications,” says Philip Kim, a professor of physics at Harvard University, who was not involved in the research.

The researchers are now planning to apply the technique to develop a range of electronic devices, including a nonvolatile memory array and flexible devices that can be worn on the skin.

They are also interested in applying the technique to develop devices for use in the “internet of things,” Kim says.

“All you need to do is grow these thick 2-D materials, then isolate them in monolayers and stack them up. So it is extremely cheap — much cheaper than the existing semiconductor process. This means it will bring laboratory-level 2-D materials into manufacturing for commercialization,” Kim says.

“That makes it perfect for IoT networks, because if you were to use conventional semiconductors for the sensing systems it would be expensive.”

Data provided by the Semiconductor Industry Association (SIA) indicates that worldwide sales of semiconductors reached USD 40.16 Billion for the month of August 2018, representing an increase of 14.9% when compared to the August 2017 total of USD 34.96 Billion. Global sales in August 2018were 1.7% higher than the July 2018 total of USD 39.49 Billion. The semiconductor industry is one of the fastest growing industries of the technology sector. According to Stratistics MRC, many semiconductor companies are beginning to embrace IoT to drive new revenue and growth models. Squire Mining Ltd. (OTC: SQRMF), Taiwan Semiconductor Manufacturing Company Limited (NYSE: TSM), Applied Materials, Inc. (NASDAQ: AMAT), Qorvo, Inc. (NASDAQ: QRVO), Entegris, Inc. (NASDAQ: ENTG)

According to a recent report by Accenture, the semiconductor industry is the most bullish sector when it comes to the integration of blockchain within their industry and the impact of artificial intelligence. “Throughout the industry’s complex supply chain, blockchain simplifies business operations leveraging semiconductor chips and related technologies,” said Syed Alam, a Managing Director in Accenture Strategy who leads Accenture’s Semiconductor practice. “This faster traceability will improve companies’ business operations and accelerate delivery of their products to market – while enabling them to do so at lower costs. Semiconductor companies can also use blockchain to create, scale and manage technology-based collaborations and redefine future business transactions.”

Squire Mining Ltd. (OTCQB: SQRMF) is also listed on the Canadian Securities Exchange under the ticker (CSE: SQR). Just earlier today, the company announced breaking news that, “Ennoconn Corporation (“Ennoconn”) as our hardware manufacturer for next generation mining systems to mine Bitcoin Cash, Bitcoin and other associated cryptocurrencies. Ennoconn is a leading industrial motherboard designer and total hardware system solution provider headquartered in Taipei, Taiwan and listed on the Taiwan stock exchange (TPE:6414). In 2007, Foxconn Technology Group, the largest “Electronic Manufacturing Service” company in the world, became the majority shareholder of Ennoconn, forming a strong strategic alliance in embedded system and electronic manufacturing.

On August 21, 2018, Squire announced that AraSystems Technology Corp. (“AraSystems”), a subsidiary of Squire, had entered into a provisional non-binding agreement with a major global technology assembly company. This company, now revealed to be Ennoconn, will assist in the design and assembly of our next generation mining rig at such time as a working prototype of our debut ASIC chip is completed.

On October 3, 2018 Squire announced the successful completion and testing of its FPGA working prototype microchip, with early results of the terahash-to-energy consumption ratio, indicating that the final ASIC chip and mining system has the potential to reduce operational costs by up to 40% for enterprise mining facilities.

● This cost reduction was estimated by one leading enterprise mining group to be worth up to $60M per year in savings to their operations alone.

● The final ASIC chip and mining system together are expected to provide up to a four times improvement in the performance of mining the blockchain, a process that enables miners to be paid, thereby increasing the return on investment, and profit, for miners. Such calculations are based on comparisons with the majority of current generation mining machines operating inside enterprise facilities around the world.

Following this success, the Company has signed a binding Memorandum of Understanding with Ennoconn and funded work to commence Phase 1 design and development of AraSystem’s next generation mining system in collaboration with its partners in Taipei, Taiwan and in Seoul, South Korea. Definitive documentation will be entered into following delivery of final specifications and data sheets to Ennoconn later this month.

Squire’s engineers are currently working with Ennoconn to design and develop AraSystem’s mining rig which will house the debut ASIC chip currently under development by the Company’s subsidiary AraCore Technology Corp (“AraCore”), in conjunction with GaonChips and Samsung Electronics (see news releases dated September 25 and October 3, 2018). In turn, Ennoconn will be responsible for mass assembly of the mining rig once all design, development and testing work has been completed.

A prototype of the mining rig along with full specifications of the AraCore ASIC chip are expected to be presented at the CoinGeek Conference in London on November 28 – 30, 2018, with presales expected to commence on or around that date. Significant interest has already been expressed by several of the industry’s largest enterprise mining companies, which currently host hundreds of thousands of mining machines in their facilities across the world.”

‘We are very pleased to be partnering with the skilled engineers at Ennoconn, one of the world’s leading electronic manufacturing companies,’ stated Simon Moore, Executive Chairman and CEO of Squire. ‘As we launch our next generation mining rig with a suite of proprietary innovations, it’s imperative that our manufacturing partners have the talent, experience and capacity to not only deliver unique hardware, but also deliver best in class quality. We believe Ennoconn will help ensure the production of an exceptional mining rig for the marketplace,’ he said. Further, Mr. Moore noted, ‘based on initial interest from the sector, the potential for significant sales and the subsequent revenue for Squire is on track in the coming year which would make Squire and its partners a noteworthy industry provider of crypto mining hardware and next generation innovation on a global scale.’

Taiwan Semiconductor Manufacturing Company Limited (NYSE: TSM) is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry segment’s largest portfolio of process-proven libraries, IPs, design tools and reference flows. TSMC recently announced the initial availability of its Open Innovation Platform® Virtual Design Environment (OIP VDE), which enables semiconductor customers to securely design in the cloud, leveraging TSMC OIP design infrastructures within the flexibility of cloud infrastructures. OIP VDE is the result of TSMC collaboration with TSMC OIP design ecosystem partners and leading cloud providers to deliver a complete systems-on-chip (SoCs) design environment in the cloud. TSMC OIP VDE’s first implementations of digital RTL-to-GDSII and custom schematic capture-to-GDSII flows are via partnerships with TSMC’s inaugural Cloud Alliance partners, Amazon Web Services (AWS), Cadence, Microsoft Azure, and Synopsys. In TSMC’s enablement of OIP VDE, both digital and custom design flows have been validated in the cloud, along with OIP design collateral-including process technology files, PDKs, foundation IP, and reference flows. To ensure low barriers to entry and high technical support levels, Cadence and Synopsys act as the focal point helping customers to set up VDE and providing first line support.

Applied Materials, Inc. (NASDAQ: AMAT) is a developer of materials engineering solutions used to produce virtually every new chip and advanced display in the world. Applied Materials recently celebrated the 20th anniversary and 5,000th shipment of the Producer® platform, a manufacturing system that helps make virtually every chip in the world. The Producer platform was launched in July of 1998 to help enable chips to run faster by changing their wiring from aluminum to copper, which is a better conductor. The transition was needed by the industry to drive the performance and power improvements associated with Moore’s Law, but it also required many additional steps that could have made the progress unaffordable. To help, Applied Materials designed every element of the Producer platform to give customers the highest performance at the lowest possible operating cost. “With the landmark Producer platform, Applied achieved something that had never been done before on this scale: create a highly flexible architecture that can support multiple technology generations and still remain incredibly productive,” said G. Dan Hutcheson, Chief Executive Officer of VLSIresearch. “Today, the Producer platform continues to allow chipmakers to imagine and build chips in entirely new ways. Congratulations to Applied Materials on this impressive milestone for one of the most important process systems in the semiconductor industry.”

Qorvo, Inc. (NASDAQ: QRVO) recently introduced a new System in Package (SiP) that enables dynamic, simultaneous support for Zigbee® 3.0, Green Power, Thread and Bluetooth Low Energy (BLE). This new SiP integrates Qorvo power amplifier technology providing 20 dBm output, which is especially important for U.S. smart home applications. The Qorvo QPG6095M is a fully integrated SiP for ultra-low power wireless communications. It is BLE 5.0 and Zigbee 3.0 platform and product certified, and offers Green Power energy efficiency. This SiP also extends range and battery life and enables robust interference mitigation. The QPG6095M delivers optimized connectivity throughout the home, eliminating the need for complex mesh architectures and unnecessary battery consumption in intermediate devices. The QPG6095M blends Qorvo’s power amplifier (PA) technology with a multi-standard, multi-protocol chip. Its level of integration and performance benefit product designers by lowering development costs and speeding time to market. Cees Links, General Manager of Qorvo’s Wireless Connectivity business unit, said, “This new SiP is another example of Qorvo’s commitment to combining and leveraging RF technologies to improve the consumer’s connected experience. Developers can now deliver BLE, Zigbee and Thread simultaneously with more range and reliability, and reduce concerns about future compatibility.”

Entegris, Inc. (NASDAQ: ENTG) is a developer and provider of specialty chemicals and advanced materials solutions for the microelectronics industry and other high-tech industries. Entegris, Inc. recently released the next generation EUV 1010 Reticle Pod for high-volume IC manufacturing using extreme ultraviolet (EUV) lithography. Developed in close collaboration with ASML, one of the world’s largest manufacturers of chip-making equipment, Entegris’s EUV 1010 is the first to be qualified by ASML for use in the NXE:3400B and beyond. As the semiconductor industry begins ramping EUV lithography for the high-volume manufacturing (HVM) of advanced technology nodes, keeping EUV reticles defect-free is more demanding than ever. Entegris’s EUV 1010 Reticle Pod is now fully qualified by ASML for their latest generation scanner having demonstrated outstanding protection of the EUV reticles, including against the most critical particle challenges. As a result, Entegris’s EUV 1010 enables customers to safely transition to smaller and smaller line widths, as needed for the most advanced lithography processes.

GLOBALFOUNDRIES today announced the addition of nine new partners to its growing RFwave Partner Program, including Akronic, Ask Radio, Catena, University of Waterloo Centre for Intelligent Antenna and Radio Systems (CIARS), Giga Solution, Helic, Incize, Mentor Graphics and Xpeedic Technology. These new partners will provide unique mmWave test and characterization capabilities along with design services, IP and EDA solutions that will enable GF clients to rapidly implement RF designs in applications spanning Internet-of-Things (IoT), mobile, RF connectivity, and networking markets.

The RFwave Partner Program builds upon GF’s industry-leading radio frequency (RF) solutions, such as FD-SOI, RF CMOS (bulk and advanced CMOS nodes), RF SOI and silicon germanium (SiGe) technologies. The program provides a low-risk, cost-effective path for designers seeking to build highly optimized RF solutions for a range of wireless applications such as IoT across various wireless connectivity and cellular standards, standalone or transceiver integrated 5G front end modules, mmWave backhaul, automotive radar, small cell and fixed wireless and satellite broadband.

“As the RFwave program continues to expand, partners play a critical role in helping to serve our growing number of clients and extend the reach of our RF ecosystem by providing innovative RF-tailored solutions and services,” said Mark Ireland, vice president of ecosystem partnerships at GF. “These new partners will help drive deeper engagement and enhance technology collaboration, including tighter interlock around quality, qualification and development methodology, enabling us to deliver advanced highly integrated RF solutions.”

GF is focused on building strong ecosystem partnerships with industry leaders. With the RFwave program, GF’s partners and clients can now benefit from a greater availability of resources to deliver innovative, highly optimized RF solutions. The new partners join current RFwave Program members including asicNorth, Cadence, CoreHW, CWS, Keysight Technologies, Spectral Design, and WEASIC.

According to Allied Market Research, the global compound semiconductor market was valued at USD 66,623 million in 2016 and is expected to reach USD 142,586 million in 2023 while growing at a CAGR of 11.3% from 2017 to 2023. The report indicates that a compound semiconductor is composed of two or more elements. Numerous compound semiconductors can be obtained by changing the combination of elements. Some of the factors affecting the market include the increasing demand for optoelectronic devices, as well as the attraction of compound semiconductor’s significant features, such as less power consumption, low price, and reduced heat dissipation. Rise in usage of optical devices, photovoltaic cells, and modules & wireless communication products is expected to provide an attractive opportunity for the compound semiconductor market. Squire Mining Ltd. (OTC: SQRMF), Nvidia Corporation (NASDAQ: NVDA), Advanced Micro Devices, Inc. (NASDAQ: AMD), KLA-Tencor Corporation (NASDAQ: KLAC), Maxim Integrated Products, Inc. (NASDAQ: MXIM)

As semiconductor technology begins to advance, new segments are swiftly being integrated into the market, such as Machine Learning. AI has observed significant growth in recent years. Initially, AI was considered a topic for academicians, though in recent years with development of various technologies, AI has turned into reality and is influencing many lives and businesses. According to MarketsandMarkets the global artificial intelligence chipset market is expected to be worth USD 16.06 Billion by 2022 and grow at a CAGR of 62.9% between 2016 and 2022.

Squire Mining Ltd. (OTCQB: SQRMF) is also listed on the Canadian Securities Exchange under the ticker (CSE: SQR). Earlier last week, the Company announced breaking news that, “to report on its prototype ASIC chip testing event held in Seoul, South Korea. With executives and board members from Squire, Future Farm, CoinGeek, Gaonchips and Samsung Electronics in attendance, Peter Kim, President of Squire’s subsidiary AraCore Technology Corp. (“Aracore”), and his team of front-end microchip engineers and programmers, unveiled and tested a working prototype mining system comprised of a newly engineered FPGA (field programmable gate array) ASIC microchip that will be converted into AraCore’s first ASIC chip utilizing 10 nanometer technology for mining Bitcoin Cash, Bitcoin and other associated cryptocurrencies. The test results confirm Aracore’s original design specifications indicating that the ASIC chip, once mass manufactured by Samsung Electronics, will be capable of delivering a projected hash rate of 18 to 22 terahash per second (TH/s) with an energy consumption of between 700 and 800 watts.

Taras Kulyk, Chief Executive Officer of CoinGeek Mining and Hardware, said “The CoinGeek team is very pleased with the progress of our strategic partners; Squire Mining and Aracore. With this next generation technology, CoinGeek will continue to pull the blockchain industry out of the proverbial basement and into the boardroom.”

Stefan Matthews, Chairman of nChain, one of the industry leaders in blockchain research and development, and a director of Squire Mining added, “The early results indicate that this ASIC microchip has the potential to be the next generation leader in providing hash power for enterprise mining of Bitcoin Cash and other associated crypto currencies. It has also demonstrated the potential to rapidly process consensus protocols across the blockchain faster whilst utilizing less energy than anything currently in this sector.”

Hash rate speed and microchip efficiency are the two most important measuring criteria in the crypto-mining industry to enable end-users to maximize profitability and ROI in their day to day mining operations.

Simon Moore, Executive Chairman and CEO of Squire Mining, stated, “Aracore’s time and investment to date have been validated by the impressive results of this new microchip. Once completed, we believe the speed and efficiency of our ASIC microchip combined with our respective mining systems powered by this Samsung manufactured microchip together have the potential to substantially increase the profitability of enterprise mining facilities around the globe. We look forward to releasing our mining system to the market in the first half of next year through our exclusive distribution partners CoinGeek, and competing for a significant piece of this multi-billion-dollar enterprise mining market.”

About AraCore Technology Corp. – Aracore is a joint venture company established by Squire and Peter Kim to design and develop next generation ASIC chips for mining Bitcoin Cash, Bitcoin and other associated cryptocurrencies. Squire owns a 75% interest in Aracore and Peter Kim owns the remaining 25% interest.

About Squire Mining Ltd. – Squire is a Canadian based company engaged, through its subsidiaries, in the business of developing data mining infrastructure and system technology to support global blockchain applications in the mining space including applicable specific integrated circuit (ASIC) chips and next generation mining rigs to mine Bitcoin Cash, Bitcoin and other associated cryptocurrencies.”

Nvidia Corporation (NASDAQ: NVDA), in 1999, sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Nvidia recently announced that it invited the world’s top automotive safety and reliability company, TÜV SÜD, to perform a safety concept assessment of its new NVIDIA Xavier system-on-chip (SoC). The 150-year-old German firm’s 24,000 employees assess compliance to national and international standards for safety, durability and quality in cars, as well as for factories, buildings, bridges and other infrastructure. As the world’s first autonomous driving processor, Xavier is the most complex SoC ever created. Its 9 billion transistors enable Xavier to process vast amounts of data. Its GMSL (gigabit multimedia serial link) high-speed IO connects Xavier to the largest array of lidar, radar and camera sensors of any chip ever built. “NVIDIA Xavier is one of the most complex processors we have evaluated,” said Axel Köhnen, Xavier lead assessor at TÜV SÜD RAIL. “Our in-depth technical assessment confirms the Xavier SoC architecture is suitable for use in autonomous driving applications and highlights NVIDIA’s commitment to enable safe autonomous driving.”

Advanced Micro Devices, Inc. (NASDAQ: AMD), for more than 45 years, has driven innovation in high-performance computing, graphics and visualization technologies ― the building blocks for gaming, immersive platforms and the datacenter. AMD recently announced the availability of world’s most powerful desktop processor, the 2nd Gen AMD Ryzen Threadripper 2990WX processor with 32 cores and 64 threads. Designed to power the ultimate computing experiences, 2nd Gen AMD Ryzen Threadripper processors are built using 12nm “Zen+” x86 processor architecture and offer the most threads on any desktop processor with the flagship model delivering up to 53% greater performance than the competition’s flagship model. Second Gen AMD Ryzen Threadripper processors support the most I/O2, and are compatible with existing AMD X399 chipset motherboards via a simple BIOS update, offering builders a broad choice for designing the ultimate high-end desktop or workstation PC. “We created Ryzen Threadripper processors because we saw an opportunity to deliver unheard-of levels of multithreaded computing for the demanding needs of creators, gamers, and PC enthusiasts in the HEDT market,” said Jim Anderson, Senior Vice President and General Manager, Computing and Graphics Business Group, AMD. “With the 2nd Gen processor family we took that challenge to a whole new level – delivering the biggest, most powerful desktop processor the world has ever seen.”

KLA-Tencor Corporation (NASDAQ: KLAC), a provider of process control and yield management solutions, partners with customers around the world to develop sinspection and metrology technologies. Recently, KLA-Tencor Corporation announced two new defect inspection products designed to address a wide variety of integrated circuit (IC) packaging challenges. The Kronos™ 1080 system offers production-worthy, high sensitivity wafer inspection for advanced packaging, providing key information for process control and material disposition. The ICOS™ F160 system examines packages after wafers have been diced, delivering fast, accurate die sort based on detection of key defect types-including sidewall cracks, a new defect type affecting the yield of high-end packages. The two new inspection systems join KLA-Tencor’s portfolio of defect inspection, metrology and data analysis systems that help accelerate packaging yield and increase die sort accuracy. “As chip scaling has slowed, advances in chip packaging technology have become instrumental in driving device performance,” said Oreste Donzella, Senior Vice President and Chief Marketing Officer at KLA-Tencor. “Packaged chips need to achieve simultaneous targets for device performance, power consumption, form factor and cost for a variety of device applications. As a result, packaging design has become more diverse and complex, featuring a range of 2D and 3D structures that are more densely packed and shrinking in size with every generation. At the same time, the value of the packaged chip has grown substantially, along with electronics manufacturers’ expectations for quality and reliability.”

Maxim Integrated Products, Inc. (NASDAQ: MXIM) develops innovative analog and mixed-signal products and technologies to make systems smaller and smarter, with enhanced security and increased energy efficiency. Maxim Integrated recently announced that automotive infotainment designers can now upgrade to bigger, higher resolution displays with greater ease, reduced cost and smaller solution size with the MAX20069 from Maxim Integrated Products, Inc. The MAX20069 provides the industry’s first solution integrating four I2C-controlled, 150mA LED backlight drivers and a four-output thin-film-transistor liquid-crystal display (TFT-LCD) bias in a single chip. The IC can reduce design footprint up to one-third compared to the closest competitor’s parts. “Automotive manufacturers are using more screens, larger panels and brighter displays across several vehicle lines to support a safer and more engaging experience on the road,” said Szukang Hsien, Executive Business Manager, Automotive Business Unit, Maxim Integrated. “Maxim’s integrated LED backlight driver and TFT-LCD bias solution supports newer panel types to help automotive manufacturers adopt lower cost yet higher resolution panels with smaller solution size and a high level of integration.”

Toshiba Memory Corporation (TMC) today announced the appointment of Stacy J. Smith as Executive Chairman, effective on October 1, 2018.

Smith brings a long and proven track record of executive leadership to TMC. He has extensive international experience, having both lived and led organizations in the Asia-Pacific, Latin America, Europe, the Middle East and Africa. He will work closely with CEO Yasuo Naruke to provide overall leadership to the business.

Smith previously spent three decades at Intel leading organizations across multiple disciplines. In his role as President, Manufacturing, Operations and Sales, from 2016 to 2018, he led 40,000 employees involved in worldwide manufacturing, technology development, supply chain, pricing and sales. He also served as Intel’s Chief Financial Officer for almost a decade and in this role also had responsibility for corporate strategy, M&A, and Intel Capital. Prior to that he served as Intel’s Chief Information Officer and Vice President for Sales for Europe, the Middle East and Africa.

Smith also brings strong board leadership experience. He currently serves as board chairman at Autodesk and as a director for Metromile. He served previously as a director for Virgin America and for GEVO. He also serves on the Board of Trustees for The Nature Conservancy of California and on the University of Texas McCombs School of Business Advisory Board. Smith attended The University of Texas at Austin, where he received his MBA in 1988 and his BBA in 1985.

“We are thrilled that Stacy is joining Toshiba Memory Corporation in this crucial leadership role at an important time in the company’s history,” said Yasuo Naruke, President and CEO of TMC. “With Stacy’s wealth of international leadership experience and knowledge of the semiconductor space, there is no doubt he is the perfect person to help lead our company in the next phase of growth as an independent company.”

“I am excited to take on this important challenge, and honored to join the TMC team,” said Smith. “Toshiba invented flash memory, and with TMC now operating as an independent company with increased capacity to invest in developing and growing semiconductor technology, the company has a strong growth trajectory ahead of it.”

Smith’s hiring follows the acquisition this year of TMC by an industry consortium led by Bain Capital Private Equity. Bain Capital Private Equity has a long history of successful investments in Japan including Skylark, Jupiter Shop Channel, BellSystem24, Domino’s Pizza Japan, Ooedo Onsen, and Asatsu-DK. The firm’s deep market knowledge, extensive local networks and expertise in driving operational improvement strategies have made Bain Capital a valued partner for Japanese companies.

“Stacy is the right leader to help TMC, already a technology leader in the flash memory industry, achieve its potential as an independent company,” said David Gross-Loh, a director of TMC and a managing director and co-head of Asia for Bain Capital Private Equity. “We are very pleased to welcome Stacy to TMC and look forward to working closely with him and the expanded management team.”