Category Archives: Semiconductors

STMicroelectronics (NYSE: STM) and Leti, a research institute of CEA Tech, today announced their cooperation to industrialize GaN (Gallium Nitride)-on-Silicon technologies for power switching devices. This power GaN-on-Si technology will enable ST to address high-efficiency, high-power applications, including automotive on-board chargers for hybrid and electric vehicles, wireless charging, and servers.

The collaboration focuses on developing and qualifying advanced power GaN-on-Silicon diode and transistor architectures on 200mm wafers, a market that the research firm IHS Markit estimates to grow at a CAGR of more than 20 percent from 2019 to 2024[1]. Together, in the framework of IRT Nanoelec, ST and Leti are developing the process technology on Leti’s 200mm R&D line and expect to have validated engineering samples in 2019. In parallel, ST will set up a fully qualified manufacturing line, including GaN/Si hetero-epitaxy, for initial production running in ST’s front-end wafer fab in Tours, France, by 2020.

In addition, given the attractiveness of GaN-on-Si technology for power applications, Leti and ST are assessing advanced techniques to improve device packaging for the assembly of high power-density power modules.

“Recognizing the incredible value of wide-bandgap semiconductors, ST’s contributions in Power GaN-on-Si manufacturing and packaging technologies with CEA-Leti move to arm us with the industry’s most complete portfolio of GaN and SiC products and capabilities, on top of our proven competence to manufacture high-quality, reliable products in volume,” said Marco Monti, President Automotive and Discrete Group, STMicroelectronics.

“Leveraging Leti’s 200mm generic platform, Leti’s team is fully committed to supporting ST’s strategic GaN-on-Si power-electronics roadmap and is ready to transfer the technology onto ST’s dedicated GaN-on-Si manufacturing line in Tours. This co-development, involving teams from both sides, leverages the IRT Nanoelec framework program to broaden the required expertise and innovate from the start at device and system levels,” said Leti CEO Emmanuel Sabonnadiere.

Lam Research Corporation (Nasdaq: LRCX), a global supplier of wafer fabrication equipment and services to the semiconductor industry, today announced the recipients of its 2018 Supplier Excellence Awards. Selected from Lam’s extensive list of preferred global suppliers, the companies were recognized for their outstanding performance, strategic services, and critical collaboration.

During Lam’s 2018 Supplier Day held on September 19th, the following six companies were presented with an award for Overall Supplier Excellence:

  • Fujikin Incorporated
  • HORIBA, LTD.
  • Texon Co., LTD.
  • TOTO, LTD.
  • Watlow Electric Manufacturing Co.
  • Wonik QnC Corporation

“Our top suppliers make it possible for us to provide exceptional, industry-leading products and services to our customers,” said Tim Archer, president and chief operating officer of Lam Research. “Close collaboration with these top performing suppliers has proven critical to delivering innovative, high-quality solutions for some of the industry’s most difficult challenges. We welcome the opportunity to honor their achievements and extend our sincere congratulations to each recipient of our 2018 Supplier Excellence Award.”

The RISC-V Foundation, a nonprofit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), today announced the keynotes for the first annual RISC-V Summit at the Santa Clara Convention Center in Santa Clara, Calif. from Dec. 3-6, 2018.

The Summit, in partnership with Informa’s Knowledge & Networking Division, KNect365, will gather the RISC-V community for a multi-track conference featuring tutorials, exhibitions and networking receptions. Leading technology companies and research institutions will share notable product updates, projects and implementations that accelerate the RISC-V ecosystem and reveal the future path for RISC-V. The initial keynotes for the Summit will be conducted by Antmicro, Facebook, Microchip, NXP, SiFive and Western Digital.

  • Michael Gielda, Vice President Business Development of Antmicro: “Accelerating Innovation: Why Google’s TPU Was Just the Start”
  • Robert Shearer, Director of Silicon Architecture and Modeling of Facebook: “The 100X Problem – How to Redefine Silicon for Augmented Reality”
  • Patrick Johnson, Vice President, Mixed Signal and FPGA Business Units of Microchip: “Enabling the Freedom to Innovate”
  • Rob Oshana, Vice President, Software Engineering of NXP: “Deepening the RISC-V Ecosystem to Drive Industry-Wide Adoption”
  • Yunsup Lee, Chief Technology Officer of SiFive: “Opportunities and Challenges of Building Silicon in the Cloud”
  • Martin Fink, Executive Vice President and Chief Technology Officer of Western Digital: “Unleashing Innovation from Core to Edge”

“This year has been a hallmark one for the RISC-V Foundation,” said Rick O’Connor, executive director of the RISC-V Foundation. “The RISC-V ecosystem is continuing to grow at a rapid pace, surpassing 150 member companies from 25 countries across the world. We’re excited to bring the RISC-V community together at the inaugural RISC-V Summit and end the year continuing the momentum from all the RISC-V milestones that have been achieved thus far.”

“This year has been a hallmark one for the RISC-V Foundation,” said Rick O’Connor, executive director of the RISC-V Foundation. “The RISC-V ecosystem is continuing to grow at a rapid pace, surpassing 150 member companies from 25 countries across the world. We’re excited to bring the RISC-V community together at the inaugural RISC-V Summit and end the year continuing the momentum from all the RISC-V milestones that have been achieved thus far.”

Micron Technology, Inc. (Nasdaq: MU) announced today that the company has appointed Mike Bokan as senior vice president of Worldwide Sales, effective Oct. 1, 2018. Bokan succeeds Steve Thorsen, who is retiring from Micron after 30 years with the company but will remain as an adviser through early November 2018 to ensure a smooth transition. Bokan is being promoted to senior vice president and will report directly to Micron President and CEO Sanjay Mehrotra.

“On behalf of the company, I want to thank Steve for his dedication to Micron’s success over the last three decades,” Mehrotra said. “He has been instrumental to the company’s tremendous growth over the years. During his tenure as head of Worldwide Sales, the company has enjoyed record sales, culminating in fiscal year 2018 revenue of over $30 billion. We wish Steve the very best in this next chapter of his life.”

“I am proud of my long career at Micron and have enjoyed building strong relationships with our customers around the world,” Thorsen said. “Mike and I have worked closely for many years, and I am confident he will be highly successful in taking on the leadership of the Worldwide Sales organization.”

Bokan is currently corporate vice president of Worldwide Sales at Micron. He joined the company in 1996 and held various sales management positions before moving to Micron’s Crucial division, where he eventually became general manager. In 2003, Bokan took on the role of director of Sales for Micron Technology. In 2007 he was promoted to senior director of Sales before becoming vice president of Worldwide OEM Sales in 2008 and corporate vice president of Worldwide Sales in 2018.

“Mike has been a great part of our sales leadership team,” Mehrotra said. “He has developed deep and trusted relationships with our OEM and hyperscale customers, as well as with our distribution partners. This is a natural next step for him, and we look forward to his leadership in driving our sales organization.”

“I am honored to follow in Steve’s footsteps and continue to broaden our market reach as memory and storage become increasingly critical to our customers,” Bokan said. “Micron is very well-positioned to take advantage of the growing demand for our products and solutions. I look forward to helping lead the company to the next level.”

Bokan earned a bachelor’s degree in business administration from Colorado State University.

By Christian G. Dieseldorff and Eugenia Liu

SEMI FabView update for calendar year Q3 2018

Global fab construction investment shows continuing strength, with 19 new fab projects expected to begin construction in 2019 and 2020, based on the latest data published in SEMI’s World Fab Forecast.

Fab investment is just one indicator of how growing demand in areas such as high-performance computing, data storage, artificial intelligence (AI), cloud computing, and automotive are driving the fourth consecutive year of spending growth in the semiconductor industry. Below are a few highlights* from September’s SEMI FabView:

Memory: Not fading

  • Micron plans to invest $3 billion by 2030 in Manassas, Virginia – These investments, driven by strong demand for automotive applications, are contemplated in Micron’s long-term model. The production ramp is anticipated to be in the first half of 2020.
  • SK Hynix to build new DRAM fab in Icheon (Gyeonggi Province), Korea – The construction, to be completed by the end of 2020, will adopt 1znm node (probably EUV). Total investment is estimated to exceed $13 billion.
  • Nanya Technology doubles 2018 capex plan – The increase is for additional DRAM capacity and more 20nm DRAM conversion (from 30nm).

200mm and below: Not leading edge, but continues to draw investment

  • Vanguard changes fab investment strategy – Vanguard will focus on 200 mm and has scrapped its plan for 300mm expansion.
  • Murata to invest into 150mm expansion – Murata announced a 5 billion Yen investment (US$44.6 million) in a new fab extension in Vantaa, Finland.

Investment, M&A in Analog, Logic, Power and Opto Segments

  • Texas Instruments is looking to invest $3.2 billion in new fab construction in 2019 – Texas Instruments is eyeing Richardson, Texas and also considering sites outside Texas.
  • Bosch 300mm fab in Dresden, Germany – Bosch held a groundbreaking ceremony on April 24. Equipment installation is expected in 2H19.
  • Microchip completes acquisition of Microsemi – Microchip closed its $8.45 billion acquisition of Microsemi on May 29. Microsemi has five fabs in the U.S. with a wide range of semiconductor products and system solutions.

New fabs in China keep on coming

  • Shanghai Jita Semiconductor/Huada Semiconductor – Shanghai Jita Semiconductor, a subsidiary of Huada Semiconductor and China Electronics Corporation (CEC), announced plans earlier this month to build both 200 mm and 300 mm semiconductor fabs for analog and power semiconductors in Shanghai. The combined fab investment will total $5.18 billion.
  • Hamamatsu Photonics building 200 mm fab – Hamamatsu announced that it is building a new facility Investment of 2.8 billion Yen (US$25 million) to boost opto semiconductor capacity. Production is anticipated to start in late 2019.

*Actual FabView updates provide more detail

SEMI FabView, a mobile-friendly, interactive version of SEMI’s popular World Fab Forecast, delivers on-demand fab information such as fab spending and capacity for over 1,200 facilities, including over 60 planned facilities worldwide, across a wide range of product segments including Power, GPU, Memory, Foundry, MEMS and Sensors fabs. Fab data include region, start of construction, operation, construction and equipment spending, capacity, wafer sizes, product types and geometries. SEMI FabView subscribers receive forecast model updates through SEMI’s World Fab Database.  Click here for a trial if you want to experience SEMI FabView first hand.

Christian G. Dieseldorff is senior principal analyst and Eugenia Liu is senior product marketing manager, Industry Research and Statistics, SEMI, Milpitas, California. 

Originally published on the SEMI blog.

Toshiba Memory Corporation and Western Digital Corporation (NASDAQ:WDC) yesterday celebrated the opening of a new semiconductor fabrication facility, Fab 6, and the Memory R&D Center, at Yokkaichi operations in Mie Prefecture, Japan.

Fab 6 and Memory R&D Center, Yokkaichi Operations (Photo: Business Wire)

Toshiba Memory started construction of Fab 6, a dedicated 3D flash memory fabrication facility, in February 2017. Toshiba Memory and Western Digital have installed cutting-edge manufacturing equipment for key production processes including deposition and etching. Mass production of 96-layer 3D flash memory utilizing the new fab began earlier this month.

Demand for 3D flash memory is growing for enterprise servers, data centers and smartphones, and is expected to continue to expand in the years ahead. Further investments to expand its production will be made in line with market trends.

The Memory R&D Center, located adjacent to Fab 6, began operations in March of this year, and will explore and promote advances in the development of 3D flash memory.

Toshiba Memory and Western Digital will continue to cultivate and extend their leadership in the memory business by actively developing initiatives aimed at strengthening competitiveness, advancing joint development of 3D flash memory, and making capital investments according to market trends.

Dr. Yasuo Naruke, President and CEO of Toshiba Memory said, “We are excited about opportunities to expand the market for our latest generation of 3D flash memory. Fab 6 and Memory R&D Center enable us to maintain our position as a leading player in the 3D flash memory market. We are confident that our joint venture with Western Digital will allow us to continue producing leading edge memories at Yokkaichi.”

“We are pleased to be opening Fab 6 and the Memory R&D Center with our valued partner Toshiba Memory. For nearly two decades, the successful collaboration between our companies has fostered growth and innovation of NAND flash technology,” said Steve Milligan, Chief Executive Officer, Western Digital. “We are ramping production of 96-layer 3D NAND to address the full range of end market opportunities from consumer and mobile applications to cloud data centers. Fab 6 is a cutting-edge facility that will enable us to further our technology and cost leadership position in the industry.”

University of Groningen physicists in collaboration with a theoretical physics group from Universität Regensburg have built an optimized bilayer graphene device which displays both long spin lifetimes and electrically controllable spin-lifetime anisotropy. It has the potential for practical applications such as spin-based logic devices. The results were published in Physical Review Letters on 20 September.

The tremendous development of computer systems over the last 60 years has increased their capability enabling them to spread into nearly all aspects of our daily life. The development approach of the last decades has been to miniaturize the elements on a computer chip. This has now reached scales below 100 atoms and is approaching its fundamental limit. Since the increasing range of applications makes higher demands of performance and energy efficiency, new concepts are required which can provide enhanced functionalities.

Spintronics

In this context, researchers are studying the use of spins for the transport and storage of information. Spin is a quantum mechanical property of electrons, which gives them a magnetic moment that could be used to transfer or store information. The field of spin-based electronics (spintronics) has already made its way into the hard drives of computers, and also promises to revolutionize the processing units.

A focus of spintronics research is on optimizing materials for the transport and control of spins. Graphene is an excellent conductor of electron spins, but it is hard to control spins in this material because of their weak interaction with the carbon atoms (the spin-orbit coupling). Previous work by the University of Groningen Physics of Nanodevices group led by Professor Bart van Wees placed graphene in close proximity to a transition metal dichalcogenide, a layered material with a high intrinsic spin-orbit coupling strength. The high spin-orbit coupling strength was transferred to graphene via a short-range interaction at the interface. This made it possible to control the spin currents, but was at the cost of reduced spin life.

Control of spin currents

In the new study, the researchers managed to control spin currents in a graphene bilayer. ‘This was actually predicted in a theoretical paper in 2012, but the technology to measure the effect accurately only became available recently’, explains Christian Leutenantsmeyer, a Ph.D. student in the Van Wees group and first author of the PRL paper. The paper is a collaboration between the Van Wees group and a theoretical physics group from Universität Regensburg in Germany.

The 2012 paper predicted anisotropic spin transport in graphene bilayers as a consequence of spin-orbit coupling in bilayer graphene. Anisotropic spin transport describes the situation in which spins pointing either in or out of the graphene plane are conducted with different efficiencies. This was indeed observed in the devices Leutenantsmeyer and his colleagues produced.

Insight

The spin current could also be controlled using spin-lifetime anisotropy since in-plane spins live much shorter than out-of-plane ones, and could be used in devices to polarize spin currents. Leutenantsmeyer: ‘We found that the strength anisotropy is comparable to graphene/transition metal dichalcogenide devices, but we observed a 100 times larger spin lifetime. We therefore achieved both efficient spin transport and efficient control of spins.’

The work provides insight into the fundamental properties of spin-orbit coupling in bilayer graphene. ‘And furthermore, our findings open up new avenues for the efficient electrical control of spins in high-quality graphene, a milestone for graphene.’

NXP Semiconductors N.V. (NASDAQ: NXPI) today announced that on September 19, 2018 (the “Closing Date”) its subsidiaries NXP B.V and NXP Funding LLC (the “Borrowers”), the lenders party thereto and Barclays Bank Plc, as administrative agent, entered into a US$1,000,000,000 senior unsecured bridge term credit facility agreement (the “Bridge Term Credit Agreement”).  On the Closing Date, an aggregate principal amount of US$1,000,000,000 of term loans (the “Term Loans”) were borrowed under the Bridge Term Credit Agreement.  The Term Loans mature 364 days following the Closing Date and bear interest, at the option of the Borrowers, at either (a) a LIBOR rate plus an applicable margin of 1.5 percent or (b) a base rate plus an applicable margin of 0.5 percent.

The proceeds of the Loans hereunder shall be used for general corporate purposes of the Borrower as well as to finance parts of the announced equity buy-back program.

All present and future obligations of the Borrowers arising under and pursuant to the terms of the Bridge Term Credit Agreement are guaranteed pursuant to a guaranty agreement dated as of the Closing Date (the “Guaranty Agreement”) and made by NXP Semiconductors Netherlands B.V., Freescale Semiconductor Holdings V, Inc., and NXP USA, Inc., in favor of Barclays Bank Plc, as administrative agent.

Developing materials suitable for use in optoelectronic devices is currently a very active area of research. The search for materials for use in photoelectric conversion elements has to be carried out in parallel with developing the optimal film formation process for each material, and this can take a few years for just one material. Until now there has been a trade-off, balancing electronic properties and material morphology. Researchers at Osaka University have developed a two-step process that can produce materials with good morphological properties in addition to excellent photoresistor performance. Their findings were published in the Journal of Physical Chemistry Letters.

The powder sample is insoluble, therefore fabrication of devices using wet processes is not possible. Credit: Osaka University

Bismuth sulfide, Bi2S3, belongs to a class of materials known as metal chalcogenides, which show significant promise owing to their optical and electronic properties. However, the performance of Bi2S3-based photoresponsive devices is dependent on the method used to process the film, and many of the reported approaches are hampered by low film crystallinity. Even when high crystallinity is achieved, the nature of the grains can have a negative effect on performance, therefore films with low surface roughness and large grain size are desirable.

“We searched more than 200 materials using a unique, ultra high-speed screening method that can evaluate performance, even when only powdered samples are available,” study corresponding author Akinori Saeki says. “We found that bismuth sulfide, which is inexpensive and less toxic than conventional inorganic solar cell materials, can be processed in a way that does not compromise its excellent photoelectrical properties.”

The technique used produces a 2D layered film in two treatment steps; solution spin-coating followed by crystallization. The photo response performance of the resulting film showed improvements of 6-100 times compared with those of films prepared using other processing methods. Owing to the non-toxic and abundant nature of bismuth and sulfur, the findings are expected to influence the development of commercial optoelectronic devices including solar cells.

“We demonstrated a facile processing technique that does not compromise material performance,” lead author Ryosuke Nishikubo says. “We believe that solution-processable bismuth-based semiconductors are viable alternatives to commercially available inorganic solar cells and show promise for widespread future use. The fact that they are non-toxic also sets them apart from other alternative optoelectronic materials, such as lead halide perovskites.”

Processing materials for device applications without compromising their electronic properties is important for making materials commercially relevant. The reported process has been used to successfully prepare other metal sulfide semiconductors such as lead sulfide, demonstrating the versatility of the approach.

By Anand Chamarthy

Materials innovation has always been vital to the semiconductor industry. In the past, it was high-κ gate dielectrics. Today, Cobalt is seen as a replacement for Tungsten in middle-of-line (MOL) contacts.

What materials innovation will the future bring?

A likely answer is Graphene, the wonder material discovered in 2004.

Graphene is one atomic layer of carbon, the thinnest and strongest material that has ever existed. It is 200 times stronger than steel and the lightest material known to man (1 square meter weighing around 0.77 mg). It is an excellent electrical and thermal conductor at room temperature with an electron mobility of ~ 200,000

cm2.V-1.s-1. At one atomic layer, graphene is flexible and transparent. Other notable properties of Graphene are its uniform absorption of light across the visible and near infrared spectrum and its applicability towards spintronics-based devices.

Graphene and Moore’s Law

Moore’s Law scaling can be broken down into 4 key areas:

  • Lithography
  • FET
  • Advanced Packaging (2.5D and 3D IC)
  • Interconnect Material

Solutions for upcoming nodes are starting to emerge in the first two areas (EUV and Nanowire- or Nanosheet-based FET respectively). Graphene play an important role in the latter two areas. For advanced packaging, Graphene can be used as a heat spreader (to lower overall thermal resistance), or as an EM shield (to lower crosstalk) as part of a 3D IC package.

Active Graphene device layers can potentially be stacked on top of each other using a low-temperature transfer process (< 400°C) to allow for a dense heterogeneous “memory near compute” configuration. This is an area DARPA is actively researching as part of its new $1.5 billion Electronics Resurgence Initiative.

Regarding interconnects, Copper interconnects are running out of steam and becoming a major IC bottleneck (projected 40% total delay for 7 nm node). Graphene’s high electron mobility and thermal conductivity make it an attractive interconnect material for MOL and back-end-of-line (BEOL), especially at line widths < 30 nm.

Graphene Device Applications

Graphene-based semiconductor applications are already starting to hit the market. A fully integrated optical transceiver (with a Graphene modulator and photodetector) operating at 25 Gb/s/channel was on display at the recent Mobile World Congress in Barcelona. San Diego-based Nanomedical Diagnostics is selling a medical device that uses a Graphene biosensor. Europe-based Emberion is building Graphene optoelectronic sensors that might find a home in LIDAR applications, where there is currently a focus on improving sensing in low-light conditions.

What will the overall Graphene roadmap in the semiconductor industry look like? The history of ion implantation serves as a good example of how a fundamental scientific discovery moves from the lab to the foundry floor.

The dominant view in the semiconductor industry at the time was that ion implantation would not work in practice (vs. thermal diffusion) and that, if it did, it would only marginally improve the manufacturing yields of existing products. There was nothing obvious about the transfer of ion bombardment techniques from nuclear physics research to semiconductor production.

Varian (led by British physicist Peter Rose) built a new, advanced ion implant tool that Mostek (DRAM manufacturer based in Texas) was able to use to create MOS ICs with clear competitive advantages. The successful collaboration between Varian and Mostek was the turning point in the development of ion implantation as a major semiconductor manufacturing process. Over the next few years, semiconductor firms used ion implantation in a growing number of process steps and, by the late 1970s, it became one of the main processes used in semiconductor manufacturing.

Likewise, the Graphene world needs to work closely with the semiconductor industry to develop the tools and techniques required to solve fundamental issues around Graphene growth (good uniformity over large area, low defect density) and Graphene transfer (high throughput, CMOS compatible). It is only then will we fully realize a future that includes 2D materials.

The first step in this process is cross-industry education and initiating the dialogue between semiconductor industry and graphene companies. The National Graphene Association will be hosting the largest gathering of graphene companies and commercial stakeholders at the Global Graphene Expo & Conference, October 15-17, 2018, in Austin, Texas.

Learn more about graphene at the upcoming Global Graphene Expo & Conference with dedicated panels of experts and investors, and roundtable discussions on how Graphene will impact the semiconductor industry. The event promo code is SEMINGA.

About the Author

Anand Chamarthy is the CEO and Co-Founder of Lab 91, an Austin-based startup that is working towards Graphene/CMOS integration at the foundry level. Anand can be reached at [email protected].

About the National Graphene Association

The National Graphene Association is the main organization and body in the U.S. promoting and advocating for commercialization of graphene and addressing critical issues such as standards and policy development.

Originally published on the SEMI blog.