Category Archives: Semiconductors

Mentor, a Siemens business, today announced LightSuite™ Photonic Compiler – the industry’s first integrated photonic automated layout system. This new tool enables companies designing integrated photonic layouts to describe designs in the Python language, from which the tool then automatically generates designs ready for fabrication. The resulting design is “Correct by Calibre” – with the implementation precisely guided by Mentor’s Calibre® RealTime Custom verification tool. LightSuite Photonic Compiler enables designers to generate as well as update large photonic layouts in minutes versus weeks.

With this breakthrough technology, companies can dramatically speed the development of integrated photonic designs that will bring speed-of-light communications directly into high-speed networking and high-performance computing (HPC) systems. It also speeds the development of more cost-effective LiDAR technology, which is seen as essential to enabling the mass deployment of autonomous vehicles.

“Mentor’s LightSuite Photonic Compiler represents a quantum leap in automating what has up to now been a highly manual, full-custom process that required deep knowledge of photonics as well as electronics,” said Joe Sawicki, vice president and general manager of the Design-to-Silicon Division at Mentor, a Siemens business. “With the new LightSuite Photonic Compiler, Mentor is enabling more companies to push the envelope in creating integrated photonic designs.”

“LightSuite Photonic Compiler fixes the biggest roadblocks preventing industry-wide adoption of electro-optical design and simulation of photonic chips,” said M. Ashkan Seyedi, Ph.D., senior research scientist, Hewlett Packard Enterprise. “Photonic chips promise amazing performance, but designing circuits today is just too difficult and requires specialized knowledge. LightSuite Photonic Compiler circumvents those challenges and enables scalability. I’m thrilled to have worked with Mentor to develop this tool to make it possible for anyone to design and build photonic circuits as easily as designing electronic circuits.”

Until now, photonic designers have been forced to use analog, full-custom IC tools to create photonic designs. In this flow, designers manually place components from a process design kit (PDK) and then interconnect those components manually. Photonic components must be interconnected with curved waveguides. After they have manually placed and interconnected the components, they typically perform a full Calibre physical verification run to check for design rule violations, as Calibre DRC can find violations even in photonic designs.

Mentor designed the new LightSuite Photonic Compiler specifically for photonic layout so that engineers have complete control of their layouts and can use the tool to automatically perform the placement and interconnecting of both photonic and electrical components. The designers create a Python script that is used to drive the LightSuite Photonic Compiler. Initial placement can also be defined in Python, or come from a pre-placed OpenAccess design. Next, the tool interconnects photonics components with curved wave guides. As some of the components might contain built-in electrical elements, the tool will route these electrical connections simultaneously along with the curved waveguides.

LightSuite Photonic Compiler uses Calibre RealTime Custom during the inner placement and routing loop, resulting in a layout that is design-rule correct. The tool enables designers to perform “what-if” design exploration for photonics designs, which was prohibitively time consuming with manual layout. With this new level of automation, designers can generate a new layout in minutes versus weeks for large designs.

Mentor will demonstrate LightSuite Photonic Compiler at ECOC in Rome, September 24 – 26 at Stand 436. LightSuite Photonic Compiler will be available on October 1.

By Walt Custer

Global economy

Manufacturing activity continues to expand – but at a slowing pace (Chart 1). The Global PMI was 52.5 in August, down from 52.8 in July and its recent high of 54.5 in December. PMI values >50 indicate an expansion.

World manufacturing growth has slowed but its growth rate varies significantly by region. Chart 2 compares the PMI values over time for the World, USA, Europe and China. Recently China and Europe have registered slower growth but U.S. growth is expanding (based on the Institute for Supply Management’s PMI). How long U.S. manufacturing will continue to accelerate remains to be seen. Geopolitical issues abound.

Semiconductor industry

In the semiconductor industry both semiconductors and SEMI capital equipment continued to register double-digit growth in July (Chart 3), but these growth rates are now moderating. In July, World semiconductor shipments were up 17.4 percent and SEMI capital equipment sales rose 13.9 percent on a 3-month growth basis.

However, SEMI equipment growth rates also vary widely by region. Per Chart 4, China growth is accelerating, Taiwan and South Korea are contracting, and Europe and the USA are still expanding but at slower rates.

Timely World and regional industry information is key to understanding present and future business conditions and this data requires careful watching in these fast-changing times.

Walt Custer of Custer Consulting Group is an analyst focused on the global electronics industry.

Originally published on the SEMI blog.

The market for microcontrollers—the IC industry’s original system-on-chip (SoC) product category—is expected to continue hitting record-high annual revenues through 2022 after worldwide sales dropped 6% in 2016 because of a slowdown in MCU unit shipments. After drawing down MCU inventories in 2016, systems manufacturers stepped up purchases of microcontrollers in 2017 with unit shipments surging 22% and strong growth continuing in 2018.  In its Mid-Year Update to The 2018 McClean Report, IC insights raised its projection for MCU shipments to 18% in 2018 with the unit volume reaching nearly 30.6 billion. MCU revenues are now forecast to rise 11% in 2018 to an all-time high of $18.6 billion, followed by 9% growth in 2019 to about $20.4 billion (Figure 1).

Figure 1

The Mid-Year Update also raised the five-year growth projection of MCU sales to a CAGR of 7.2%, reaching nearly $23.9 billion in 2022, with unit shipments increasing by a compound annual growth rate of 11.1% to about 43.8 billion in the final forecast year.

The ASP for microcontrollers fell to the lowest point ever in 2017 and prices are continuing to drop at about the same rate in 2018. However, the annual rate of decline has eased in the last five years compared to earlier this decade.  IC Insights’ new forecast for MCU ASP shows the average selling price falling by a CAGR of -3.5% in the 2017-2022 period, much slower than the -5.8% decline seen during the 2012-2017 period and the 20-year CAGR of -6.3% between 1997 and 2017.

A key factor in the 2017 recovery of MCU sales from the decline in 2016 was a turnaround in the smartcard microcontroller segment. About 40% of total MCU shipments are currently for smartcard applications, but that is down from about half early in this decade. Excluding smartcard MCUs, sales of “general” microcontrollers for embedded systems, automated control, sensing applications, and IoT-connected things are forecast to grow 11% in 2018 to $16.4 billion after rising 14% in 2017.  Shipments of general MCUs are projected to climb 25% in 2018 to 18.9 billion units after rising 21% in 2017.   General microcontrollers now represent a little over 60% of MCU unit shipments and are forecast to reach 68% of the total in 2022.  Currently, general MCUs generate about 88% of total microcontroller revenues, and they are expected to reach 90% of the entire market value in 2022.

Across nearly all MCU applications, strong growth in 32-bit microcontrollers has reshaped the market as suppliers aggressively promote more powerful designs that are cost competitive with 8-bit and 16-bit devices, which have typically been used in consumer products and other high-volume systems.  In some cases new 32-bit MCUs are being priced below the cost of 8-bit microcontrollers.  On average, 32-bit MCUs were selling for about twice the amount of the ASP for all microcontrollers in 2012 ($1.76 for 32-bit versus $0.88 for total MCUs).  In 2018, the ASP for 32-bit MCUs is expected to be just $0.09 higher than the ASP for all MCUs, and by 2022, the difference is forecast to shrink to $0.05 ($0.60 for 32-bit versus an average of $0.55 for total MCUs).

SUNY Polytechnic Institute (SUNY Poly) announced today that Professor of Nanobioscience Dr. Nate Cady has been awarded $500,000 in funding from the National Science Foundation to develop advanced computing systems based on a novel approach to the creation of non-volatile memory architecture. This research, which will also support student opportunities, aims to advance today’s typical computing model, in which processing and memory are separate, by bringing them together to make the entire process faster and more energy efficient.

“I am proud to congratulate Professor Cady on this National Science Foundation (NSF) award which is focused on enabling advanced computing capabilities, and notably, has important implications for advances in artificial intelligence,” said SUNY Poly Interim President Dr. Grace Wang. “The NSF’s selection of Dr. Cady’s research for this funding exemplifies the quality and impact of SUNY Poly’s research where our faculty and students leverage our world-class high-tech resources, explore new frontiers, and develop critical technologies for our society.”

The research will enable the design of a scalable computing infrastructure that uses nanoscale non-volatile memory (NVM) devices for both storage and computation. One of the current limits to computing speed is the result of current personal computing architecture, which separates the processor and memory and leads to a cap on data throughput, known as the “von Neumann bottleneck.” By combining storage and computation on the same device, the project circumvents this barrier and creates scalable solutions for extreme-scale computing—computing that is up to one thousand times more capable than current comparable computing—based on wires that cross each other to form memory cells at every intersection. This more powerful capability is made possible because each memory cell, acting like a synapse of the human brain, can be switched on or off, similar to the 1’s and 0’s of current computing, but it can also store many other values between the on or off states, increasing the amount of information that a given memory cell can store exponentially.

“This grant showcases the incredible potential of our faculty to tackle real-world problems with high-tech solutions that stem from the SUNY Poly’s advanced labs, cleanrooms, and capabilities. This news is especially exciting for a number of our graduate students who will be able to focus on this promising research area where they will be at the cutting-edge,” said SUNY Poly Interim Provost Dr. Steven Schneider.

“Dr. Cady’s research is a powerful example of the kind of expertise that SUNY Poly’s faculty possess as our innovation-centered ecosystem provides us with unique opportunities to move the technologies of the future forward,” said SUNY Poly Interim Dean of the College of Nanoscale Sciences; Empire Innovation Professor of Nanoscale Science; and Executive Director, Center for Nanoscale Metrology Dr. Alain Diebold.

“I look forward to advancing this non-volatile memory research at SUNY Poly, using the institution’s cutting-edge fabrication facilities in order to address current computing bottlenecks that slow computing capability and waste energy,” said Dr. Cady. “This grant will drive the development of computing and memory infrastructure that will be evaluated using high-performance simulations and experimental benchmarking within our state-of-the-art laboratory at SUNY Poly where we are eager to develop the architecture that can help revolutionize processing and memory capabilities for next-gen computers.”

Dr. Cady’s research will support SUNY Poly graduate students who will be able to obtain hands-on experience developing the computing/memory structures. The materials for this project will be developed, demonstrated, and then integrated with traditional complementary metal-oxide-semiconductor (CMOS) computer chips as part of a larger production, which will utilize SUNY Poly’s 200mm and 300mm state-of-the-art fabrication facilities. The University of Central Florida is receiving its own funds for collaborative research related to this effort.

Computing using multiple parallel flows of current through data stored in nanoscale “crossbars” is often fast and more energy-efficient, but the design of such crossbars is highly unintuitive for human designers. More specifically, this project explores formal methods for more efficiently conducting Boolean searches and using artificial intelligence techniques such as best-first search, in addition to automatically synthesizing non-volatile memory crossbar designs from specifications written in a high-level programming language.

Sandwiching two-dimensional materials used in nanoelectronic devices between their three-dimensional silicon bases and an ultrathin layer of aluminum oxide can significantly reduce the risk of component failure due to overheating, according to a new study published in the journal of Advanced Materials led by researchers at the University of Illinois at Chicago College of Engineering.

An experimental transistor using silicon oxide for the base, carbide for the 2D material and aluminum oxide for the encapsulating material. Credit: (Image: Zahra Hemmat).

Many of today’s silicon-based electronic components contain 2D materials such as graphene. Incorporating 2D materials like graphene — which is composed of a single-atom-thick layer of carbon atoms — into these components allows them to be several orders of magnitude smaller than if they were made with conventional, 3D materials. In addition, 2D materials also enable other unique functionalities. But nanoelectronic components with 2D materials have an Achilles’ heel — they are prone to overheating. This is because of poor heat conductance from 2D materials to the silicon base.

“In the field of nanoelectronics, the poor heat dissipation of 2D materials has been a bottleneck to fully realizing their potential in enabling the manufacture of ever-smaller electronics while maintaining functionality,” said Amin Salehi-Khojin, associate professor of mechanical and industrial engineering in UIC’s College of Engineering.

One of the reasons 2D materials can’t efficiently transfer heat to silicon is that the interactions between the 2D materials and silicon in components like transistors are rather weak.

“Bonds between the 2D materials and the silicon substrate are not very strong, so when heat builds up in the 2D material, it creates hot spots causing overheat and device failure,” explained Zahra Hemmat, a graduate student in the UIC College of Engineering and co-first author of the paper.

In order to enhance the connection between the 2D material and the silicon base to improve heat conductance away from the 2D material into the silicon, engineers have experimented with adding an additional ultra-thin layer of material on top of the 2D layer — in effect creating a “nano-sandwich” with the silicon base and ultrathin material as the “bread.”

“By adding another ‘encapsulating’ layer on top of the 2D material, we have been able to double the energy transfer between the 2D material and the silicon base,” Salehi-Khojin said.

Salehi-Khojin and his colleagues created an experimental transistor using silicon oxide for the base, carbide for the 2D material and aluminum oxide for the encapsulating material. At room temperature, the researchers saw that the conductance of heat from the carbide to the silicon base was twice as high with the addition of the aluminum oxide layer versus without it.

“While our transistor is an experimental model, it proves that by adding an additional, encapsulating layer to these 2D nanoelectronics, we can significantly increase heat transfer to the silicon base, which will go a long way towards preserving functionality of these components by reducing the likelihood that they burn out,” said Salehi-Khojin. “Our next steps will include testing out different encapsulating layers to see if we can further improve heat transfer.”

Japan is at the heart of the semiconductor industry as the era of artificial intelligence (AI) dawns. SEMICON Japan 2018 will highlight AI and SMART technologies in Japan’s industry-leading event. Registration is now open for SEMICON Japan, Japan’s largest global electronics supply chain event, December 12-14 at Tokyo Big Sight in Tokyo.

Themed “Dreams Start Here,” SEMICON Japan 2018 reflects the promise of AI, Internet of Things (IoT) and other SMART technologies that are shaping the future. Japan is positioned to help power a semiconductor industry expansion that is enabling this new path ahead, supplying one-third of the world’s semiconductor equipment and half of its chip IC materials.

According to VLSI Research, seven of the world’s top 15 semiconductor equipment manufacturers in 2017 are headquartered in Japan. In the semiconductor materials market, Japanese companies dominate silicon wafers, photoresists, sputtering targets, bonding wires, lead frames, mold compounds and more. For SEMICON Japan visitors, the event is the ideal platform for connecting with Japan’s leading suppliers.

The SMART Application Zone at SEMICON Japan will once again connect SMART industries with the semiconductor supply chain to foster collaboration across the electronics ecosystem.

SEMICON Japan Keynotes

SEMICON Japan opening keynotes will feature two young leaders of Japan’s information and communications technology (ICT) industry sharing their vision for the industry:

Motoi Ishibashi, CTO of Rhizomatiks, will discuss the latest virtual and mixed reality technologies. Rhizomatiks, a Japanese media art company that staged the Rio Olympic Games closing ceremony, will orchestrate the opening performance at SEMICON Japan 2018. The company is dedicated to creating large-scale commercial projects combining technology with the arts.

Toru Nishikawa, president and CEO at Preferred Networks, will explore computer requirements for enabling deep learning applications. Preferred Networks, a deep-learning research startup, is conducting collaborative research with technology giants including Toyota Motors, Fanuc, NVIDIA, Intel and Microsoft.

Registration

For more information and to register for SEMICON Japan, visit www.semiconjapan.org/en/. Registration for the opening keynotes and other programs will open October 1.

This premier international conference, sponsored by the IEEE Electronics Packaging Society (IEEE EPS), covers a wide spectrum of electronic packaging technology topics, including components, materials, assembly, interconnect design, device and system packaging, wafer level packaging, Si photonics, LED and IoT, optoelectronics, 2.5D and 3D integration technology, and reliability.

The ECTC Program Committee, with more than 200 experts from broad-ranging technical areas, is committed to creating an engaging technical program for all. ECTC typically attracts more than 1,400 attendees from over 25 countries. Last year’s 68th ECTC in San Diego, California, had 1,738 attendees, with 331 papers and interactive presentations featured in 41 sessions.

The 69th ECTC program will include six parallel technical sessions in the mornings and afternoons over three days, along with other special topic panel discussions to present high-level trends and best practices in the industry. Professional Development Courses (PDCs) will also be offered by world-class experts, enabling participants to broaden their technical knowledge base.

The technical program and PDCs will be supplemented by Technology Corner Exhibits, which provide an opportunity for leading companies in the electronic components, materials, and packaging fields to exhibit their latest technologies and products. Last year’s 68th ECTC matched our record number of 106 exhibitors.

Please submit an abstract between 250 and 750 words that describes the scope, content, and key points of your proposed technical paper at www.ectc.net. You are also welcome to submit proposals for PDCs. All abstracts and manuscripts must be original, free of commercial content, and non-confidential.

Deadlines to Remember:

  • 0.08.2018| Abstracts and PDC Proposals Due

12.10-2018| Authors Notified of Acceptance

01.02.2019| Advance Online Registration Opens

  • 02.23.2018| Manuscripts due for inclusion in the Conference Proceedings.

Air Products (NYSE : APD ) today announced it has been awarded by Samsung Electronics additional gaseous nitrogen and hydrogen supply to its semiconductor fab in Giheung, South Korea.

Air Products, who has been supplying industrial gases to Samsung Electronics’ Giheung site since 1998, will invest in building a new air separation unit, multiple hydrogen plants, and pipelines, which are scheduled to be operational in 2020 to supply the customer’s increased demand.

“We are proud to expand our longstanding relationship with Samsung Electronics and have their continued confidence in our ability to support their technological development and growth plans,” said Kyo-Yung Kim, president of Air Products Korea. “Our latest investment once again reinforces Air Products’ commitment to serving our strategic customer, as well as the broader semiconductor and electronics industries, with our safety, reliability, efficiency and excellent service.”

Air Products supplies many of Samsung’s operations worldwide, including its semiconductor cluster in the north region of South Korea spanning Giheung, Hwaseong and Pyeongtaek. In Pyeongtaek, the company has been undertaking a multi-phase expansion project to support Samsung Electronics’ multibillion dollar fab.

A leading integrated gases supplier, Air Products has been serving the global electronics industry for more than 40 years, supplying industrial gases safely and reliably to most of the world’s largest technology companies. Air Products is working with these industry leaders to develop the next generation of semiconductors and displays for tablets, computers and mobile devices.

Schottky diode is composed of a metal in contact with a semiconductor. Despite its simple construction, Schottky diode is a tremendously useful component and is omnipresent in modern electronics. Schottky diode fabricated using two-dimensional (2D) materials have attracted major research spotlight in recent years due to their great promises in practical applications such as transistors, rectifiers, radio frequency generators, logic gates, solar cells, chemical sensors, photodetectors, flexible electronics and so on.

The understanding of 2D material-based Schottky diode is, however, plagued by multiple mysteries. Several theoretical models have co-existed in the literatures and a model is often selected a priori without rigorous justifications. It is not uncommon to see a model, whose underlying physics fundamentally contradicts with the physical properties of 2D materials, being deployed to analyse a 2D material Schottky diode.

Reporting in Physical Review Letters, researchers from the Singapore University of Technology and Design (SUTD) have made a major step forward in resolving the mysteries surrounding 2D material Schottky diode. By employing a rigorous theoretical analysis, they developed a new theory to describe different variants of 2D-material-based Schottky diodes under a unifying framework. The new theory lays down a foundation that helps to unite prior contrasting models, thus resolving a major confusion in 2D material electronics.

Schematic drawing of a 2D-material-based lateral (left) and vertical (right) Schottky diode. For broad classes of 2D materials, the current-temperature relation can be universally described by a scaling exponent of 3/2 and 1, respectively, for lateral and vertical Schottky diodes. Credit: Singapore University of Technology and Design

“A particularly remarkable finding is that the electrical current flowing across a 2D material Schottky diode follows a one-size-fits-all universal scaling law for many types of 2D materials,” said first-author Dr. Yee Sin Ang from SUTD.

Universal scaling law is highly valuable in physics since it provides a practical “Swiss knife” for uncovering the inner workings of a physical system. Universal scaling law has appeared in many branches of physics, such as semiconductor, superconductor, fluid dynamics, mechanical fractures, and even in complex systems such as animal life span, election results, transportation and city growth.

The universal scaling law discovered by SUTD researchers dictates how electrical current varies with temperature and is widely applicable to broad classes of 2D systems including semiconductor quantum well, graphene, silicene, germanene, stanene, transition metal dichalcogenides and the thin-films of topological solids.

“The simple mathematical form of the scaling law is particularly useful for applied scientists and engineers in developing novel 2D material electronics,” said co-author Prof. Hui Ying Yang from SUTD.

The scaling laws discovered by SUTD researchers provide a simple tool for the extraction of Schottky barrier height – a physical quantity critically important for performance optimisation of 2D material electronics.

“The new theory has far reaching impact in solid state physics,” said co-author and principal investigator of this research, Prof. Lay Kee Ang from SUTD, “It signals the breakdown of classic diode equation widely used for traditional materials over the past 60 years, and shall improve our understanding on how to design better 2D material electronics.”

Worldwide semiconductor manufacturing equipment billings reached US$16.7 billion in the second quarter of 2018, 1 percent lower than the previous record quarter and 19 percent higher than the same quarter a year ago, SEMI, the global industry association representing the electronics manufacturing supply chain, reported today.

The data are gathered jointly with the Semiconductor Equipment Association of Japan (SEAJ) from more than 95 global equipment companies that provide monthly data. The quarterly billings data by region in billions of U.S. dollars, quarter-over-quarter growth and year-over-year rates by region are as follows:
2Q2018
1Q2018
2Q2017
2Q18/1Q18
(Qtr-over-Qtr)
2Q18/2Q17
(Year-over-Year)
Korea
4.86
6.26
4.79
-22%
2%
China
3.79
2.64
2.51
44%
51%
Japan
2.28
2.13
1.55
7%
47%
Taiwan
2.19
2.27
2.76
-4%
-21%
North America
1.47
1.14
1.23
29%
20%
Europe
1.18
1.28
0.66
-7%
80%
Rest of World
0.96
1.27
0.62
-24%
56%
Total
16.74
16.99
14.11
-1%
19%

Source: SEMI (www.semi.org) and SEAJ, September 2018

The Equipment Market Data Subscription (EMDS) from SEMI provides comprehensive market data for the global semiconductor equipment market.