Category Archives: Semiconductors

IC Insights released its August Update to the 2018 McClean Report earlier this month.  This Update included a discussion of the top-25 semiconductor suppliers in 1H18 (the top-15 1H18 semiconductor suppliers are covered in this research bulletin) and Part 1 of an extensive analysis of the IC foundry market and its suppliers.

The top-15 worldwide semiconductor (IC and O-S-D—optoelectronic, sensor, and discrete) sales ranking for 1H18 is shown in Figure 1.  It includes seven suppliers headquartered in the U.S., three in Europe, two each in South Korea and Taiwan, and one in Japan.  After announcing in early April 2018 that it had successfully moved its headquarters location from Singapore to the U.S. IC Insights now classifies Broadcom as a U.S. company.

Figure 1

As shown, all but four of the top 15 companies had double-digit year-over-year growth in 1H18. Moreover, seven companies had ≥20% growth, including the five big memory suppliers (Samsung, SK Hynix, Micron, Toshiba/Toshiba Memory, and Western Digital/SanDisk) as well as Nvidia and ST.

The top-15 ranking includes one pure-play foundry (TSMC) and four fabless companies. If TSMC were excluded from the top-15 ranking, U.S.-based Apple would have been ranked in the 15th position. Apple is an anomaly in the top company ranking with regards to major semiconductor suppliers. The company designs and uses its processors only in its own products—there are no sales of the company’s MPUs to other system makers. IC Insights estimates that Apple’s custom ARM-based SoC processors and other custom devices had a “sales value” of $3.5 billion in 1H18.

IC Insights includes foundries in the top-15 semiconductor supplier ranking since it has always viewed the ranking as a top supplier list, not a marketshare ranking, and realizes that in some cases the semiconductor sales are double counted. With many of our clients being vendors to the semiconductor industry (supplying equipment, chemicals, gases, etc.), excluding large IC manufacturers like the foundries would leave significant “holes” in the list of top semiconductor suppliers. Foundries and fabless companies are identified in the Figure. In the April Update to The McClean Report, marketshare rankings of IC suppliers by product type were presented and foundries were excluded from these listings.

Overall, the top-15 list shown in Figure 1 is provided as a guideline to identify which companies are the leading semiconductor suppliers, whether they are IDMs, fabless companies, or foundries.

In May 2018, Toshiba completed the $18.0 billion sale of its memory IC business to the Bain Capital-led consortium. Toshiba then repurchased a 40.2% share of the business. The Bain consortium goes by the name of BCPE Pangea and the group owns 49.9% of Toshiba Memory Corporation (TMC). Hoya Corp. owns the remaining 9.9% of TMC’s shares. The new owners have plans for an IPO within three years. Bain has said it plans to support the business in pursing M&A targets, including potentially large deals.

As a result of the sale of Toshiba’s memory business, the 2Q18 sales results shown in Figure 1 include the combined sales of the remaining semiconductor products at Toshiba (e.g., Discrete devices and System LSIs) and the new Toshiba Memory’s NAND flash sales. The estimated breakdown of these sales in 2Q18 is shown below:

Toshiba System LSI: $468M
Toshiba Discrete: $315M
Toshiba Memory Corporation: $3,107M
Total Toshiba/Toshiba Memory Corporation 2Q18 Sales: $3,890M

In total, the top-15 semiconductor companies’ sales surged by 24% in 1H18 compared to 1H17, four points higher than the total worldwide semiconductor industry 1H18/1H17 increase of 20%. Amazingly, the Big 3 memory suppliers—Samsung, SK Hynix, and Micron, each registered greater than 35% year-over-year growth in 1H18. Fourteen of the top-15 companies had sales of at least $4.0 billion in 1H18, three companies more than in 1H17. As shown, it took just over $3.7 billion in sales just to make it into the 1H18 top-15 semiconductor supplier list.

Intel was the number one ranked semiconductor supplier in 1Q17 but lost its lead spot to Samsung in 2Q17 as well as in the full-year 2017 ranking, a position it had held since 1993. With the continuation of the strong surge in the DRAM and NAND flash markets over the past year, Samsung went from having only 1% more total semiconductor sales than Intel in 1H17 to having 22% more semiconductor sales than Intel in 1H18!

It is interesting to note that memory devices are forecast to represent 84% of Samsung’s semiconductor sales in 2018, up three points from 81% in 2017 and up 13 points from 71% just two years earlier in 2016. Moreover, the company’s non-memory sales in 2018 are expected to be only $13.5 billion, up 8% from 2017’s non-memory sales level of $12.5 billion. In contrast, Samsung’s memory sales are forecast to be up 31% this year and reach $70.0 billion.

The 64thannual IEEE International Electron Devices Meeting (IEDM), the world’s largest, most influential forum for technologists to unveil breakthroughs and new concepts in transistors and related micro/nanoelectronics devices, will be held December 1-5, 2018 at the Hilton San Francisco Union Square hotel. The late-news submission deadline is September 10.

The IEDM’s tradition of spotlighting more leading work in more areas of the field continues, even as the conference evolves to support the interdisciplinary and continuing educational needs of the scientists, engineers and students whose efforts make possible the expansion of the worldwide electronics industry.

“We live in a time when electronics technology touches more aspects of business and industry than ever before,” said Kirsten Moselund, IEDM 2018 Publicity Chair and Research Staff Member at IBM Research–Zurich. “No matter what their specialty is, attendees will come away from the conference with a deeper understanding of the challenges and opportunities before them.”

“In terms of industrial applications, the evening panel session on EUV will give attendees the opportunity to explore and debate this emerging technology with the very people who are driving it forward,” said Rihito Kuroda, IEDM 2018 Publicity Vice Chair and Associate Professor at Tohoku University. “This is just one way in which the IEDM conference gives people insights into the technologies that will become mainstream in a few years.”

Here are details of some of the talks and events that will take place at this year’s IEDM. The papers to be presented in the technical sessions will be chosen in late September and highlights from them will be forthcoming soon thereafter:

Focus Sessions

  • Quantum Computing – Quantum computing will enable new types of algorithms to tackle problems in areas from materials science to medicine to artificial intelligence. We are still in early stages, facing fundamental questions such as: What is the best way to implement a quantum bit of information? How to connect them together? How to scale to larger systems without being overwhelmed by errors? This session brings together experts at the forefront of quantum computing research. Starting from an applications perspective, attendees will hear about different approaches to address fundamental questions at the device level; the progress achieved so far; and next steps.
    • Application Requirements for Quantum Computing, John Preskill, Caltech
    • Materials and Device Challenges for Near-Term Superconducting Quantum Processors, Jerry Chow, IBM
    • Towards Scalable Silicon Quantum Computing, Maud Vinet, CEA-Leti
    • Silicon Isotope Technology for Quantum Computing, Kohei Itoh, Keio University
    • Qubit Device Integration Using Advanced Semiconductor Manufacturing Process Technology, Ravi Pillarrisetty, Intel
    • Scalable Quantum Computing with Single Dopant Atoms in Silicon, Andrea Morello, Univ. New South Wales
    • Majorana Qubits, Leo Kouwenhoeven, Microsoft
  • Future Technologies Towards Wireless Communications: 5G and Beyond– 5G technology will drastically reduce limitations on accessibility, bandwidth, performance, and latency, but as it triggers fundamentally new applications it also will impose unique hardware requirements. This focus session will set a big picture view and then narrow down to how innovations in CMOS technologies, devices, filters, transceivers and antennas are coming together to enable the 5G platform.
    • Intel 22nm FinFET (22FFL) Process Technology for RF and mmWave Applications and Circuit Design Optimization for FinFET Technology, Hyung-Jin Lee, Intel
    • RFIC/CMOS Technologies for 5G, mmWave and Beyond, Ali Niknejad, UC Berkeley
    • GaN HEMTs for 5G Base Station Applications, Shigeru Nakajima, Sumitomo Electron Devices
    • Highly Integrated mm-Wave Transceivers for Communication Systems,Vadim Issakov, Infineon
    • BAW Filters for 5G Bands, Robert Aigner, Qorvo
    • Reconfigurable Micro/Millimeter-wave Filters, Dimitrios Peroulis, Purdue
  • Challenges for Wide Bandgap Device Adoption in Power Electronics– Wide bandgap (WBG) power devices offer potential savings in both energy and cost. But converters powered by WBG devices require innovation at all levels, entailing changes to system design, circuit architecture, qualification metrics and even market models. Can SiC or GaN push beyond what silicon can possibly achieve? What are the big challenges researchers should answer over the next decade? A team of experts will interpret the landscape and discuss challenges to the widespread adoption of these technologies.
    • GaN and SiC Devices for Automotive Applications, Tetsu Kachi, Nagoya University
    • SiC MOSFET for Mainstream Adoption, Peter Friedrichs, Infineon
    • GaN Power Commercialization with Highest Quality-Highest Reliability 650V HEMTs- Requirements, Successes and Challenges, Primit Parikh, Transphorm
    • The Current Status and Future Prospects of SiC High Voltage Technology, Andrei Mihaila, ABB
    • Barriers to Wide Bandgap Semiconductor Device Adoption in Power Electronics, Isik Kizilyalli, ARPA-E
    • High to Ultra-High Voltage SiC Power Device Technology, Yoshiyuki Yonezawa, AIST
    • Effects of Basal Plane Dislocations on SiC Power Device Reliability, Robert E. Stahlbush, Naval Research Laboratory
  • Interconnects to Enable Continued Technology Scaling –BEOL copper (Cu) interconnects are close to end-of-life as a manufacturing technology, while the increasing complexity of MEOL processes requires novel materials. Also, the end of the Cu roadmap will coincide with significant changes in the dominant transistor architecture, and therefore the interaction between transistor architecture and interconnect will drive future interconnect development. This session provides a holistic perspective of interconnect scaling challenges and solutions. It will address the drivers of future interconnect architectures, the process options likely to be implemented in manufacturing, and how they will be tuned to ensure circuit reliability is maintained.
    • Interconnect Design and Technology Optimization for Conventional and Exotic Nanoscale Devices: A Physical Design Perspective, Naeemi, Georgia Tech
    • Mechanisms of Electromigration Damage in Cu Interconnects, K. Hu, IBM
    • Interconnect Metals Beyond Copper: Reliability Challenges and Opportunities, K. Croes, Imec
    • Microstructure Evolution and Effect on Resistivity for Cu Nano-interconnects and Beyond, Paul Ho, UT Austin
    • Integrating Graphene into Future Generations of BEOL Interconnects,-S. Philip Wong, Stanford
    • Interconnect Trends for Single Digit Nodes, Mehul Naik, Applied Materials

90-Minute Tutorials – Saturday, Dec. 1

A series of 90-minute tutorial sessions on emerging technologies will be presented by experts in the fields, bridging the gap between textbook-level knowledge and leading-edge current research.

  • Reliability Challenges in Advanced Technologies,Ryan Lu, TSMC
  • STT-MRAM Design and Device Requirements, Shinichiro Shiratake, Toshiba Memory
  • Quantum Computing Primer, Mark B. Ritter, IBM
  • Power Transistors in Integrated BCD Technologies, Hal Edwards, Texas Instruments
  • Design-Technology Co-optimization at RF and mmWave, Bertand Parvais, IMEC
  • Emerging Device Technologies for Neuromorphic Computing, Damien Querlioz, CNRS

Short Courses – Sunday, Dec. 2

Full-day Short Courses will be held, offering the opportunity to learn about important areas and developments, and to network with experts from around the world.

  • It’s All About Memory, Not Logic!, organized by Nirmal Ramaswamy, Micron
  • DRAM: Its Challenging History and Future, Dong Soo Woo, Samsung
  • 3D Flash Memories: Overview of Cell Structures, Operations and Scaling Challenges, Makoto Fujiwara, Toshiba Memory Corporation.
  • Emerging Memories Including Cross-Point, Opportunities and Challenges, Kiran Pangal, Intel
  • Memory Reliability, Qualification and their Relation to System-Level Reliability Strategies, Todd Marquart, Micron
  • Packaging Technology for High Bandwidth Memory, Nick (Namseog) Kim, SK Hynix
  • Processing in Memory (PIM): Performance and Thermal Challenges and Opportunities, Mircea Stan, UVA
  • Scaling Survival Guide in the More-than-Moore Era, organized by Jin Cai, TSMC
  • Extreme-UV Lithography – Principles, Present Status and Outlook,Tony Yen, ASML
  • MOSFET Scaling Knobs (GAA, NCFET…) and Future Alternatives,Witek Maszara, Globalfoundries
  • Overcoming Variation Challenges, Sivakumar Mudanai, Intel
  • Embedded Memory: Present Status and Emerging Architecture and Technology for Future Applications,Eric Wang, TSMC
  • 3D Integration for Density and Functionality,Julien Ryckaert, Imec
  • Advanced Packaging: the Next Frontier for Moore’s “Law,” Subramanian Iyer, UCLA

Plenary Presentations – Monday, Dec. 3

  • Future Computing Hardware for AI, Jeffery Welser, Vice President, IBM Research-Almaden
  • “4th Industrial Revolution and Foundry: Challenges and Opportunities,” Eun Seung Jung, President of Foundry Business, Samsung Electronics
  • The Status, Challenges and Opportunities of 5G, Prof. Gerhard P. Fettweis, TU Dresden

Evening Panel Session – Tuesday evening, Dec. 4

  • EUV: Too Little, Too Late, Too Expensive or the Ultimate Cure-All?,organized by Sanjay Natarajan, Senior VP of Applied Materials. Much progress has been made in EUV patterning technology, and yet manufacturing throughput, masks, pellicles and resists still persist as problems today. The complexity of reliably transferring features at the 7nm node and below using quadruple patterning and 193nm immersion is affecting yield, affecting the cost-per-gate reduction and slowing down Moore’s Law. The industry eagerly awaits EUV, but is it too little, too late and too expensive, or is it the ultimate panacea? A team of world-renowned experts from the leading logic and memory IDMs, foundries and fabless companies will vigorously debate the issue.

Luncheon – Wednesday, Dec. 5

The speakers are yet to be determined, but IEDM will have a new lunch event this year that features industry leaders engaging the audience on the state of the industry, and on careers in device and VLSI technology.

Vendor Exhibition/Poster Sessions

  • A vendor exhibition will be held once again, with special exhibit events in the evenings.
  • This year two poster sessions will be held, one on MRAM technology organized by the IEEE Magnetics Society, the other a student research showcase hosted by the Semiconductor Research Corporation.

Further information about IEDM

For registration and other information, visit www.ieee-iedm.org.

Follow IEDM via social media

About IEEE
IEEE is the world’s largest technical professional organization dedicated to advancing technology for the benefit of humanity. Through its highly cited publications, conferences, technology standards, and professional and educational activities, IEEE is the trusted voice in a wide variety of areas ranging from aerospace systems, computers, and telecommunications to biomedical engineering, electric power, and consumer electronics. Learn more at http://www.ieee.org.

Nordson SONOSCAN, a developer and producer of acoustic micro imaging (AMI) tools, announces its new Gen7™ laboratory style acoustic micro-imaging tool. The new Gen7 AMI tool enhances operator productivity and part throughput rate by providing greater versatility in transducer movement, faster scanning of samples, and faster processing of data.

Orders are now being taken for the Gen7 AMI tool, which, like its predecessors in the Nordson SONOSCANC-SAM® line, is designed for analytical work on small numbers of samples, although it can also screen modest quantities of components. Among its differentiating features:

  • 50% higher screening throughput from faster transducer motors.
  • Scan area significantly enlarged, so more parts can be scanned at one time.
  • Upward and downward range of Z movement of the transducer more than doubled to enable scanning of samples having a greater range of height variation.
  • Windows® 10 operating system and Sonolytics 2™ user interface have replaced Windows® 7 and Sonolytics™, respectively.
  • Intel’s i7 seventh generation chips make the system’s computer hardware 33% faster, giving, for example, quicker delivery of Digital Image Analysis.
  • Both monitors have high resolution 4K screens to reveal more detail.
  • Includes Waterplume™ technology, so a separate C-SAM tool is not needed to image IGBT modules.

Users will notice that frequently used menu items now appear in the User Interface, eliminating the need to open a menu. Other changes include easy access to the current timing mode in the A-Scan and the ability to Go To a TOF directly from the movement interface.

RF power semiconductors for wireless infrastructure (for <4GHz and >3W) was over a US$1 billion business for 2018. The segment was essentially revenue flat, but Gallium Nitride (GaN) continues to make inroads into this segment.

“Gallium Nitride should continue to gain share over the next few years,” noted ABI Research Director Lance Wilson. “It bridges the gap between two older technologies, exhibiting the high-frequency performance of Gallium Arsenide combined with the power handling capabilities of Silicon LDMOS. It is now a mainstream technology which has achieved measurable market share and, in the future, will capture a significant part of the market.”

The wireless infrastructure sub-segment while representing about two-thirds of total RF power device sales has been anemic recently but is still holding its own.

The eventual deployment of 5G also offers an upside for the wireless Infrastructure segment. The main issue is one of timing on a large-scale rollout. Wilson also added, “the business environment for the RF power semiconductor device business has become more complex with potential trade tariffs, merger and acquisition troubles and other similar issues clouding the market”.

These findings are from ABI Research’s RF Power Semiconductor Devices for Mobile Wireless Infrastructure report. These reports are part of the company’s 5G & Mobile Network Infrastructureresearch service, which includes research, data, and Executive Foresights.

Adesto Technologies (NASDAQ:IOTS), a provider of application-specific semiconductors for the IoT era, announced it will present new research showing the significant potential for Resistive RAM (RRAM) technology in high-reliability applications such as automotive. Adesto Fellow Dr. John Jameson, who led the research team, will share the results at the ESSCIRC-ESSDERC 48th European Solid-State Device Research Conference, being held in Germany on September 4th, 2018.

RRAM has great potential to become a widely used, low-cost and simple embedded non-volatile memory (NVM), as it utilizes simple cell structures and materials which can be integrated into existing manufacturing flows with as little as one additional mask. However, many RRAM technologies to-date have faced integration and reliability challenges. Adesto’s engineers will describe recent innovations that significantly increase the reliability of Adesto’s RRAM technology (trademarked as CBRAM®), making it a promising candidate for high-reliability applications. CBRAM consumes less power, requires fewer processing steps, and operates at lower voltages as compared to conventional embedded flash technologies.

“We’re delighted to share our latest RRAM research with the prestigious technical community at ESSCIRC-ESSDERC,” said Dr. Venkatesh Gopinath, VP of CBRAM and RRAM Technology and Production Development at Adesto. “For the first time, RRAM is being demonstrated as an ideal low-cost, one-mask embedded NVM for high-reliability applications. Adesto was the first company to bring commercial RRAM devices to market, and now our CBRAM technology is production-proven for IoT and other ultra-low power applications. Our continued innovation and advancements will bring the benefits of CBRAM to an even broader range of applications.”

Dr. Jameson will present the Adesto research on Tuesday, September 4th at 15:00 local time.

On the heels of a 37.3% growth in wafer front end (WFE) semiconductor equipment growth in 2017, the market will grow only 10% in 2018 to $62.3 billion, according to the report “The Global Semiconductor Equipment: Markets, Market Shares, Market Forecasts,” recently published by The Information Network, (www.theinformationnet.com) a New Tripoli, PA-based market research company.

For the first six months of 2018, WFE billings were $35.3 billion, meaning billings of $27.0 billion will be registered in the second half of 2018 if the sector as a whole grows 10% in CY 2018.

This means a drop of 24% between 1H 2018 and 2H 2018.

The chart below shows that U.S. equipment companies held a 48.8% share of the total sector in 1H 2018 followed by Japan with a 30.3% share and ROW (primarily Europe) with a 26.9% share. For 2H 2018, the weak Japanese Yen means Japan will have a 29.1% share, but stronger EUV sales by ASML will mean Europe’s share will grow to 28.0%.

The memory market is moving into a period of oversupply: NAND oversupply started six months ago and has resulted in device price drops, while DRAMs will reach an oversupply situation in the next few months. As a result, market leader Samsung Electronics has pushed out purchases. Foundry leader TSMC has reduced its estimate for sales revenue growth in 2018 and its capital expenditure budget.

Synopsys, Inc. (Nasdaq: SNPS) today announced a collaboration with IBM to apply design technology co-optimization (DTCO) to the pathfinding of new semiconductor process technologies for the 3-nanometer (nm) process node and beyond. DTCO is a methodology for efficiently evaluating and down-selecting new transistor architectures, materials and other process technology innovations using design metrics, starting with an early pathfinding phase before wafers become available. The collaboration will extend the current Synopsys DTCO tool flow to new transistor architectures and other technology options while enabling IBM to develop early process design kits (PDKs) for its partners to assess the power, performance, area, and cost (PPAC) benefits at IBM’s advanced nodes.

“Process technology development beyond 7 nanometers requires the exploration of new materials and transistor architectures to achieve optimum manufacturability, power, performance, area, and cost. A major challenge for foundries is to converge on the best architecture in a timely manner while vetting all the possible options,” said Dr. Mukesh Khare, vice president of Semiconductor Research, IBM Research Lab. “Our DTCO collaboration with Synopsys allows us to efficiently select the best transistor architecture and process options based on metrics derived from typical building blocks, such as CPU cores, thus contributing to faster process development at reduced cost.”

In this collaboration, IBM and Synopsys are developing and validating new patterning techniques with Proteus™ mask synthesis, modeling new materials with QuantumATK, optimizing new transistor architectures with Sentaurus™ TCAD and Process Explorer, and extracting compact models with Mystic. Design rules and process assumptions derived from these process innovations are used to design and characterize a standard cell library while Fusion Technology™ at the block level using the Synopsys physical implementation flow based on IC Compiler™ II place-and-route, StarRC™ extraction, SiliconSmart® characterization, PrimeTime® signoff, and IC Validator physical verification benefits the evaluation of PPAC.

The scope of the joint development agreement covers multiple facets, including:

  • DTCO to optimize transistor- and cell-level design across routability, power, timing, and area
  • Evaluate and optimize new transistor architectures, including gate-all-around nanowire and nanoslab devices, with process and device simulation
  • Optimize variation-aware models for SPICE simulation, parasitic extraction (PEX), library characterization, and static timing analysis (STA) to accurately encapsulate the effects of variation on timing and power for highest-reliability design with least over-design and design flow runtime overhead
  • Gather gate-level design metrics to refine the models, library architecture, and design flows to maximize PPAC benefits

“Synopsys has developed the only complete DTCO solution, from materials exploration to block-level physical implementation,” said Dr. Antun Domic, chief technology officer at Synopsys. “IBM’s extensive process development and design know-how makes them an ideal partner for extending our DTCO solution to 3 nanometers and beyond.”

Automotive electronics are a bright light for the semiconductor industry, as smartphone growth slows, and personal computing growth continues to decline. The expectation is that automotive electronics will become the next big technology market driver. The automotive semiconductor market will exceed the overall industry growth as semiconductor content expands with added features and functionality. The desire to put self-driving vehicles on the road is creating increased interest in innovative automotive solutions as well as increased semiconductor demand. A new research report from Semico Research, Automotive Semiconductors: Accelerating in the Fast Lane, states that the automotive segment of the semiconductor industry will grow to $73 billion by 2023.

“There are a number of challenges in the automotive industry that are unique for the system developers to navigate. Autonomous driving is a critical one,” says Jim Feldhan, President of Semico Research. “Many people feel AI is the key to the success of autonomous driving. Autonomous driving includes the ability to have optical character recognition, i.e. reading signs, distinguishing a sign from a person, and determining if the brakes should be turned on. Security surveillance, computer vision, virtual reality and image processing, real-time diagnosis and corrective solutions and strategic map planning are critical to autonomous driving. Increasing levels of processing are required as these systems become more sophisticated.”

Key findings in the report include:

The TAM market for automotive IP processor royalties will grow to $2.34 billion by 2023.
A fully autonomous vehicle (L5) is expected to require 74GB DRAM and 1TB NAND memory.
Powertrain requires the highest compute function and carries the highest ASP.

Revenue generated from processors in Autonomous Driving Systems will reach $422 million in 2018.
In its recent report, Automotive Semiconductors: Accelerating in the Fast Lane (MP118-18), Semico Research provides a comprehensive review of the current market and future opportunities for the semiconductor industry in the automotive segment. Topics covered in the report include Automotive Trends, Opportunities and Challenges, Manufacturing Technology for Auto ICs, Automotive Forecast, and Semiconductor IP in Automotive. The report is 56 pages long and includes 28 tables and 34 figures.

Cabot Microelectronics Corporation (Nasdaq: CCMP), a supplier of chemical mechanical planarization (CMP) polishing slurries and second largest CMP pads supplier to the semiconductor industry, and KMG Chemicals, Inc. (NYSE: KMG), a global provider of specialty chemicals and performance materials, have entered into a definitive agreement under which Cabot Microelectronics will acquire KMG in a cash and stock transaction with a total enterprise value of approximately $1.6 billion. Under the terms of the agreement, KMG shareholders will be entitled to receive, per KMG share, $55.65 in cash and 0.2000 of a share of Cabot Microelectronics common stock, which represents an implied per share value of $79.50 based on the volume weighted average closing price of Cabot Microelectronics common stock over the 20-day trading period ended on August 13, 2018.  The transaction has been unanimously approved by the Boards of Directors of both companies and is expected to close near the end of calendar year 2018.

The combined company is expected to have annual revenues of approximately $1 billion and approximately $320 million in EBITDA, including synergies, extending and strengthening Cabot Microelectronics’ position as one of the leading suppliers of consumable materials to the semiconductor industry.  Additionally, the combined company will be a leading global provider of performance products and services for improving pipeline operations and optimizing throughput.

“We are excited about the combination of two world-class organizations with dedicated and talented employees that provide innovative, high quality solutions to solve our customers’ most demanding challenges,” said David Li, President and CEO of Cabot Microelectronics. “KMG’s industry-leading electronic materials business is highly complementary to our CMP product portfolio, while its performance materials business broadens our product offerings into the fast-growing industry for pipeline performance products and services.  We welcome KMG’s employees to our team and look forward to our future together as one company.”

Chris Fraser, KMG Chairman and CEO, said, “This is an outstanding combination, bringing together two leading companies that will benefit from increased size, scale and geographic reach. For KMG shareholders, this transaction creates significant and immediate value while also providing participation in the future growth of the combined company.  Thanks to the dedication and hard work of KMG employees around the world, KMG has achieved significant progress over the past several years, and I am confident that Cabot Microelectronics will continue to build on this success to further enhance value for our shareholders.”

pSemi Corporation (formerly Peregrine Semiconductor), a Murata company focused on semiconductor integration, introduces the world’s first monolithic, silicon-on-insulator (SOI) Wi-Fi front-end module (FEM)—the PE561221. Ideal for Wi-Fi home gateways, routers and set-top boxes, this high-performance module uses a smart bias circuit to deliver a high linearity signal and excellent long-packet error vector magnitude (EVM) performance. The PE561221 combines the intelligent integration capabilities of pSemi’s SOI technology and Murata’s expertise in Wi-Fi connectivity solutions and advanced packaging. This 2.4 GHz Wi-Fi FEM integrates a low-noise amplifier (LNA), a power amplifier (PA) and two RF switches (SP4T, SP3T). The monolithic die uses a compact 16-pin, 2 x 2 mm LGA package ideal for either stand-alone use or in 4 x 4 MIMO and 8 x 8 MIMO modules.

“The new IEEE 802.11ax standard is utilizing high-order modulation schemes (1024 QAM) with demanding EVM requirements,” says Colin Hunt, vice president of worldwide sales at pSemi. “Traditional process technologies struggle to keep up with both performance and integration requirements, and only SOI can offer the ideal combination of integration and high performance. This new monolithic Wi-Fi module is a great example of the types of technology and product advancements pSemi and Murata can accomplish together.”

The 2.4 GHz Wi-Fi FEM is based on pSemi’s UltraCMOS® technology platform—a patented, advanced form of SOI. With its outstanding RF and microwave properties, SOI is an ideal substrate for integration. When paired with high-volume CMOS manufacturing—the most widely used semiconductor technology—the result is a reliable, repeatable technology platform that offers superior performance compared to other mixed-signal processes. UltraCMOS technology also enables intelligent integration—the unique design ability to integrate RF, digital and analog components on a single die.

Features, Packaging and Availability 

The PE561221 leverages the intelligent integration capabilities of UltraCMOS technology to deliver exceptional performance, low power consumption and high reliability with 2 kV HBM ESD rating. Through advanced analog and digital design techniques, the Wi-Fi FEM delivers excellent long-packet EVM performance with less than 0.1 dB of gain droop while operating across the entire -40°C to 85°C temperature range. At -40 dB EVM (MCS9), the output power is +19 dBm with less than 0.05 dBm droop in power output after a 4 milliseconds packet. The IC delivers best-in-class dynamic error vector magnitude (DEVM) and current consumption without requiring digital pre-distortion (DPD), and it has excellent MCS11 performance for 802.11ax applications.

Volume-production parts and samples of the PE561221 are available from pSemi. For sales information, please contact [email protected].

The PE561221 is the first product in the pSemi Wi-Fi FEM portfolio; the product roadmap includes 5 GHz Wi-Fi FEM solutions.