Category Archives: Semiconductors

IC Insights recently released its Mid-Year Update to The McClean Report 2018.  The update includes a revised forecast of the largest and fastest-growing IC product categories this year.  Sales and unit growth rates are shown for each of the 33 IC product categories defined by the World Semiconductor Trade Statistics (WSTS) organization in the Mid-Year Update.

The five largest IC product categories in terms of sales revenue and unit shipments are shown in Figure 1.  With forecast sales of $101.6 billion, (39% growth) the DRAM market is expected to be the largest of all IC product categories in 2018, repeating the ranking it held last year.  If the sales level is achieved, it would mark the first time an individual IC product category has surpassed $100.0 billion in annual sales. The DRAM market is forecast to account for 24% of IC sales in 2018.  The NAND flash market is expected to achieve the second-largest revenue level with total sales of $62.6 billion this year. Taken together, the two memory categories are forecast to account for 38% of the total $428.0 billion IC market in 2018.

Figure 1

For many years, the standard PC/server MPU category topped the list of largest IC product segments, but with ongoing increases in memory average selling prices, the MPU category is expected to slip to the third position in 2018.  In the Mid-Year Update, IC Insights slightly raises its forecast for 2018 sales in the MPU category to show revenues increasing 5% to an all-time high of $50.8 billion, after a 6% increase in 2017 to the current record high of $48.5 billion.  Helping drive sales this year are AI-controlled systems and data-sharing applications over the Internet of Things.  Cloud computing, machine learning, and the expected tidal wave of data traffic coming from connected systems and sensors is also fueling MPU sales growth this year.

Two special purpose logic categories—computer and peripherals, and wireless communications—are forecast to round out the top five largest product categories for 2018.

Four of the five largest categories in terms of unit shipments are forecast to be some type of analog device.  Total analog units are expected to account for 54% of the total 318.1 billion IC shipments forecast to ship this year.  Power management analog devices are projected to account for 22% of total IC units and are forecast to exceed the combined unit shipment total of the next three categories on the list.  As the name implies, power management analog ICs help regulate power usage and to keep ICs and systems running cooler, to manage power usage, and ultimately to help extend battery life—essential qualities for an increasingly mobile and battery-powered world of devices.

By Laith Altimime

In a bid to reinvigorate Europe’s electronics strategy and strengthen the region’s position in key emerging technologies, European electronics industry CEOs in June called on public and private actors to accelerate collaboration at the European Union and national levels. The CEO’s proposed new strategic actions include creating a European Design Alliance to pool the expertise of design houses and forming an electronics education and skills task force consisting of representatives from industry, research, European institutions, member states and SEMI.

The business executive’s calls – embodied in “Boosting Electronics Value Chain in Europe,” a report submitted to Mariya Gabriel, Commissioner for Digital Economy and Society, of the European Commission – come as global competition in the electronics industry intensifies. The document highlights Europe’s need to buttress its position amongst others in artificial intelligence (AI), autonomous driving and personalized healthcare – applications that rely on new semiconductor architectures, materials, equipment and design methodologies.

The European semiconductor industry plans to pour more than 50 billion EUR into technology development and innovation by 2025, deepening its investments in research, innovation and manufacturing to help drive Europe’s digital transformation.

For its part, SEMI, as the industry association connecting the electronics value chain, is well-positioned to bring together member companies and public actors to address key challenges facing the sector. This year in April, SEMI announced that Electronics System Design Alliance (ESD Alliance) will join SEMI, adding key electronics design companies to SEMI membership and unlocking the full potential of collaboration between electronics design and manufacturing.  With the ESD Alliance, SEMI adds the product design segment to the electronics supply chain, streamlining and connecting the full ecosystem. The integration also promises to support the industry coordination required to develop specialized (AI) chips used in various smart applications.

SEMI Europe is also accelerating its education and workforce development activities. SEMI Europe this year created its Workforce Development Council Europe, chaired by Emir Demircan, SEMI Europe’s senior manager of public policy, based in Brussels. The council is designed to connect electronics industry human resources representatives with members to evolve best practices in hiring that help Europe gain, train and retain world-class talent.

Other SEMI Europe workforce development activities include the following:

  • SEMI member forums across Europe are helping young talent with career opportunities in the semiconductor industry.
  • In November, SEMICON Europa will host a Career Café where STEM students will explore careers in electronics design and manufacturing.
  • With the participation of representatives from the European Commission, SEMI Europe’s Industry Strategy Symposium in April focused on strategies for attracting more skilled workers into electronics design and manufacturing.

Looking ahead, semiconductor sales is forecast to reach USD 1 trillion by 2030. The global semiconductor industry is at the heart of a new era of connectivity, developing breakthrough solutions for ascendant data-driven technologies such as AI and Internet of Things (IoT). SEMI Europe’s role in strengthening the region’s position in the global electronics industry to help drive this extraordinary growth is critical. SEMI Europe will continue to foster public-private partnerships to tackle industry challenges that are too big, too risky and too costly for companies and government institutions to address alone.

Contact: Laith Altimime, President, SEMI Europe, [email protected] ; Emir Demircan, Sr Manager Public Policy, [email protected]

Originally published on the SEMI blog.

By Cherry Sun

Aiming to forge stronger ties between the two technology heavyweights as partners in semiconductor industry innovation, SEMI and CASPA (Chinese American Semiconductor Professional Association) in mid July signed a strategic cooperation agreement to promote industry innovation between Silicon Valley and China. Under the agreement, SEMI and CASPA will work to connect Silicon Valley and China industry resources and encourage greater collaboration.

The agreement, signed at the “SIIP China Innovation and Investment Forum: Innovation at Scale: from IoT, Cloud to AI & ADAS” in Silicon Valley, supports key SEMI principles including free trade, open markets, intellectual property protection, global cooperation and innovation, said SEMI China president Lung Chu.

Brandon Wang, president and chairman of CASPA, and Lung Chu, SEMI China president, sign strategic cooperation agreement.

Speaking at the event attended by more 200 industry executives and visionaries, Chu noted that with 2019 expected to be another record year for fab and equipment investment and the semiconductor on track to reach $500 billion by next year, the time is ripe for greater cooperation between Silicon Valley and China. China and South Korea (Samsung) are driving sharp growth in global semiconductor equipment sales.

The global artificial intelligence (AI) industry is taking shape with companies ranging from startups and multinationals to semiconductor and Internet providers investing in AI research and development as China and the United States make the heaviest AI investments of all regions. A plethora of AI applications enabled by 5G will spur even greater IC demand.

Opening the event, SEMI president and CEO Ajit Manocha noted that technologies such as AI, Internet of Things (IoT) will transform our lives and that semiconductor industry leaders must cultivate a new generation of innovators to ensure continued industry growth.

Mark Ding, CEO of Shanghai Industrial Technology Research Institute (SITRI), said China is well-positioned to help goose semiconductor industry growth with its ample capital, lower capital expenditures and strong local market. He also noted that three keys to innovation are platforms, talent and capital.

Dr. Naveed Shervani, CEO of SiFive, the first fabless semiconductor company to build customized silicon based on the free and open RISC-V instruction set architecture, proposed goals for future semiconductor industry growth including reducing IC and IP costs and cutting design time.

Stuart Ching, VP of KULR Technology, a provider of thermal management technologies, pointed to the importance of lithium batteries. Those with higher energy density and lower cost would promote a range of power applications for mobile electronic equipment and lead to the mass production of solid-state batteries between 2023 and 2025.

Originally published on the SEMI blog.

The semiconductor industry today is faced with several substantial issues-not the least of which are the continuing rise in design costs for complex SoCs, the decrease in the incidence of first-time-right designs and the increase in the design cycle time against shrinking market windows and decreasing product life cycles. An additional factor has now been added to SoC design costs with the emergence of very complicated software applications intended to run on the SoC silicon. The costs of the software effort have outstripped the silicon design costs and have become the major part of the cost of these designs. IP integration is also a growing part of design costs. Semico’s new report SoC Silicon and Software 2018 Design Cost Analysis: How Rising Costs Impact SoC Design Starts addresses these and many other design concerns while reporting that the average design cost for Basic SoCs across all geometries in 2017 was $1.7 million.

“Analysis of design activity for the three types of SoC profiled in this report shows that while design costs at new nodes continue to increase, the average design cost at each node is not increasing as quickly, giving room for designers to still accomplish their silicon solutions at reasonable costs if they are prudent in their design selection,” says Rich Wawrzyniak, Sr. Market Analyst for ASIC & SoC at Semico. “For each of the three types of SoC there is still considerable activity at the older nodes of 90nm, 65nm and 40nm. Costs at these geometries are much less than at 10nm and 7nm so even though these newer designs cost much more, the average for all SoCs has dropped due to the increase in new designs for Basic SoC.”

Key findings of the report include:

  • The average design cost for Value Multicore SoCs across all geometries was $4.8M in 2017.
  • The average design cost for all SoCs across all geometries is forecast to increase to $5.3M by 2023.
  • The number of ‘first-time-right’ designs has dropped at every process geometry since the 180nm node.
  • Silicon design costs at the 7nm node for an Advanced Performance Multicore SoC first-time effort are projected to be 23% higher than at the 10nm node.

In a unique, insightful look at this constantly evolving market, Semico Research’s new report, SoC Silicon and Software 2018 Design Cost Analysis: How Rising Costs Impact SoC Design Starts, examines the primary forces and integration pressures that are driving this market today in 135 pages, with 41 tables and 64 graphs. This study analyzes many important questions facing the semiconductor industry today including:

  • What is the current cost for a Complex System-on-a-Chip (SoC) design, and what will it be in the near future?
  • Is it possible to do SoC designs without maximizing the costs for these designs?
  • What is the incidence of ‘first-time-right’ for these designs today and in the near future?
  • How is the design cycle time for these designs changing?
  • How do complicated software applications impact the design costs?
  • How fast are IP integration costs rising, and how high will they go?
  • What strategies are designers using to cope with rising design costs?
  • What is the average silicon design cost today for each process geometry and SoC type, and how quickly is it rising?
  • What impact will EDA tools that include some artificial intelligence (AI) and machine learning (ML) functionality have on design costs for complex silicon?

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $117.9 billion during the second quarter of 2018, an increase of 6.0 percent over the previous quarter and 20.5 percent more than the second quarter of 2017. Global sales for the month of June 2018 reached $39.3 billion, an uptick of 1.5 percent over last month’s total of $38.7 billion, and a surge of 20.5 percent compared to the June 2017 total of $32.6 billion. Cumulatively, year-to-date sales during the first half of 2018 were 20.4 percent higher than they were at the same point in 2017. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Halfway through 2018, the global semiconductor industry continues to post impressive sales totals, notching its highest-ever quarterly sales in Q2 and record monthly sales in June,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Global sales have increased year-to-year by more than 20 percent for 15 consecutive months, and sales of every major product category increased year-to-year in June. Sales into the Americas market continue to be strong, with year-to-date totals more than 30 percent higher than at the same point last year.”

Regionally, sales increased compared to June 2017 in China (30.7 percent), the Americas (26.7 percent), Europe (15.9 percent), Japan (14.0 percent), and Asia Pacific/All Other (8.6 percent). Sales also were up compared to last month in China (3.2 percent), Japan (1.3 percent), the Americas (1.2 percent), and Asia Pacific/All Other (0.5 percent), but down slightly in Europe (-0.8 percent).

For comprehensive monthly semiconductor sales data and detailed WSTS Forecasts, consider purchasing the WSTS Subscription Package. For detailed data on the global and U.S. semiconductor industry and market, consider purchasing the 2018 SIA Databook.

United Microelectronics Corporation (NYSE: UMC; TWSE: 2303) (“UMC”), a global semiconductor foundry, and Avalanche Technology, Inc., the next generation STT-MRAM (Spin Transfer Torque Magnetic RAM) leader, today announced that they have entered a partnership for joint development and production of MRAM to replace embedded flash. UMC will also make this technology available to other companies through licensing with Avalanche Technology Inc.

Under the terms of the agreement, UMC will provide embedded non-volatile MRAM blocks based on UMC’s 28nm CMOS manufacturing process. This will enable customers to integrate low latency, very high performance and low power embedded MRAM memory blocks into MCUs and SoCs, targeting the Internet of Things, wearable, consumer, industrial and automotive electronics markets.

The two companies are also considering to expand the cooperation beyond 28nm, as Avalanche Technology’s CMOS compatibility and scalability to advanced process nodes enables integration of unified memory (non-volatile as well as SRAM) blocks into next generation highly integrated MCUs and SoCs. This allows system designers to maintain the same architecture and software ecosystem without a redesign.

“We’re excited to team with a world leader in semiconductor manufacturing such as UMC to bring this outstanding technology to market,” said Petro Estakhri, CEO and co-founder of Avalanche Technology.

“UMC is continuously introducing enhanced process offerings to bring added competitive benefits to our customers,” said G C Hung, vice president of Advanced Technology Development at UMC. “With embedded NVM becoming more prevalent in today’s IC designs, we have developed a strong portfolio of robust eNVM process solutions for high growth sectors such as emerging consumer and automotive applications. We are happy to cooperate with Avalanche Technology for 28nm MRAM, and we look forward to ramping this process to production for UMC customers.”

Samsung Electronics Co., Ltd. today announced that it has begun mass producing the industry’s first 4-bit (QLC, quad-level cell) 4-terabyte (TB) SATA solid-state drive (SSD) for consumers.

Based on 1-terabit (Tb)* V-NAND with outstanding performance equivalent to the company’s 3-bit design, Samsung’s QLC SSD is expected to bring a new level of efficiency to consumer SSDs.

“Samsung’s new 4-bit SATA SSD will herald a massive move to terabyte-SSDs for consumers,” said Jaesoo Han, executive vice president of memory sales & marketing at Samsung Electronics. “As we expand our lineup across consumer segments and to the enterprise, 4-bit terabyte-SSD products will rapidly spread throughout the entire market.”

With its new 1Tb 4-bit V-NAND chip, Samsung will be able to efficiently produce a 128GB memory card for smartphones that will lead the charge toward higher capacities for high-performance memory storage.

Typically, as data stored within a memory cell increases from three bits to four, the chip capacity per unit area would rise and the electrical charge (used to determine information from a sensor) would decrease by as much as 50 percent, making it considerably more difficult to maintain a device’s desired performance and speed.

However, Samsung’s 4-bit 4TB QLC SATA SSD maintains its performance levels at the same level as a 3-bit SSD, by using a 3-bit SSD controller and TurboWrite technology, while increasing drive capacity through the use of 32 chips, all based on 64-layer fourth-generation 1Tb V-NAND.

The 4-bit QLC SSD enables a sequential read speed of 540 MB/s and a sequential write speed of 520 MB/s, and comes with a three-year warranty.

Samsung plans to introduce several 4-bit consumer SSDs later this year with 1TB, 2TB, and 4TB capacities in the widely used 2.5-inch form factor.

Since introducing the 32-gigabyte (GB) 1-bit SSD in 2006, which ushered in the PC SSD era, to today’s 4TB 4-bit SSD, Samsung continues to drive new thresholds for each multi-bit generation.**

In addition, the company expects to provide M.2 NVMe SSDs for the enterprise this year and begin mass production of 4-bit fifth-generation V-NAND. This will considerably expand its SSD lineup to meet the growing demand for faster, more reliable performance across a wide span of applications, such as next generation data centers, enterprise servers, and enterprise storage.

* 1Tb (128GB) x 32 = 4TB (4,096GB)

** Samsung’s mass production history of SSDs in bits per cell

Year Bit Nodes Chip Capacity Drive Capacity
2006 1-bit SLC (single-level cell) 70nm-class 4Gb 32GB
2010 2-bit MLC (multi-level cell) 30nm-class 32Gb 512GB
2012 3-bit TLC (triple-level cell) 20nm-class 64Gb

500GB
2018 4-bit QLC (quad-level cell) 4th-gen V-NAND 1Tb 4 TB

A UCF physicist has discovered a new material that has the potential to become a building block in the new era of quantum materials, those that are composed of microscopically condensed matter and expected to change our development of technology.

Researchers are entering the Quantum Age, and instead of using silicon to advance technology they are finding new quantum materials, conductors that have the ability to use and store energy at the subatomic level.

Assistant Professor Madhab Neupane has spent his career learning about the quantum realm and looking for these new materials, which are expected to become the foundation of the technology to develop quantum computers and long-lasting memory devices. These new devices will increase computing power for big data and greatly reduce the amount of energy required to power electronics.

Madhab Neupane and his research team with the in-house ARPES system. From left to right: Gyanendra Dhakal (Graduate student), Klauss Dimitri (Undergraduate student), Md Mofazzel Hosen (Graduate student), Madhab Neupane, Christopher Sims (Graduate student), Firoza Kabir (Graduate student) Credit: University of Central Florida

Big companies recognize the potential and they are investing in research. Microsoft has invested in its Station Q, a lab dedicated solely to studying the field of topological quantum computing. Google has teamed up with NASA on a Quantum AI Lab that studies how quantum computing and artificial intelligence can mesh. Once the quantum phenomena are well understood and can be engineered, the new technologies are expected to change the world, much like electronics did at the end of the 20th century.

Neupane’s discovery, published today in Nature Communications is a big step in making that reality happen.

“Our discovery takes us one step closer to the application of quantum materials and helps us gain a deeper understanding of the interactions between various quantum phases,” Neupane said.

The material Neupane and his team discovered, Hf2Te2P – chemically composed of hafnium, tellurium and phosphorus — is the first material that has multiple quantum properties, meaning there is more than one electron pattern that develops within the electronic structure, giving it a range of quantum properties.

Neupane’s research group is using its specialized equipment for advanced-spectroscopic characterization of quantum materials to develop their work further.

“With the discovery of such an incredible material, we are at the brink of having a deeper understanding of the interplay of topological phases and developing the foundation for a new model from which all technology will be based off, essentially the silicon of a new era,” Neupane said.

The term energy harvesting, also known as power scavenging, is used to describe the creation of energy derived from a variety of external sources such as solar power, thermal energy, wind energy, kinetic energy or electromagnetic sources. Energy harvesters accumulate the wasted energy in a system, such as heat given off by motors or semiconductors, or the vibrations of motors or other moving objects. The basic technologies for generating energy are: mechanical vibration (kinetic energy), thermoelectric, solar (photovoltaic), and RF/Inductive.  A new research report from Semico Research Energy Harvesting: Reaping the Abundant Market, estimates that the semiconductor content for energy harvesting solutions will explode to $3.4 billion by 2022.

“While there is a great deal of interest in the different types of energy harvesting devices or energy generators, the greater opportunity for the semiconductor industry is the overall solution which includes power conversion, power management, microcontrollers, radios and MEMS sensors,” says Joanne Itow, Semico’s Manager of Manufacturing Research. “The advent of IoT with remote monitoring and data collection has also prompted more interest in energy harvesting as a viable solution to maintain WSNs (Wireless Sensor Networks).”

Key findings of the report include:

  • The number of devices with an energy harvesting solution will reach 509 million units by 2022.
  • Consumer devices (including toys) with energy harvesting accounted for 8 million units in 2017.
  • Bridges are expected to be a large user of energy harvesting in the infrastructure sector by 2022.
  • Energy harvesting devices in all buildings is expected to have a CAGR of 20.7% by 2022.

In its recent report “Energy Harvesting: Reaping the Abundant Market” (MP112-18), Semico Research examines the market opportunity for energy harvesting outside of large solar installations and commercial power generation. A broad range of markets will employ energy harvesting to either replace batteries or extend battery life. These applications cover wireless sensor nodes (WSN) for bridges, infrastructure, building automation and controls, home automation (including lighting, security and environmental), automotive applications, cell phones, wearables and other consumer electronics. The report is 98 pages long and includes 13 tables and 37 figures.

Companies cited in the report include:

Analog Devices, Microchip (Atmel), CHERRY/ZF, Cymbet, Cypress, EnOcean, e-peas, Analog Devices/Linear Technology, Maxim Integrated, Microchip Technology, Powercast, Renesas, Semtech, Silicon Labs, Silicon Reef, STMicroelectronics, Texas Instruments, Ilika, Imprint Energy, Sakti3, Solid Power, Apple, Laird, microGen, Micropelt, Perpetuum, Piezo Systems, Sanyo, Thermo Life, Thermogen Technologies, EH Solution Providers, LORD Microstrain®, National Instruments, Nikola Labs, Phase IV Engineering, Resensys, Soundpower Corp., Eta Compute, Mentor Graphics, and X-FAB.

Entegris, Inc. (NASDAQ: ENTG) today released the next generation EUV 1010 Reticle Pod for high-volume IC manufacturing using extreme ultraviolet (EUV) lithography. Developed in close collaboration with ASML, one of the world’s largest manufacturers of chip-making equipment, Entegris’s EUV 1010 is the first to be qualified by ASML for use in the NXE:3400B and beyond.

As the semiconductor industry begins ramping EUV lithography for the high-volume manufacturing (HVM) of advanced technology nodes, keeping EUV reticles defect-free is more demanding than ever.  Entegris’s EUV 1010 Reticle Pod is now fully qualified by ASML for their latest generation scanner having demonstrated outstanding protection of the EUV reticles, including against the most critical particle challenges.  As a result, Entegris’s EUV 1010 enables customers to safely transition to smaller and smaller line widths, as needed for the most advanced lithography processes.

To achieve these levels of performance within the NXE:3400B scanner, Entegris developed new technologies for contacting the reticles and controlling the environment. “The Entegris EUV 1010 represents a significant breakthrough in improving defectivity so customers implementing HVM for advance technology nodes can focus on increasing efficiency and throughput,” said Paul Magoon, vice president of wafer and reticle handing for Entegris. “Development and testing with ASML ensures that EUV 1010 has been qualified for the most advanced EUV scanner available.”

Entegris is ISO 9001 certified and has manufacturing, customer service and/or research facilities in the United States, China, France, Germany, Israel, Japan, Malaysia, Singapore, South Korea and Taiwan.