Category Archives: Semiconductors

Scientists from the University of Konstanz and Paderborn University have succeeded in producing and demonstrating what is known as Wannier-Stark localization for the first time. In doing so, the physicists managed to overcome obstacles that had so far been considered insurmountable in the field of optoelectronics and photonics. Wannier-Stark localization causes extreme imbalance within the electric system of crystalline solids. “This fundamental effect was predicted more than 80 years ago. But it has remained unclear ever since whether this state can be realized in a bulk crystal, that is, on the level of chemical bonds between atoms,” says Professor Alfred Leitenstorfer, Professor of Experimental Physics at the University of Konstanz. Analogues of the effect have so far been demonstrated only in artificial systems like semiconductor superlattices or ultracold atomic gases. In a bulk solid, Wannier-Stark localization can only be maintained for an extremely short period of time, shorter than a single oscillation of infrared light. Using the ultrafast laser systems at the University of Konstanz, Wannier-Stark localization has now been demonstrated for the first time. The experiment was conducted in a high-purity gallium arsenide crystal grown at ETH Zurich using epitaxial growth. The research results were published in the scientific journal Nature Communications on 23 July 2018.

What is Wannier-Stark localization?

If we tried to picture the atoms of a crystal, it would have to be as a three-dimensional grid composed of small beads that repel each other and are only kept together by rubber bands. The system remains stable as long as the rubber band is as strong as the repulsion is. If this is the case, the beads neither move closer to each other, nor do they move away from each other – the distance between them remains about the same. Wannier-Stark localization occurs when the rubber bands are removed abruptly. It is the electronic state that happens at the precise moment in time when the rubber bands have already gone but the beads still remain in place: The chemical bonds that hold the crystal together have been suspended.

If this state is maintained for too long, the beads will break apart and the crystal dissolves. To analyze Wannier-Stark localization, the physicists had to remove the stabilizing structures, capture the system within a fraction of a light oscillation using light pulses, and finally to stabilize it again to prevent the atoms from breaking apart. The experiment was made possible through the highly intense electric field of an ultrashort infrared light pulse, which is present in the crystal for a few femtoseconds only. “This is what we specialize in: studying phenomena that only exist on very short time scales,” explains Alfred Leitenstorfer.

“In perfect insulators and semiconductors, electronic states expand throughout the entire crystal. According to an 80-year-old prediction, this changes as soon as electrical voltage is applied,” says Professor Torsten Meier from Paderborn University. “If the electric field inside the crystal is strong enough, the electronic states can be localized to a few atoms. This state is called the Wannier-Stark ladder”, explains the physicist, who is also Vice-President for International Relations at Paderborn University.

New electronic characteristics

“A system that deviates so extremely from its equilibrium has completely new characteristics,” says Alfred Leitenstorfer about why this state is so interesting from a scientific perspective. The short-lived Wannier-Stark localization correlates with drastic changes to the electronic structure of the crystal and results, for example, in extremely high optical nonlinearity. The scientists also assume that this state is chemically particularly reactive.

The first-ever experimental realization of Wannier-Stark localization in a gallium arsenide crystal was made possible through highly intense Terahertz radiation with field intensities of more than ten million volts per centimetre. The application of more ultrashort optical light pulses resulted in changes to the crystal’s optical characteristics, which was instrumental to proving this state. “If we use suitably intense light pulses consisting of a few oscillations lasting some ten femtoseconds only, we can realize the Wannier-Stark localization for a short period of time,” says Alfred Leitenstorfer. “Our readings match the theoretical considerations and simulations carried out both by my own research team and by that of my colleague, Professor Wolf Gero Schmidt,” adds Torsten Meier. The researchers are planning to study the extreme state of Wannier-Stark localization on the atomic scale in more detail in the future and intend to make its particular characteristics usable.

Reaching their highest recorded quarterly level ever on robust demand, worldwide silicon wafer area shipments rose 2.5 percent in the second quarter of 2018 to 3,160 million square inches from 3,084 million square inches the previous quarter, according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry. New quarterly total area shipments are 6.1 percent higher than second quarter 2017 shipments.

“The second calendar quarter of the year typically enjoys a volume increase over the first quarter,” said Neil Weaver, chairman SEMI SMG and Director, Product Development and Applications Engineering of Shin Etsu Handotai America. “This quarter is no exception. Continued solid demand is driving record wafer volume shipments.”

Silicon* Area Shipment Trends

Millions of Square Inches
1Q2017
2Q2017
3Q2017
4Q2017
1Q2018
2Q2018
Total
2,858
2,978
2,997
2,977
3,084
3,160
*Semiconductor applications only
Source: SEMI, (www.semi.org), July

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices, or chips, are fabricated.

All data cited in this release includes polished silicon wafers, including virgin test wafers and epitaxial silicon wafers, as well as non-polished silicon wafers shipped by the wafer manufacturers to end users.

By Jay Chittooran, Public Policy Manager, SEMI 

Two months after opposing $34 billion in U.S. trade tariffs on behalf of the U.S. semiconductor manufacturing industry, Jonathan Davis, global vice president of industry advocacy at SEMI, this week spoke out against an additional $16 billion duties on Chinese goods. Testifying before the same U.S. interagency panel mulling the merits of the tariffs, Davis called for the removal of 29 tariff lines covering items critical to semiconductor manufacturing including machines and spare parts used to make, wafers, flat panel displays and masks.

In his testimony to the panel, Davis stressed that while SEMI supports stronger protections against the theft of valuable intellectual property (IP), tariffs do little to address U.S. concerns over IP loss. Over the past month, SEMI has also submitted written comments and opposed the tariffs in public testimony. The panel includes representatives from the U.S. Trade Representative (USTR), Departments of Treasury, Commerce, State and Defense, and the Council of Economic Advisers.

Also testifying, Joe Pon, corporate vice president at Applied Materials, explained that the proposed tariffs will harm small and midsized companies and other U.S. business interests. Describing the tariffs as a tax on exports of high-value U.S. goods, Pon said the duties give non-U.S. firms an unfair competitive advantage.

In a parallel push to Davis’s testimony, SEMI, with more than 10 representatives from six member companies, met with 16 congressional offices this week to underscore the damage the tariffs would wreak on the U.S. semiconductor industry. The fallout would include higher operating costs, fewer exports and slower innovation. The tariffs would also curb industry growth and put thousands of high-paying, high-skill jobs at risk. SEMI pressed congressional leaders to reject the tariffs and support a push for congress to re-assert itself on trade policy.

Tariffs to cost U.S. SEMI members more than $500 million

SEMI estimates that the second list of proposed tariffs, covering about $16 billion in Chinese goods, will cost its 400 U.S. members more than $500 million annually in additional duties.

The tariffs on $34 billion in Chinese goods, which took effect July 6, impact products such as test and inspection equipment as well as spare parts that enter the U.S. from China. That round of tariffs will cost SEMI member companies and estimated tens of millions of dollars annually.

SEMI public policy team asks members to review tariff list

Looking ahead, SEMI encourages members to review the newly released $200 billion tariff list, determine any impact to their businesses and share their findings with SEMI’s public policy team.

The U.S. Trade Representative (USTR) has published the exclusion process for products subject to the China 301 tariffs. If your company’s products are subject to tariffs, you can request an exclusion.

In evaluating product exclusion requests, the USTR will consider whether a product is available from a source outside of China, whether the additional duties would cause severe economic harm to the requestor or other U.S. interests, and whether the product is strategically important or related to Chinese industrial programs (such as “Made in China 2025”).

The deadline for submitting product exclusion requests to USTR is October 9, 2018. Approved exclusions will be effective for one year upon approval and retroactive to July 6, 2018.

More information including the process for submitting the product exclusion request can be found here.

Any SEMI members with questions should contact Jay Chittooran, Public Policy Manager at SEMI, at [email protected].

Imec, a research and innovation hub in nanoelectronics and digital technologies, announces that Niels Verellen, one of its young scientists, has been awarded an ERC Starting Grant. The grant of 1.5 million euros (for 5 years) will be used to enable high-resolution, fast, robust, zero-maintenance, inexpensive and ultra-compact microscopy technology based on on-chip photonics and CMOS image sensors. The technology paves the way for multiple applications of cell imaging in life sciences, biology, and medicine and compact, cost-effective DNA sequencing instruments.

Microscopy is an indispensable tool in biology and medicine that has fueled many breakthroughs. Recently the world of microscopy has witnessed a true revolution in terms of increased resolution of fluorescent imaging techniques, including a Nobel Prize in 2014. Yet, these techniques remain largely locked-up in specialized laboratories as they require bulky, expensive instrumentation and highly skilled operators.

The next big push in microscopy with a large societal impact will come from extremely compact and robust optical systems that will make high-resolution microscopy highly accessible and as such facilitate the diagnosis and treatment of diseases or disorders caused by problems at the cell or molecular level, such as meningitis, malaria, diabetes, cancer, and Alzheimer’s disease. Moreover, it will pave the way to DNA analysis as a more standard procedure, not only for the diagnosis of genomic disorders or in forensics, but also in cancer treatment, follow-up of transplants, the microbiome, pre-natal tests, and even agriculture, and archeology.

Niels Verellen, Senior Photonics Researcher & project leader at imec: “Compact, high-resolution and high-throughput microscopy devices will induce a profound change in the way cell biologists do research, in the way DNA sequencing becomes more and more accessible, in the way certain diseases can be diagnosed, new drugs are screened in the pharma industry, and healthcare workers can diagnose patients in remote areas.”

The topic of Verellen’s ERC grant is the development of Integrated high-Resolution On-Chip Structured Illumination Microscopy (IROCSIM). This new technology is based on a novel imaging platform that integrates active on-chip photonics and CMOS image sensors. “Whereas existing microscopy techniques today suffer from a trade-off between equipment size, field-of-view, and resolution, the IROCSIM solution will eliminate the need for bulky optical components and enable microscopy in the smallest possible form-factor, with a scalable field-of-view and without compromising the resolution,” continues Verellen.

The European Research Council (ERC) is a pan European funding body designed to support investigator-driven frontier research and stimulate scientific excellence across Europe. The ERC aims to support the best and most creative scientists to identify and explore new opportunities and directions in any field of research. ERC Starting grants in particular are designed to support outstanding researchers with 2 to 7 years postdoctoral experience.

Jo De Boeck, imec’s CTO says: “We are very proud that young researchers such as Niels Verellen are awarded an ERC Starting Grant and as such get a unique opportunity to fulfill their ambitions and creative ideas in research. At imec, we select and foster our young scientists and provide them with a world-class infrastructure. These ERC Starting Grants show that their work indeed meets the highest standards.”

The silicon-on-insulator market is expected to reach USD 1,832.5 million by 2023 from USD 686.0 million by 2018, at a CAGR of 21.7%, According to the new market research report “Silicon on Insulator (SOI) Market by Wafer Size (200 mm and less than 200 mm, 300 mm), Wafer type (RF-SOI, FD-SOI, PD-SOI, Power SOI, Emerging-SOI), Application (Consumer Electronics, Automotive, Datacom, Industrial), Technology – Global Forecast to 2023”, published by MarketsandMarkets™ . The increasing use of SOI wafers in advanced devices such as smartphones, tablets, earphones/headphones, and wearables is expected to boost the market for consumer electronics application. Moreover, while manufacturing thin wafers, the use of SOI technology prevents the wastage of silicon, which reduces the cost of semiconductor devices. Hence, the effective use of silicon during the manufacture of thin SOI wafers is a major factor driving the growth of the SOI market.

SOI market for 300-mm wafers size to grow at a higher CAGR during forecast period

The market for 300-mm wafer size is expected to grow at the highest CAGR during 2018-2023. Wafer and foundry players expanding their capacity for producing 300-mm wafers is one of the driving factors for the growth of the SOI market. For instance, Soitec expanded its manufacturing capacity for the production of 300-mm SOI wafers.

Consumer electronics application expected to hold the largest share of the SOI market during the forecast period

Among the SOI applications, the market for consumer electronics is expected to hold the largest share during 2018-2023. The growth of this market is attributed to the increasing demand for SOI products in smartphones and other consumer electronics devices. For instance, RF SOI wafers are commonly used in smart devices as these wafers enable device integration, cost-effectiveness, and high performance. Also, the growing adoption of FD SOI for consumer or IoT devices is expected to drive the growth of the market.

SOI market in APAC expected to grow at the highest CAGR during the forecast period

SOI market in APAC is expected to grow at the highest CAGR during 2018-2023. APAC is witnessing an increase in the use of SOI products owing to the presence of a large number of consumer electronic companies, smartphone manufacturers, and advanced ICT technology providers, and wafer and foundry players in APAC.

Major players operating in this market are Soitec (France), Shin-Etsu Chemical (Japan), GlobalWafers (Taiwan), SUMCO (Japan), Simgui (China), GlobalFoundries (US), STMicroelectronics N.V. (Switzerland), TowerJazz (Isreal), NXP Semiconductor N.V. (Netherlands), and Murata Manufacturing (Japan).

Know more about the Silicon on Insulator (SOI) Market:

https://www.marketsandmarkets.com/Market-Reports/global-silicon-on-insulator-market-158.html

SiFive, the provider of commercial RISC-V processor IP, today welcomed Chipus Microelectronics, a semiconductor company with proven expertise in the development of ultra-low-power (ULP), low-voltage, analog and mixed-signal integrated circuits, to the growing DesignShare ecosystem. Through the partnership, Chipus will provide ULP IP for power management and ULP RF Front-Ends.

Chipus’ customizable technology will make it easier for SiFive customers to save power and extend battery life for IoT edge devices. Chipus also plans to add temperature sensors and switched regulators to the DesignShare program in the near future.

“Chipus is thrilled to partner up with SiFive to bring more chip design opportunities to reality, enabling innovation with our Ultra-Low-Power and simple-to-customize IP solutions,” said Murilo Pilon Pessatti, CEO and co-founder of Chipus. “Our mission, together with SiFive, is to enable innovation. With our expertise, Chipus looks forward to contributing to new IoT applications and edge devices.”

The availability of Chipus’ ULP IP through the DesignShare program shortens the time to market and removes common barriers to entry that have traditionally prevented smaller companies from developing custom silicon. Companies like SiFive, Chipus and other DesignShare partners provide low- or no-entry fee IP to emerging companies, minimizing the upfront engineering costs needed to bring a custom chip from design to realization.

“Startups today go through extensive processes, from sourcing viable IP to negotiating legal contracts, before they can even develop a prototype,” said Shafy Eltoukhy, vice president of operations and head of DesignShare for SiFive. “With Chipus joining our growing DesignShare economy, we continue to simplify the prototyping process and spur innovation across the industry.”

Since DesignShare launched in 2017, the program has grown to include a wide range of IP solutions, from complete ASIC solutions and trace technology to embedded memory and precision PLL. For more information on DesignShare and to see the complete list of available technologies, visit www.sifive.com/designshare.

Hewlett Packard Enterprise (HPE) and PLDA®, an industry leader in high-speed interconnect IP, today announced a joint collaboration to meet the challenges of next-generation connectivity for advanced workloads. Gen-Z is a new open interconnect protocol and connector developed by the Gen-Z Consortium to solve the challenges associated with processing and analyzing huge amounts of data in real time. HPE and PLDA are working together to develop Gen-Z semiconductor IP designed to the Gen-Z Core Specification 1.0.

Announced in February 2018, the Core Specification 1.0 enables the industry to begin the development of products that incorporate the Gen-Z interconnect protocol.

Creating one standard interconnect is important because it allows any component – processing, memory, accelerators, networking – to talk to any other component as if it were communicating with its own local memory using simple commands. PLDA’s Gen-Z IP will provide the building blocks to create high performance low latency solutions where every device in the system is connected at the speed of memory.

“PLDA is proud to collaborate with HPE to provide comprehensive design IP to silicon providers to enable volume production of Gen-Z compatible components and to enable system vendors to utilize the Gen-Z silicon components to build network, storage and compute systems and solutions,” said Arnaud Schleich, CEO, at PLDA. “This will enable an open ecosystem of Gen-Z building blocks for a variety of solutions from the intelligent edge to the cloud.”

With Gen-Z, the industry can simultaneously support memory, I/O, storage and different forms of compute on a common disaggregated, composable or memory-semantic fabric (or interconnect).

Gen-Z reflects a broader industry trend that recognizes the importance and role of open standards in providing a level playing field to promote adoption, innovation and choice. By enabling technologists to collaborate and contribute to an open and competitive ecosystem, Gen-Z will help the industry fundamentally change how the world thinks about computing.

“At HPE, we recognize the need to partner in the development of new architectures and technologies that can effectively meet the needs of our customers,” said Mark Potter, CTO, HPE and Director, Hewlett Packard Labs. “HPE is committed to supporting open standards and working collaboratively to develop this new interconnect. The collaboration with PLDA is a demonstration of HPE’s commitment to the development and industry-wide proliferation of Gen-Z, an important technology in meeting the demands of the modern data center and in creating a Memory-Driven Computing architecture.”

With Gen-Z, the industry can combine fast persistent memory, DRAM and task-specific processing and accelerators on a fast memory fabric without legacy constraints or device hierarchies. This approach optimizes and simplifies system configurations to deliver optimal performance tailored to specific user demands simply and efficiently with better performance at reduced cost.

In a key move to inspire the next generation of innovators, the School District of Osceola County (SDOC) today became the first school district to join the SEMI High Tech U (HTU) Certified Partner Program (CPP), a curriculum that prepares high-school students to pursue careers in STEM fields.

Under the program sponsored by the SEMI Foundation, SDOC will independently deliver HTU programs to local students at the Osceola Technical College Campus, in Kissimmee, Florida. SEMI Foundation awarded SDOC the certification today at a graduation ceremony for HTU students.

“SDOC’s partnership with the SEMI Foundation gives young people and families in our community exposure to high-tech career opportunities and the educational pathways to reach their goals,” said Debra Pace, superintendent of School District of Osceola County. “Our industry partners – including Mercury, University of Central Florida, BRIDG, Osceola Technical College, imec, Neo City and the Osceola County Education Foundation – have all made it possible for SDOC to offer this amazing opportunity to students.”

“We are delighted to partner with SDOC in our common goal to motivate the next generation of innovators,” said Leslie Tugman, executive director of the SEMI Foundation. “The School District of Osceola County is well-positioned to put college-bound high school students on a track that speeds the time from graduation to employment in high technology. SDOC’s certification is a tremendous benefit for it students, the community and employers in the fast-growing Central Florida tech corridor.”

To win the certification, SDOC delivered HTU over the past three years with guidance and instruction from SEMI. SDOC is only the second organization to receive the certification.

The nonprofit SEMI Foundation has been delivering its flagship program, SEMI High Tech U, at industry sites around the world since 2001 to emphasize the importance of STEM skills and inspire young people to pursue careers in high-technology fields. HTU students meet engineers and STEM volunteer instructors from industry for site tours and hands-on classroom activities such as etching wafers, making circuits, coding and training for professional interviews.

SEMI’s Certified Partner Program identifies organizations that provide quality training and can recruit and educate local high-school students in the value of careers in science, technology, engineering and math (STEM). Participating organizations are trained to deliver the unique SEMI curriculum with the support of volunteer instructors from the high-tech and STEM industries. SEMI High Tech U is the longest-running STEM career exploration program in the United States with documented student impact. Since inception, SEMI has reached over 8,000 high-school students in 12 states and nine countries with its award-winning program.

SEMI Foundation is a 501(c)(3) nonprofit charitable organization founded in 2001 to support education and career awareness in the electronics and high-tech fields through career exploration programs and scholarships. For more information, visit www.semifoundation.org.

Solar cells need to slim down.

Solar cells are devices that absorb photons from sunlight and convert their energy to move electrons — enabling the production of clean energy and providing a dependable route to help combat climate change. But most solar cells used widely today are thick, fragile and stiff, which limits their application to flat surfaces and increases the cost to make the solar cell.

“Thin-film solar cells” could be 1/100th the thickness of a piece of paper and flexible enough to festoon surfaces ranging from an aerodynamically sleek car to clothing. To make thin-film solar cells, scientists are moving beyond the “classic” semiconductor compounds, such as gallium arsenide or silicon, and working instead with other light-harvesting compounds that have the potential to be cheaper and easier to mass produce. The compounds could be widely adopted if they could perform as well as today’s technology.

In a paper published online this spring in the journal Nature Photonics, scientists at the University of Washington report that a prototype semiconductor thin-film has performed even better than today’s best solar cell materials at emitting light.

“It may sound odd since solar cells absorb light and turn it into electricity, but the best solar cell materials are also great at emitting light,” said co-author and UW chemical engineering professor Hugh Hillhouse, who is also a faculty member with both the UW’s Clean Energy Institute and Molecular Engineering & Sciences Institute. “In fact, typically the more efficiently they emit light, the more voltage they generate.”

The UW team achieved a record performance in this material, known as a lead-halide perovskite, by chemically treating it through a process known as “surface passivation,” which treats imperfections and reduces the likelihood that the absorbed photons will end up wasted rather than converted to useful energy.

“One large problem with perovskite solar cells is that too much absorbed sunlight was ending up as wasted heat, not useful electricity,” said co-author David Ginger, a UW professor of chemistry and chief scientist at the CEI. “We are hopeful that surface passivation strategies like this will help improve the performance and stability of perovskite solar cells.”

Ginger’s and Hillhouse’s teams worked together to demonstrate that surface passivation of perovskites sharply boosted performance to levels that would make this material among the best for thin-film solar cells. They experimented with a variety of chemicals for surface passivation before finding one, an organic compound known by its acronym TOPO, that boosted perovskite performance to levels approaching the best gallium arsenide semiconductors.

“Our team at the UW was one of the first to identify performance-limiting defects at the surfaces of perovskite materials, and now we are excited to have discovered an effective way to chemically engineer these surfaces with TOPO molecules,” said co-lead author Dane deQuilettes, a postdoctoral researcher at the Massachusetts Institute of Technology who conducted this research as a UW chemistry doctoral student. “At first, we were really surprised to find that the passivated materials seemed to be just as good as gallium arsenide, which holds the solar cell efficiency record. So to double-check our results, we devised a few different approaches to confirm the improvements in perovskite material quality.”

DeQuilettes and co-lead author Ian Braly, who conducted this research as a doctoral student in chemical engineering, showed that TOPO-treating a perovskite semiconductor significantly impacted both its internal and external photoluminescence quantum efficiencies — metrics used to determine how good a semiconducting material is at utilizing an absorbed photon’s energy rather than losing it as heat. TOPO-treating the perovskite increased the internal photoluminescence quantum efficiencies by tenfold — from 9.4 percent to nearly 92 percent.

“Our measurements observing the efficiency with which passivated hybrid perovskites absorb and emit light show that there are no inherent material flaws preventing further solar cell improvements,” said Braly. “Further, by fitting the emission spectra to a theoretical model, we showed that these materials could generate voltages 97 percent of the theoretical maximum, equal to the world record gallium arsenide solar cell and much higher than record silicon cells that only reach 84 percent.”

These improvements in material quality are theoretically predicted to enable the light-to-electricity power conversion efficiency to reach 27.9 percent under regular sunlight levels, which would push the perovskite-based photovoltaic record past the best silicon devices.

The next step for perovskites, the researchers said, is to demonstrate a similar chemical passivation that is compatible with easily manufactured electrodes — as well as to experiment with other types of surface passivation.

“Perovskites have already demonstrated unprecedented success in photovoltaic devices, but there is so much room for further improvement,” said deQuilettes. “Here we think we have provided a path forward for the community to better harness the sun’s energy.”

Semiconductor Research Corporation (SRC), today announced the release of $26 million in added research funding for its New Science Team (NST) Joint University Microelectronics Program (JUMP). JUMP will fund 24 additional research projects spanning 14 unique U.S. universities. The new projects will be integrated into JUMP’s six existing research centers. NST will continue to distribute funds over its five-year plan, and industrial sponsors are welcome to join to further accentuate those plans.

The awards have been given to 27 faculty and will enhance the program’s expertise in technical areas such as atomic layer deposition (ALD), novel ferroelectric and spintronic materials and devices, 3D and heterogeneous integration, thermal management solutions, architectures for machine learning and statistical computing, memory abstractions, reconfigurable RF frontends, and mmWave to THz arrays and systems for communications and sensing.

“The goal of the NST project is not only to extend the viability of Moore’s Law economics through 2030, but to also change the research paradigm to one of co-optimization across the design hierarchy stack through multi-disciplinary teams,” said Ken Hansen, President and CEO of Semiconductor Research Corporation. “Our strategic partnerships with industry, academia, and government agencies foster the environment needed to realize the next wave of semiconductor technology innovations.”

“A new wave of fundamental research is required to unlock the ultimate potential of autonomous vehicles, smart cities, and Artificial Intelligence (AI),” said Dr. Michael Mayberry, Senior Vice President and Chief Technology Officer of Intel and the elected Chairman of the NST Governing Council. “Such advances will be fueled by novel and far-reaching improvements in the materials, devices, circuits, architectures, and systems used for computing and communications.”

The JUMP program, a consortium consisting of 11 industrial participants and the Defense Advanced Research Projects Agency (DARPA), is one of two complementary research programs for the NST project—a 5-year, greater than $300 million SRC initiative launched this January. JUMP and its six thematic centers will advance a new wave of fundamental research focused on the high-performance, energy-efficient microelectronics for communications, computing, and storage needs for 2025 and beyond.