Category Archives: Semiconductors

By Cherry Sun

Storage and memory chipmaker and SEMI China member Tsinghua Unigroup is gearing up to meet burgeoning product demand with huge investments in its manufacturing plants. But the high-tech enterprise under Tsinghua University is eyeing a much bigger prize – growth of the region’s semiconductor industry and the realization of its ambition to become a more prominent force on the global stage.

Inspired by the national strategy, the Tsinghua Unigroup’s big spends include USD 24 billion in Wuhan (Yangtze Memory Technologies Co., Ltd.,) USD 30 billion in Chengdu, USD 30 billion in Nanjing and USD 100 billion in Chongqing, said Liu Hongyu, senior vice president of Tsinghua Unigroup, speaking at the SEMI China Equipment and Materials Committee meeting last month.

Advanced packaging is another rich vein of opportunity the region is tapping for expansion, said Liu Hongjun, vice president of China Wafer Level CSP Co., Ltd., another SEMI China member attending the event, hosted by NAURA in Beijing. Hongjun sees strong growth for Fan-in, Fan-out, FCBGA, 2.5D and 3DIC, with Fan-out out front.

Liang Sheng, administrative commission director at BDA, a business advisory firm supporting high-technology manufacturing in the E-Town economic development zone, pointed to 5G chips and smart, networked electric automobiles as drivers of the next growth phase of Beijing’s integrated circuit (IC) industry.

Global tailwinds are lifting China’s semiconductor industry and the region’s hopes, with SEMI and major industry analysts raising their semiconductor industry growth projects for 2018 to between 9 percent and 16 percent. According to SEMI’s latest market report, global semiconductor industry manufacturing equipment revenue reached USD 17 billion in the first quarter of 2018, logging all-time highs after jumping 12 percent from the previous quarter and 30 percent year-over-year. Korea was the top-performing region at USD 6.26 billion, followed by China at USD 2.64 billion.

Tighter integration with the rest of the global semiconductor industry is critical to the growth of China’s chip sector, and SEMI China is squarely focused on this assimilation, said SEMI China president Lung Chu. The spearhead of this effort is the SEMI Innovation Investment Platform (SIIP) China, established by SEMI China last year to help grow China’s pool of skilled workers, promote advanced technology, generate industry capital, and expand China’s semiconductor industry while developing stronger connections with chip sectors in other regions.

To strengthen ties with other regions, SIIP China will stage a number of innovation and investment forums this year including Chinese Night at SEMICON West (July 10-12) and a SIIP China Forum in Silicon Valley (July 15). In August, representatives from the Korea chip industry will visit counterparts in China (August), and a China delegation will travel to Japan for meetings (October). SIIP China is also strengthening the region’s links with Germany and Israel as SEMI serves as a crucial bridge between China’s semiconductor sector and the global industry.

At the invitation of Shanghai authorities and the Ministry of Commerce of the People’s Republic of China, SEMI China in November will join the China International Export & Import Exposition in Shanghai, an event that will underscore China’s commitment to the openness and cooperation of its semiconductor industry with the international chip community. As part of the exposition, SEMI will work with the Ministry of Commerce and domestic chip manufacturers to begin development of a special integrated circuit (IC) zone. SEMI China members are welcome to participate.

With workforce development no less vital to the future of China’s semiconductor industry, the Equipment & Materials Committee offered potential solutions to the industry’s talent gap. Measures included targeting university students and engineers with industry lectures and courses in key cities, campus recruiting, talent training that members said they are willing to help SEMI coordinate and stage and, much like the push to better integrate China with the global semiconductor industry, mobilizing member resources around a campaign to polish the image of the industry to make it more attractive to students and young workers.

Storage and memory chipmaker and SEMI China member Tsinghua Unigroup is gearing up to meet burgeoning product demand with huge investments in its manufacturing plants.

Cherry Sun is a marketing manager at SEMI China. 

Originally published on the SEMI blog.

Rahul Goyal of Intel has been elected to a one-year term as board chair of Silicon Integration Initiative, a research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. The election was held during Si2’s board meeting at the recent Design Automation Conference.

A member of the Si2 board since 2003, Goyal is vice president, Technology and Manufacturing Group and director, Research and Development Strategic Enabling for Intel. He has global responsibility for strategic sourcing, supply chain strategy, industry relations, ecosystem development, strategic collaborations, data analytics, and capacity management related to product development across Intel’s broad product portfolio. This includes software, system and semiconductor intellectual property, product development outsourcing services, electronic measurement solutions, electronic design automation software, prototyping and verification products used in all aspects of product design, validation and technology development.

Goyal joined Intel in 1989 and has held various technical and management positions in software engineering and technology development. His previous roles there include engineering director in the Design and Technology Solutions Group, director of the integrated silicon technology roadmap development in the Microprocessor Products Group, and senior engineering manager of mask operations.

Goyal holds a bachelor’s degree in electrical and electronics engineering from Birla Institute of Technology and Science, Pilani, India, and a master’s degree in computer engineering from Syracuse University, Syracuse, N.Y.

Taking a multiband approach explains ‘electron-hole reverse drag’ and exciton formation

Mystifying experimental results obtained independently by two research groups in the USA seemed to show coupled holes and electrons moving in the opposite direction to theory.

Now, a new theoretical study has explained the previously mysterious result, by showing that this apparently contradictory phenomenon is associated with the bandgap in dual-layer graphene structures, a bandgap which is very much smaller than in conventional semiconductors.

The study authors, which included FLEET collaborator David Neilson at the University of Camerino and FLEET CI Alex Hamilton at the University of New South Wales, found that the new multiband theory fully explained the previously inexplicable experimental results.

Excitons travel across an ultra-low energy transistor without wasted dissipation of energy. Credit: FLEET: ARC Centre of Excellence in Future Low Energy Electronics Technologies

Exciton transport

Exciton transport offers great promise to researchers, including the potential for ultra-low dissipation future electronics.

An exciton is a composite particle: an electron and a ‘hole’ (a positively charged ‘quasiparticle’ caused by the absence of an electron) bound together by their opposite electrical charges.

In an indirect exciton, free electrons in one 2D sheet can be electrostatically bound to holes that are free to travel in the neighbouring 2D sheet.

Because the electrons and holes are each confined to their own 2D sheets, they cannot recombine, but they can electrically bind together if the two 2D sheets are very close (a few nanometres).

If electrons in the top (‘drive’) sheet are accelerated by an applied voltage, then each partnering hole in the lower (‘drag’) sheet can be ‘dragged’ by its electron.

This ‘drag’ on the hole can be measured as an induced voltage across the drag sheet, and is referred to as Coulomb drag.

A goal in such a mechanism is for the exciton to remain bound, and to travel as a superfluid, a quantum state with zero viscosity, and thus without wasted dissipation of energy.

To achieve this superfluid state, precisely engineered 2D materials must be kept only a few nanometres apart, such that the bound electron and hole are much closer to each other than they are to their neighbours in the same sheet.

In the device studied, a sheet of hexagonal-boron-nitride (hBN) separates two sheets of atomically-thin (2D) bilayer graphene, with the insulating hBN preventing recombination of electrons and holes.

Passing a current through one sheet and measuring the drag signal in the other sheet allows experimenters to measure the interactions between electrons in one sheet and holes in the other, and to ultimately detect a clear signature of superfluid formation.

Only recently, new, 2D heterostructures with sufficiently thin insulating barriers have been developed that allow us to observe features brought by strong electron-hole interactions.

Explaining the inexplicable: negative drag

However, experiments published in 2016 showed extremely puzzling results. Under certain experimental conditions, the Coulomb drag was found to be negative – i.e. moving an electron in one direction caused the hole in the other sheet to move in the opposite direction!

These results could not be explained by existing theories.

In this new study, these puzzling results are explained using crucial multi-band processes that had not previously been considered in theoretical models.

Previous experimental studies of Coulomb drag had been performed in conventional semiconductor systems, which have much larger bandgaps.

However bilayer graphene has a very small bandgap, and it can be changed by the perpendicular electric fields from the metal gates positioned above and below the sample.

The calculation of transport in both conduction and valence bands in each of the graphene bilayers was the ‘missing link’ that marries theory to experimental results. The strange negative drag happens when the thermal energy approaches the bandgap energy.

The strong multiband effects also affect the formation of exciton superfluids in bilayer graphene, so this work opens up new possibilities for exploration in exciton superfluids.

The study Multiband Mechanism for the Sign Reversal of Coulomb Drag Observed in Double Bilayer Graphene Heterostructures by M. Zarenia, A.R. Hamilton, F.M. Peeters and D. Neilson was published in Physical Review Letters in July 2018.

Acknowledgement: The study was led by David Neilson, and by Mohammad Zarenia while at the University of Antwerp, Belgium. The authors of the theoretical study worked with data provided by experimentalists from the two US groups: Cory Dean (Columbia University) and Emanuel Tutuc (University of Texas at Austin) who discovered the original puzzling results. The research was supported by the Flemish government (Belgium), the University of New South Wales, the University of Camerino and by the Australian Research Council via FLEET.

Superfluids and FLEET

Exciton superfluids are studied within FLEET’s Research theme 2 for their potential to carry zero-dissipation electronic current, and thus allow the design of ultra-low energy exciton transistors.

The use of twin atomically-thin (2D) sheets to carry the excitons will allow for room-temperature superfluid flow, which is key if the new technology is to become a viable ‘beyond CMOS’ technology. A bilayer-exciton transistor would be a dissipationless switch for information processing.

In a superfluid, scattering is prohibited by quantum statistics, which means that electrons and holes can flow without resistance.

In this single, pure quantum state, all particles flow with the same momentum, so that no energy can be lost through dissipation.

FLEET (the Australian Research Council Centre of Excellence in Future Low-Energy Electronics Technologies) brings together over a hundred Australian and international experts, with the shared mission to develop a new generation of ultra-low energy electronics.

The impetus behind such work is the increasing challenge of energy used in computation, which uses 5-8% of global electricity and is doubling every decade.

A key challenge of such ultra-miniature devices is overheating – their ultra-small surfaces seriously limit the ways for the heat from electrical currents to escape.

Working to address “hotspots” in computer chips that degrade their performance, UCLA engineers have developed a new semiconductor material, defect-free boron arsenide, that is more effective at drawing and dissipating waste heat than any other known semiconductor or metal materials.

This could potentially revolutionize thermal management designs for computer processors and other electronics, or for light-based devices like LEDs.

Illustration showing a schematic of a computer chip with a hotspot (bottom); an electron microscope image of defect-free boron arsenide (middle); and an image showing electron diffraction patterns in boron arsenide. Credit: Hu Research Lab / UCLA Samueli

The study was recently published in Science and was led by Yongjie Hu, UCLA assistant professor of mechanical and aerospace engineering.

Computer processors have continued to shrink down to nanometer sizes where today there can be billions of transistors on a single chip. This phenomenon is described under Moore’s Law, which predicts that the number of transistors on a chip will double about every two years. Each smaller generation of chips helps make computers faster, more powerful and able to do more work. But doing more work also means they’re generating more heat.

Managing heat in electronics has increasingly become one of the biggest challenges in optimizing performance. High heat is an issue for two reasons. First, as transistors shrink in size, more heat is generated within the same footprint. This high heat slows down processor speeds, in particular at “hotspots” on chips where heat concentrates and temperatures soar. Second, a lot of energy is used to keep those processors cool. If CPUs did not get as hot in the first place, then they could work faster and much less energy would be needed to keep them cool.

The UCLA study was the culmination of several years of research by Hu and his students that included designing and making the materials, predictive modeling, and precision measurements of temperatures.

The defect-free boron arsenide, which was made for the first time by the UCLA team, has a record-high thermal conductivity, more than three-times faster at conducting heat than currently used materials, such as silicon carbide and copper, so that heat that would otherwise concentrate in hotspots is quickly flushed away.

“This material could help greatly improve performance and reduce energy demand in all kinds of electronics, from small devices to the most advanced computer data center equipment,” Hu said. “It has excellent potential to be integrated into current manufacturing processes because of its semiconductor properties and the demonstrated capability to scale-up this technology. It could replace current state-of-the-art semiconductor materials for computers and revolutionize the electronics industry.”

The study’s other authors are UCLA graduate students in Hu’s research group: Joonsang Kang, Man Li, Huan Wu, and Huuduy Nguyen.

In addition to the impact for electronic and photonics devices, the study also revealed new fundamental insights into the physics of how heat flows through a material.

“This success exemplifies the power of combining experiments and theory in new materials discovery, and I believe this approach will continue to push the scientific frontiers in many areas, including energy, electronics, and photonics applications,” Hu said.

In its upcoming Mid-Year Update to The McClean Report 2018 (to be released at the end of July), IC Insights forecasts that the 2018 global electronic systems market will grow 5% to $1,622 billion while the worldwide semiconductor market is expected to surge by 14% this year to $509.1 billion, exceeding the $500.0 billion level for the first time.  If the 2018 forecasts come to fruition, the average semiconductor content in an electronic system will reach 31.4%, breaking the all-time record of 28.8% that was set in 2017 (Figure 1).

Figure 1

Historically, the driving force behind the higher average annual growth rate of the semiconductor industry as compared to the electronic systems market is the increasing value or content of semiconductors used in electronic systems.  With global unit shipments of cellphones (-1%), automobiles (3%), and PCs (-1%) forecast to be weak in 2018, the disparity between the moderate growth in the electronic systems market and high growth of the semiconductor market is directly due to the increasing content of semiconductors in electronic systems.

While the trend of increasing semiconductor content has been evident for the past 30 years, the big jump in the average semiconductor content in electronic systems in 2018 is expected to be primarily due to the huge surge in DRAM and NAND flash ASPs and average electronic system sales growth this year. After slipping to 30.2% in 2020, the semiconductor content percentage is expected to climb to a new high of 31.5% in 2022.  IC Insights does not anticipate the percentage will fall below 30% any year through the forecast period.

The trend of increasingly higher semiconductor value in electronic systems has a limit.  Extrapolating an annual increase in the percent semiconductor figure indefinitely would, at some point in the future, result in the semiconductor content of an electronic system reaching 100%.  Whatever the ultimate ceiling is, once it is reached, the average annual growth for the semiconductor industry will closely track that of the electronic systems market (i.e., about 4%-5% per year).

Texas Instruments Incorporated (TI) (NASDAQ: TXN) today announced the resignation of Brian Crutcher as president, CEO and a member of the TI board. The board has named Rich Templeton, the company’s chairman, to reassume the roles of president and CEO on an ongoing, indefinite basis, in addition to continuing as chairman. Templeton’s appointment is not temporary, and the board is not searching for a replacement.

Crutcher resigned due to violations of the company’s code of conduct.  The violations are related to personal behavior that is not consistent with our ethics and core values, but not related to company strategy, operations or financial reporting.

“For decades, our company’s core values and code of conduct have been foundational to how we operate and behave, and we have no tolerance for violations of our code of conduct,” said Mark Blinn, lead director of the TI Board. “Over the past 14 years, Rich has successfully led TI to become the company it is today, and we have great confidence in his values and ability to continue to lead this company forward.”

“I have tremendous pride in this company, and passion for continuing to make TI even stronger and better,” said Rich Templeton, TI chairman, president and CEO. “I remain dedicated to moving TI forward with an unwavering commitment to operate ethically and conduct ourselves professionally in everything we do.”

TI also reported second-quarter revenue of $4.02 billion, up 9 percent from the same quarter a year ago, and earnings per share of $1.40. EPS included a 3 cent discrete tax benefit not in the company’s original guidance. TI will provide full second-quarter results and third-quarter guidance in its earnings release and conference call on July 24.

Micron (Nasdaq:MU) and Intel today announced an update to their 3D XPoint™ joint development partnership, which has resulted in the development of an entirely new class of non-volatile memory with dramatically lower latency and exponentially greater endurance than NAND memory.

The companies have agreed to complete joint development for the second generation of 3D XPoint technology, which is expected to occur in the first half of 2019. Technology development beyond the second generation of 3D XPoint technology will be pursued independently by the two companies in order to optimize the technology for their respective product and business needs.

The two companies will continue to manufacture memory based on 3D XPoint technology at the Intel-Micron Flash Technologies (IMFT) facility in Lehi, Utah.

“Micron has a strong track record of innovation with 40 years of world-leading expertise in memory technology development, and we will continue driving the next generations of 3D XPoint technology,” said Scott DeBoer, executive vice president of Technology Development at Micron. “We are excited about the products that we are developing based on this advanced technology which will allow our customers to take advantage of unique memory and storage capabilities. By developing 3D XPoint technology independently, Micron can better optimize the technology for our product roadmap while maximizing the benefits for our customers and shareholders.”

“Intel has developed a leadership position delivering a broad portfolio of Optane products across client and data center markets with strong support from our customers,” said Rob Crooke, senior vice president and general manager of Non-Volatile Memory Solutions Group at Intel Corporation. “Intel Optane’s direct connection to the world’s most advanced computing platforms is achieving breakthrough results in IT and consumer applications. We intend to build on this momentum and extend our leadership with Optane, which combined with our high-density 3D NAND technology, offer the best solutions for today’s computing and storage needs.”

Silicon Labs (NASDAQ: SLAB), a provider of silicon, software and solutions for a smarter, more connected world, announces two new executive appointments. Daniel Cooley has been named Senior Vice President and Chief Strategy Officer. In this new role, Mr. Cooley will focus on Silicon Labs’ overall growth strategy, business development, new technologies and emerging markets. Matt Johnson, a semiconductor veteran with more than 15 years of industry experience, joins Silicon Labs as Senior Vice President and General Manager of IoT products. Both executives will report to Tyson Tuttle, CEO.

Mr. Cooley has led Silicon Labs’ IoT business for the past four years. Under his leadership, the company built an industry-leading portfolio of secure connectivity solutions, with IoT revenue now exceeding a $100 million per quarter run rate. Mr. Cooley joined Silicon Labs in 2005 as a chip design engineer developing broadcast audio products and short-range wireless devices. Over the years, he has served in various senior management, engineering and product management roles at the company’s Shenzhen, Singapore, Oslo and Austin sites. The new role leverages Mr. Cooley’s proven talents in strategy and business development.

Mr. Johnson will lead Silicon Labs’ IoT business including the development and market success of the company’s broad portfolio of wireless products, microcontrollers, sensors, development tools and wireless software. Mr. Johnson has a track record of growing revenue and leading large global teams, and he brings a deep understanding of analog, MCU and embedded software businesses to Silicon Labs. Previously, he served as Senior Vice President and General Manager of automotive processing products and software development at NXP Semiconductors/Freescale, as well as SVP and General Manager of mobile solutions at Fairchild Semiconductor.

“With these executive appointments, we are expanding our ability to execute on large and growing market opportunities in the IoT,” said Tyson Tuttle, CEO of Silicon Labs. “Together, these two talented leaders will help Silicon Labs scale the business to the next level and focus on future growth.”

Intel to acquire eASIC


July 16, 2018

The following is an opinion editorial provided by Dan McNamara of Intel Corporation.

Intel is competing to win in the largest-ever addressable market for silicon, which is being driven by the explosion of data and the need to process, analyze, store and share it. This dynamic is fueling demand for computing solutions of all kinds. Of course Intel is known for world-class CPUs, but today we offer a broader range of custom computing solutions to help customers tackle all kinds of workloads – in the cloud, over the network and at the edge. In recent years, Intel has expanded its products and introduced breakthrough innovations in memory, modems, purpose-built ASICs, vision processing units and field programmable gate arrays (FPGAs).

FPGAs are experiencing expanding adoption due to their versatility and real-time performance. These devices can be programmed anytime – even after equipment has been shipped to customers. FPGAs contain a mixture of logic, memory and digital signal processing blocks that can implement any desired function with extremely high throughput and very low latency. This makes FPGAs ideal for many critical cloud and edge applications, and Intel’s Programmable Solutions Group revenue has grown double digits as customers use FPGAs to accelerate artificial intelligence, among other applications.

Customers designing for high-performance, power-constrained applications in market segments like wireless, networking and the internet of things (IoT) sometimes begin deployments with FPGAs for fast time-to-market and flexibility. They then migrate to devices called structured ASICs, which can be used to optimize performance and power-efficiency. A structured ASIC is an intermediary technology between FPGAs and ASICs. It offers performance and power-efficiency closer to a standard-cell ASIC, but with the faster design time and at a fraction of the non-recurring engineering costs associated with ASICs.

Today, I’m excited to announce that Intel plans to expand its programmable solutions portfolio to include structured ASICs by acquiring eASIC®, a leading structured ASICs provider headquartered in Santa Clara, California. eASIC has a proven, 19-year success record, leading products and a world-class team, which will join Intel’s Programmable Solutions Group. The addition of eASIC will help us meet customers’ diverse needs of time-to-market, features, performance, cost, power and product life cycles.

This combination brings together the best-in-class technologies from both companies to provide customers with more choice, faster time-to-market and lower development costs. Specifically, having a structured ASICs offering will help us better address high-performance and power-constrained applications that we see many of our customers challenged with in market segments like 4G and 5G wireless, networking and IoT. We can also provide a low-cost, automated conversion process from FPGAs (including competing FPGAs) to structured ASICs.

Longer term, we see an opportunity to architect a new class of programmable chip that takes advantage of Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) technology to combine Intel FPGAs with structured ASICs in a system in package solution. Together with partners and customers, Intel and eASIC expect to deliver industry-leading solutions.

We expect to complete the acquisition in the third quarter of 2018 after customary closing conditions are met. We look forward to serving eASIC’s current customers and to offering Intel customers a new solution for unlocking the power of data.

Australian scientists have achieved a new milestone in their approach to creating a quantum computer chip in silicon, demonstrating the ability to tune the control frequency of a qubit by engineering its atomic configuration. The work has been published in Science Advances.

A team of researchers from the Centre of Excellence for Quantum Computation and Communication Technology (CQC2T) at UNSW Sydney have successfully implemented an atomic engineering strategy for individually addressing closely spaced spin qubits in silicon.

The frequency spectrum of an engineered molecule. The three peaks represent three different configurations of spins within the atomic nuclei, and the distance between the peaks depends on the exact distance between atoms forming the molecule. Credit: Dr. Sam Hile

The researchers built two qubits – one an engineered molecule consisting of two phosphorus atoms with a single electron, and the other a single phosphorus atom with a single electron – and placed them just 16 nanometres apart in a silicon chip.

By patterning a microwave antenna above the qubits with precision alignment, the qubits were exposed to frequencies of around 40GHz. The results showed that when changing the frequency of the signal used to control the electron spin, the single atom had a dramatically different control frequency compared to the electron spin in the molecule of two phosphorus atoms.

The UNSW researchers collaborated closely with experts at Purdue University, who used powerful computational tools to model the atomic interactions and understand how the position of the atoms impacted the control frequencies of each electron even by shifting the atoms by as little as one nanometre.

“Individually addressing each qubit when they are so close is challenging,” says UNSW Scientia Professor Michelle Simmons, Director CQC2T and co-author of the paper.

“The research confirms the ability to tune neighbouring qubits into resonance without impacting each other.”

Creating engineered phosphorus molecules with different separations between the atoms within the molecule allows for families of qubits with different control frequencies. Each molecule can be operated individually by selecting the frequency that controls its electron spin.

“We can tune into this or that molecule – a bit like tuning in to different radio stations,” says Sam Hile, lead co-author of the paper and Research Fellow at UNSW.

“It creates a built-in address which will provide significant benefits for building a silicon quantum computer.”

Tuning in and individually controlling qubits within a 2 qubit system is a precursor to demonstrating the entangled states that are necessary for a quantum computer to function and carry out complex calculations.

These results show how the team – led by Professor Simmons – have further built on their unique Australian approach of creating quantum bits from precisely positioned individual atoms in silicon.

By engineering the atomic placement of the atoms within the qubits in the silicon chip, the molecules can be created with different resonance frequencies. This means that controlling the spin of one qubit will not affect the spin of the neighbouring qubit, leading to fewer errors – an essential requirement for the development of a full-scale quantum computer.

“The ability to engineer the number of atoms within the qubits provides a way of selectively addressing one qubit from another, resulting in lower error rates even though they are so closely spaced,” says Professor Simmons.

“These results highlight the ongoing advantages of atomic qubits in silicon.”

This latest advance in spin control follows from the team’s recent research into controllable interactions between two qubits.