Category Archives: Semiconductors

Intel has won SEMI’s 2018 Award for the Americas. SEMI honored the celebrated chipmaker for pioneering process and integration breakthroughs that enabled the first high-volume Integrated Silicon Photonics Transceiver. The award was presented yesterday at SEMICON West 2018.

SEMI’s Americas Awards recognize technology developments with a major impact on the semiconductor industry and the world.

The Intel® Silicon Photonics 100G CWDM4 (Coarse Wavelength Division Multiplexing 4-lane) QSFP28 optical transceiver, a highly integrated optical connectivity solution, combines the power of optics and the scalability of silicon. The small form-factor, high-speed, low-power consumption 100G optical transceivers are used in optical interconnects for data communications applications, including large-scale cloud and data centers, and in Ethernet switch, router, and client telecommunications interfaces.

Dr. Thomas Liljeberg, senior director of R&D for Intel Silicon Photonics, accepted the award on behalf of Intel. Dr. Liljeberg is one of the technologists responsible for bringing Intel’s silicon photonics 100G transceivers to high-volume production.

“Every year SEMI honors key technological contributions and industry leadership through the SEMI Award,” said David Anderson, president, SEMI Americas. “Intel was instrumental in delivering technologies that will influence product design and system architecture for many years to come. Congratulations to Intel for this significant accomplishment.”

“The 2018 Award recognizes the enablement of high-volume manufacturing through technology leadership and collaboration with key vendors in the supply chain,” said Bill Bottoms, chairman of the SEMI Awards Advisory Committee. “Intel’s collaboration is a model for how the industry can accelerate innovation in the future.”

SEMI established the SEMI Award in 1979 to recognize outstanding technical achievement and meritorious contributions in the areas of Semiconductor Materials, Wafer Fabrication, Assembly and Packaging, Process Control, Test and Inspection, Robotics and Automation, Quality Enhancement, and Process Integration.

The SEMI Americas award is the highest honor conferred by the SEMI Americas region. It is open to individuals or teams from industry or academia whose specific accomplishments have a broad commercial impact and widespread technical significance for the entire semiconductor industry. Nominations are accepted from individuals of North American-based member companies of SEMI. For a list of past award recipients, visit www.semi.org/semiaward.

SEMI yesterday honored two industry leaders at SEMICON West 2018 for their outstanding accomplishments in developing Standards for the electronics and related industries. The SEMI Standards awards were announced at the SEMI International Standards reception.

The Technical Editor Award recognizes the efforts of a member to ensure the technical excellence of a committee’s Standards. This year’s recipient is Sean Larsen of Lam Research. Mr. Larsen has led the North America EHS Committee and multiple EHS task forces for over a decade. His knowledge of the Regulations, Procedure Manual, and Style Manual, combined with his vast experience in the industry, ensures that complex safety matters are explained in a clear, consistent manner, and ballot authors frequently rely on him for his technical skills in preparing ballots.

In addition to co-chairing the North America EHS Committee, Mr. Larsen is currently the co-leader of the SEMI S22 (Electrical Design) Revision TF, the SEMI S2 Non-Ionizing Radiation TF, the SEMI S2 Korean High Pressure Gas Safety TF, and the Control of Hazardous Energy TF.

The Corporate Device Member Award recognizes the participation of the user community and is presented to individuals from device manufacturers. This year’s recipient is Don Hadder of Intel. Mr. Hadder has been actively involved in the Standards Program for several years, and currently leads the Chemical Analytical Methods Task Force and chairs the North America Liquid Chemicals Committee. He has successfully re-energized the committee, which is now focused on enabling continued process control improvements for advanced nodes. He recently drove the development of a critical new standard: SEMI C96, Test Method for Determining Density of Chemical Mechanical Polish Slurries, the first document in a series of SEMI Standards that will be devoted specifically to CMP slurry users, IDMs, slurry suppliers, metrology manufacturers and OEM equipment suppliers.

Mr. Hadder has worked at Intel for 23 years, where his experience and system ownership has been in Diffusion, Wet Etch, Planar-CMP, Ultra-Pure Water, Waste Treatment Systems, Abatement and Vacuum Systems, Bulk and Specialty Gas, Bulk Chemical Delivery and Planar Chemical Delivery.

BY PAUL VAN DER HEIDE, director of materials and components analysis, imec, Leuven, Belgium

To keep up with Moore’s Law, the semiconductor industry continues to push the envelope in developing new device architectures containing novel materials. This in turn pushes the need for new solid-state analytical capabilities, whether for materials characterization or inline metrology. Aside from basic R&D, these capabilities are established at critical points of the semiconductor device manufacturing line, to measure, for example, the thickness and composition of a thin film, dopant profiles of transistor’s source/drain regions, the nature of defects on a wafer’s surface, etc. This approach is used to reduce “time to data”. We cannot wait until the end of the manufacturing line to know if a device will be functional or not. Every process step costs money and a fully functional device can take months to fabricate. Recent advances in instrumentation and computational power have opened the door to many new, exciting analytical possibilities.

One example that comes to mind concerns the development of coherent sources. So far, coherent photon sources have been used for probing the atomic and electronic structure of materials, but only within large, dedicated synchrotron radiation facilities. Through recent developments, table top coherent photon sources have been introduced that could soon see demand in the semiconductor lab/fab environment.

The increased computational power now at our finger tips is also allowing us to make the most of these and other sources through imaging techniques such as ptychography. Ptychog- raphy allows for the complex patterns resulting from coherent electron or photon interaction with a sample to be processed into recognizable images to a resolution close to the sources wavelength without the requirement of lenses (lenses tend to introduce aberrations). Potential application areas extend from non-destructive imaging of surface and subsurface structures, to probing chemical reactions at sub femto-second timescales.

Detector developments are also benefiting many analytical techniques presently used. As an example, transmission electron microscopy (TEM) and scanning transmission electron microscopy (STEM) can now image, with atomic resolution, heavy as well as light elements. Combining this with increased computational power, allows for further devel- opment of imaging approaches such as tomography, holography, ptychography, differential phase contrast imaging, etc. All of which allow TEM/STEM to not only look at atoms in e.g. 2D materials such as MoS2 in far greater detail, but also opens the possibility to map electric fields and magnetic domains to unprecedented resolution.

The semiconductor industry is evolving at a very rapid pace. Since the beginning of the 21st century, we have seen numerous disruptive technologies emerge; technologies that need to serve is an increasingly fragmented applications space. It’s no longer solely about ‘the central processing unit (CPU)’. Other applications ranging from the internet of things, autonomous vehicles, wearable human-electronics interface, etc., are being pursued, each coming with unique requirements and analytical needs.

Looking ten to fifteen years ahead, we will witness a different landscape. Although I’m sure that existing techniques such as TEM/STEM will still be heavily used – probably more so than we realize now (we are already seeing TEM/STEM being extended into the fab). We will also see developments that will push the boundaries of what is possible. This would range from the increased use of hybrid metrology (combining results from multiple different analytical techniques and process steps) to the development of new innovative approaches.

To illustrate the latter, I take the example of secondary ion mass spectrometry (SIMS). With SIMS, an energetic ion beam is directed at the solid sample of interest, causing atoms in the near surface region to leave this surface. A small percentage of them are ionized, and pass through a mass spectrometer which separates the ions from one another according to their mass to charge ratio. When this is done in the dynamic-SIMS mode, a depth profile of the sample’s composition can be derived. Today, with this technique, we can’t focus the incoming energetic ion beam into a confined volume, i.e. onto a spot that approaches the size of a transistor. But at imec, novel concepts were intro- duced, resulting in what are called 1.5D SIMS and self-focusing SIMS (SF-SIMS). These approaches are based on the detection of constituents within repeatable array structures, giving averaged and statistically significant information. This way, the spatial resolution limit of SIMS was overcome.

And there are exciting developments occurring here at imec in other analytical fields such as atom probe tomography (APT), photoelectron spectroscopy (PES), Raman spectroscopy, Rutherford back scattering (RBS), scanning probe microscopy (SPM), etc. One important milestone has been the development of Fast Fourier Transform-SSRM (FFT-SSRM) at imec. This allows one to measure carrier distributions in FinFETs to unparalleled sensitivity.

Yet, probably the biggest challenge materials characterization and inline metrology face over the next ten to fifteen years will be how to keep costs down. Today, we make use of highly specialized techniques developed on mutually exclusive and costly platforms. But why not make use of micro-electro-mechanical systems (MEMS) that could simultaneously perform analysis in a highly parallel fashion, and perhaps even in situ? One can imagine scenarios in which an army of such units could scan an entire wafer in the fraction of the time it takes now, or alternatively, the incorporation of such units into wafer test structure regions.

BY DEBRA VOGLER, SEMI, Milpitas, CA

With chipmakers looking toward 5nm manufacturing, it’s clear that traditional scaling is not dead but continuing in combination with other technologies. The industry sees scaling enabled by 3D architectures such as die stacking and the stacking of very small geometry wafers. Interconnect scaling also comes into play. This year’s Scaling Technologies TechXPOT at SEMICON West (Scaling Every Which Way! – Thursday, July 12, 2:00PM-4:00PM) will provide an update on the evolution of scaling and describe how the various players (foundry, IDM, fabless, and application developers) are jockeying for innovation leadership. As a prelude to the event, SEMI asked speakers to provide insights on important scaling trends. For a full list of speakers and program agenda, visit http://www.semiconwest.org/programs-catalog/scaling-every-which-way.

Challenges for gate-all-around (GAA) and FinFET devices

Common performance boosters for gate-all-around (GAA) FETs and FinFETs include lower access resistance, lower parasitic capacitance, and stress. “However, one specific performance booster that only applies to GAA is the reduction of the spacing between the vertical wires or sheets,” says Diederik Verkest, imec distinguished member of technical staff, Semiconductor Technology and Systems.

“This reduces parasitic capacitance without affecting drive current and hence benefits both performance and power.” He further notes that imec demonstrated the first stacked gate-all-around (GAA) devices in scaled nodes. “In fact, we are the only ones that published working circuits – ring oscillators in a scaled node using industry-standard processes – in our case replacement metal gate (RMG), and embedded in situ doped source/drain (S/D) epitaxy.”

“There are two elements of the stacked GAA architecture that need to be addressed,” says Verkest. “The first is that this architecture uses epitaxially-grown layers of Si and SiGe to define the device channel. The use of grown materials for the channel and the lattice mismatch between the two materials represent a departure from the traditional fabrication of CMOS devices, so the industry needs to develop and gain confidence in novel metrology that allows for good control of the layers and also proves their low defectivity.” The second aspect is the three-dimensional nature of the GAA devices. “During the processing of these devices, we have ‘non-line-of-sight’ hidden features that are difficult to control and characterize and may also lead to new defect mechanisms that would impact yield, and possibly product reliability.”

Huiming Bu, director, Advanced Logic/Memory Research – Integration and Device, IBM Research, Semiconductor Group, says that naming of technology nodes has been used extensively for marketing strategies in “foundry land,” but the designations have lost much of their meaning as technology scaling differentiators. “That said, when it comes to technology innovation and value proposition, IBM, in conjunction with Samsung and GLOBALFOUNDRIES, has developed the GAA NanoSheet transistor for 5nm to provide a full technology node scaling benefit in density, power and performance,” says Bu (FIGURE 1). The key parameters for intrinsic device optimization when scaling to the 3nm node, explains Bu, are the NanoSheet width for better electrostatic characteristics, and the number of sheets for increased current density. Also necessary are strain engineering for carrier transport enhancement, and interconnect innovations for parasitic RC reduction.

“Beyond that, the industry needs to look into something different, something more disruptive.”

Materials challenges

Materials challenges are also a concern as the industry moves to 5nm and below. “We see increasing complexity in the material systems that are being used,” explains Verkest. One example he cites in scaled FinFET or GAA technologies is the use of two to three layers of different materials–typically metals such as TiN – to which small amounts of other elements are added to set device characteristics such as the threshold voltage. “At the same time, the requirements for the thickness of these materials, driven by gate dimensions for example, or the distance between the wires, are increasingly challenging.” Other examples of materials challenges are the use of two to three different types of insulators in the middle-of-the- line, each with different etch contrasts. “We use novel materials such as carbon containing oxides or oxynitrides that have lower dielectric constants in order to boost the performance of circuits,” he says, noting that the materials list “is quite long.”

Several critical dimensions in transistors at advanced technology nodes have already reached a few monolayers of atoms, fueling expectations for innovation at the material level for transistor scaling, Bu notes. “The other argument is that there is a growing gap between computing demand and the slowdown of technology advancement driven by conventional scaling,” says Bu. One trend that addresses this gap is integrating more computing functions that make the technology solution more modular, which naturally leads to the incorporation of more materials for more applications. Bu cautions, however, that intro- ducing new materials in semiconductor technology has never been easy. “It takes many years of R&D to reach this implementation point, if it ever happens. So, do we need new materials when the industry moves to 5nm and 3nm? Yes, though I expect new material implementation to be a lot faster in interconnect and packaging at these nodes rather than intrinsic to the transistor.”

Challenges in developing atomic-level processes

There will be challenges in developing atomic-level processes used in scaling, such as atomic layer depositions (ALD) and atomic layer etches, notes Verkest. “These classes of processes are both required to handle the scaled dimensions at the 5nm and 3nm nodes, and also the 3D nature of the scaled technologies – and here we are talking about logic and memories,” Verkest says. “With respect to depositions, we would need to develop thermal ALD processes (not plasma-based) that enable accurate and conformal depositions in non-line-of-sight structures.”

Adhesion and wetting, smoothness, and throughput would also need to be addressed. “Longer term, these processes need to facilitate selectivity and self-alignment to address gap-fill challenges in highly scaled structures,” he says. Other concerns he notes with respect to atomic layer etches are selectivity to various materials, and fidelity requirements that increase the requirements for metrology accuracy. “Throughput is also a concern.”

Bu believes that a new device architecture beyond FinFET is required to provide a full technology node scaling benefit (i.e., density, power and performance) at 5nm and 3nm.
“Beyond 3nm, we may need to continue the transistor scaling in the vertical direction and start to stack them together,” Bu says. He also cites the need for parasitic R/C reduction in the interconnect to take advantage of the intrinsic transistor benefit at the circuit and chip levels. “We see a lot of opportunity in atomic-level processes, especially in atomic layer etch and selective material deposition, to address these challenges in the transistor and the interconnect.”

Multi-Trigger chemistry, which is designed specifically for EUV, creates a high- chemical gradient at pattern boundaries, significantly reducing blurring and improving line-edge roughness to reduce the RLS trade off.

BY DAVID URE, ALEXANDRA MCCLELLAND and ALEX ROBINSON, Irresistible Materials, Wellesley, MA and Birmingham, U.K.

The semiconductor industry has invested billions of dollars to develop extreme ultraviolet (EUV) lithography and high-volume deployment of the technology is imminent. However, EUV lithography is not yet a complete solution. Most notably, new photoresist materials that enable the full benefits of EUV have yet to be developed.

While incremental modifications of incumbent ‘chemically amplified resists’ will be used for the planned initial EUV introduction in 2019, there are presently no clear solutions that address the industry feature size targets, defectivity requirements, and sensitivity needs for 2020 and onwards. This is a significant concern and continues to cast a shadow over the industry’s long anticipated switch to EUV lithography. Indeed, the lack of a suitable resist for EUV lithography is now one of the biggest problems faced by the semiconductor industry.

What makes a good resist?

The critical performance parameters for any successful resist are: 1) Resolution (R): How narrow the lines on a microchip are, 2) Line-edge roughness LER (L): How ‘wobbly’ the lines are; and 3) Sensitivity (S): How small a dose of radiation is required (how quickly the pattern can be formed). These performance metrics are known as the RLS targets, and they are set out in the ITRS. For a given material, these metrics have a conflicting relationship (one can only be improved at the cost of another): The ‘RLS tradeoff’. For a given material, improving one or two of the metrics leads to a loss in the third. To improve the RLS tradeoff, it is necessary to move to a new RLS graph. This can only be done by changing the resist material as illustrated in FIGURE 1.

In addition to the primary RLS targets, there are a series of critical secondary peformance metrics a commercially successful resist system needs to address, including the ability to pattern with extraordinarily low level of defects, high durability in the post processing steps, ultra-low contamination levels and wide process latitude.

The limitations with current state-of-art resist technology

Existing state-of-the-art photoresists are polymer- based platforms known as Chemically Amplified Resists (or CARs). The original CAR was based on a poly(hydroxystryene) chain with acid-labile tBOC protecting groups on the phenols, mixed with a photoacid generator. The photoacid released upon light exposure diffused through the polymer matrix catalytically removing the protecting groups, leading to a strong change in the solubility. While modern chemically amplified resists have increased in complexity, often using proprietary co-polymers with multiple functional units to address etch durability, adhesion and other properties, the core mechanisms of patterning have remained the same as the original CAR technology.

Such materials have demostrated significant design flexibility to address the evolving needs of the lithog- raphy industry. However, as feature sizes have continued to shrink, the diffuse nature of the acid – required for high senstitivity – has hampered resolution, and the acid quenchers, added to address this, have driven defects and roughness up. These limitations have risen to the fore as the industry prepares for the introduction of EUV lithography and the targeted feature sizes are increas- ingly incompatible with CAR technology.

Solving the EUV resist problem?

Given the limitations of polymer-platform photoresists originally developed for 193nm lithography, as the industry prepares for EUV introduction, the approach to photoresist development is being challenged. Indeed, device manufacturers and scanner suppliers have urged the photoresist suppliers to consider novel approaches to design photoresist systems specifically to meet the needs of EUV lithography.

One of the new photoresist platforms that has risen to prominence has been given the name ‘molecular resist’ because it represents a departure from polymer- based photoresists to formulations based around ‘small molecules.’ Originally developed to reduce the chemical ‘pixel’ size of the resist, this platform has demonstrated promise in reducing line-edge roughness, but until recently has not fulfilled its early promise in EUV.

Another novel approach has been the development of metal-oxide resist platforms. These have demonstrated a compelling combination of high resolution, and low-line edge roughness, and sensitivities have improved recently. However, like other contenders, these materials currently demonstrate high defects and face a hurdle due to concerns over the use of metals in a cleanroom environment.

Another leading new ‘EUV specific’ resist system is being developed by Irresistible Materials Ltd (IM), a company headquartered in Birmingham, England. IM has developed a new approach to achieve high-resolution, high sensitivity, and a low LER resist called the Multi-Trigger Resist platform(MTR). MTRs comprise a small proprietary resin molecule; an MTR process compatible cross-linker; and (like a chemically amplified resist) a photo-acid generator (PAG). However, the novel Multi-Trigger chemistry creates a high-chemical gradient at pattern boundaries, significantly reducing blurring and improving line-edge roughness to reduce the RLS trade off (FIGURE 2).

In a Multi-Trigger material, resist exposure proceeds via a catalytic process in a similar manner to a chemically amplified resist. However, instead of a single photoacid causing a single deprotection event and then being regen- erated, the Multi-Trigger resist uses multiple photoacids to activate multiple acid sensitive molecules, which then react with each other to cause a single resist event while also regenerating the photoacids. Importantly, it is only when two complimentary activated molecules react with each other that the resist is exposed – a single activated molecule, which is not near another will quench the acid, and remain unexposed.

In areas with a high number of activated photoacids (higher dose areas, for instance at the centre of a pattern feature), resist components are activated in close proximity and the multi-step resist exposure reaction proceeds, ending with photoacids regeneration and thus further reactions, ensuring high sensitivity. In areas with only a low number of activated photoacids (lower dose areas, for instance at the edge of a pattern feature), the activated resist components are too widely separated to react and the photoacids are thus removed, stopping the catalytic chain. The Multi- Trigger resist creates an increase in the chemical gradient at the edge of patterned features and reduces undesirable acid diffusion out of the patterned area. FIGURE 3 and 4 illustrate how the Multi-Trigger approach departs from the traditional approach used in existing state-of-the-art resist systems (CARs).

How good is the MTR system and where is it in its development cycle?

The MTR system is presently in an advanced development phase. Results have already shown this system can match and exceed the performance capabilities of state-of-the- art CARs. Furthermore, the specific formulation of the MTR system can be tailored by changing the ratio of the components within the resist. To date, IM has demonstrated that the sensitivity of the resist can be varied from 12 mJ/cm2 to over 50 mJ/cm2, with the patterned resolution ranging from 20nm half pitch to under 16nm half pitch respectively, to meet varying lithographic requirements.

Some example data from the ASML NXE 3300 scanner at IMEC in Belgium is included for reference below. ASML’s NXE platform is the industry’s first production platform for extreme ultraviolet lithography (EUVL), using 13.5 nm EUV light, generated by a tin-based plasma source.

FIGURE 5 shows results for 20nm half-pitch lines patterned on a pitch of 40nm. At a dose of 44.5 mJ/cm2, the LER is 2.6nm. FIGURE 6 shows 16nm half-pitch lines patterned on a pitch of 32nm. At a dose of 38.5 mJ/cm2, the LER is 3.7nm (unbiased values). These LER values compare very favorably with existing state-of-the-art CAR resists modified for EUV lithography. Importantly, the MTR technology is at the very beginning of its optimization cycle, with significant further performance enhancements expected as the technology matures. To this end, IM is in the process of scaling operations to accelerate the optimization of the MTR system in preparation for commercial launch.

The roadmap to commercial readiness

Prior to commercial integration into a Fab, it is also critical to address the ‘secondary’ performance metrics previously discussed. It is these tests that often prove a stumbling block to progressing from a promising new material. For an SME such as Irresistible Materials, passing this testing is a challenge as often new infrastructure and a specialist, custom tool set is required to pass stringent tests such as contamination. A resist that meets all lithography criteria could still fail to be adopted if, for example, the solubility of the components has not be synthesised with the required solubility in common fabrication solvents which will be present in the waste system.

For IM’s MTR, a precipitation test using waste drain solvents passed the precipitation test with no precipitate optically visible. These results indicate that the IM resist can be used within a fabrication facility with no precipitation issues. The resist also passes outgassing requirements so that it does not contaminate the lithog- raphy tool. Furthermore, because the resist is not metal based, there are no inherent track contamination issues. Metallic ion migration is a key concern for advanced device manufacturers and IM has implemented several protocols to address metal ion related concerns — the current contaminant metal levels are below 15ppb for each individual metal and will reduce further as production system are optimized.

Another major step in the commercialization roadmap is the ability to produce material in a quality controlled, high-volume manufacturing process at commercially competitive costs. To address this requirement, IM has established a partnership with Nano-C for the high- volume supply of IM’s proprietary resin molecule. Nano-C, Inc. is a leading supplier of specialist small molecules and has recently doubled the footprint at its Massachusetts site as preparations are made to scale production of the IM materials.

Looking towards the future

IM is targeting launch of its initial MTR products in 2020 (to address the industry N5 node),and is presently engaged in a variety of tests/trials with potential end-user and distribution partners as the resist system is optimized, scaled and readied for commercial release. However, IM also recognizes the potential of this resist system to go beyond N5 and has a clear pathway for addressing future industry nodes, to N3 and potentially beyond. Notable upgrade pathways from the gen 1 MTR include optimizing the metastable nature of the proton quenching, increasing opacity, reducing the number of components in the resist to reduce the impact of stochastics, and optimizing the ancillary process.

BY PETE SINGER

There’s an old proverb that the shoemaker’s children always go barefoot, indicating how some professionals don’t apply their skills for themselves. Until lately, that has seemed the case with the semiconductor manufacturing industry which has been good at collecting massive amounts of data, but no so good at analyzing that data and using it to improve efficiency, boost yield and reduce costs. In short, the industry could be making better use of the technology it has developed.

That’s now changing, thanks to a worldwide focus on Industry 4.0–more commonly known as “smart manufacturing” in the U.S. – which represents a new approach to automation and data exchange in manufacturing technologies. It includes cyber-physical systems, the Internet of things, cloud computing, cognitive computing and the use of artificial intelligence/deep learning.

At SEMICON West this year, these trends will be showcased in a new Smart Manufacturing Pavilion where you’ll be able to see – and experience – data-sharing breakthroughs that are creating smarter manufacturing processes, increasing yields and profits, and spurring innovation across the industry. Each machine along the Pavilion’s multi-step line is displayed, virtually or with actual equipment on the floor – from design and materials through front-end patterning, to packaging and test to final board and system assembly.

In preparation for the show, I had the opportunity to talk to Mike Plisinski, CEO of Rudolph Technologies, the sponsor of the Smart Pavilion about smart manufacturing. He said in the past “the industry got very good at collecting a lot of data. We sensors on all kinds of tools and equipment and we’d track it with the idea of being able to do predictive maintenance or predictive analytics. That I think had minimal success,” he said.

What’s different now? “With the industry consolidating and the supply chains and products getting more complex that’s created the need to go beyond what existed. What was inhibiting that in the past was really the ability to align this huge volume of data,” he said. The next evolution is driven by the need to improve the processes. “As we’ve gone down into sub-20 nanometer, the interactions between the process steps are more complex, there’s more interaction, so understanding that interaction requires aligning digital threads and data streams.” If a process chamber changed temperature by 0.1°C, for example, what impact did it have on lithography process by x, y, z CD control. That’s the level of detail that’s required.

“That has been a significant challenge and that’s one of the areas that we’ve focused on over the last four, five years — to provide that kind of data alignment across the systems,” Plisinski said.

Every company is different, of course, and some have been managing this more effectively than others, but the cobbler’s children are finally getting new shoes.

By Pete Singer

Increasingly complicated 3D structures such finFETs and 3D NAND require very high aspect ratio etches. This, in turn, calls for higher gas flow rates to improve selectivity and profile control. Higher gas flow rates also mean higher etch rates, which help throughput, and  higher rates of removal for etch byproducts.

“Gas flow rates are now approaching the limit of the turbopump,” said Dawn Stephenson, Business Development Manager – Chamber Solutions at Edwards Vacuum. “No longer is it only the process pressure that’s defining the size of the turbopump, it’s now also about how much gas you can put through the turbopump.”

Turbopumps operate by spinning rotors at very high rates of speed (Figure 1). These rotors propel gases and process byproducts down and out of the pump. The rotors are magnetically levitated (maglev) to reduce friction and increase rotor speed.

Figure 1. Spinning rotors propel gases and process byproducts out of the pump.

The challenge starts with processes that have high gas flow rates, over a thousand sccm, and lower chamber pressures, below 100 mTorr.  Such processes include chamber clean steps where high flows of oxygen-containing gases are used to remove and flush the process byproducts from inside the chamber, through Silicon via (TSV) in which SF6is widely used at high gas flowrates for deep silicon reactive ion etch (RIE) and more recently, gaseous chemical oxide removal (COR) which typically uses HF and NH3to remove oxide hard masks.

However, the challenge is intensified with the more general trend to higher aspect ratio etch across all technologies.

Stephenson said the maximum amount of gas you can put through a maglev turbo is determined by two things: the motor power and the rotor temperature. Both of these are affected adversely by the molecular weight of the gas. “The heavier the molecule, the lower the limit. For motor power, if the gas flow rate is increased, the load on the rotor is increased, and then you need more power. Eventually you reach a gas flow at which you exceed the amount of power you have to keep the rotor spinning and it will slow down,” she said.

The rotor temperature is an even bigger limiting factor. “As gas flow rates increase, the number of molecules hitting the rotor are increased. The amount of energy transferred into the rotors is also increased which elevates the temperature of the rotor. Because the rotor is suspended in a vacuum and because it’s levitated, it’s not very easy to remove that heat from the rotor because its primary thermal transfer is through radiation,” she explained.

Pumping heavier gases, particularly ones that have poor thermal conductivity, cause the rotor temperature to rise, leading to what is known as “rotor creep.”Rotor creep is material growth due to high temperature and centrifugal force (stress).  Rotor creep deformation over time narrows clearances between rotor and stator and can eventually lead to contact and catastrophic failure (Figure 2).

Figure 2. Edwards pumps have the highest benchmark for rotor creep life temperature in the industry, due to the use of a premium aluminum alloy as the base material for its mag-lev rotors, combined with a low stress design.

Where it gets even worse are in applications where the turbopump is externally heated to reduce byproduct deposition inside the pump. Such a heated pump will have a higher baseline rotor temperature and significantly lower allowable gas flowrates than an unheated one. This becomes a challenge particularly for the heated turbopumps on semiconductor etch and flat panel display processes using typical reactant gases such as HBr and SF6.  “Those are very heavy gases with low thermal conductivity and the maximum limit of the turbopump is actually quite low,” Stephenson said.

The good news is that Edwards has been diligently working to overcome these challenges. “What we have done to maximize the amount of gas you can put into our turbopumps is to  ensure our rotors can withstand the highest possible temperature design limit for a 10 year creep lifetime.   We use a premium alloy for the base rotor material and then beyond that we have done a lot of work with our proprietary modeling techniques to design a very low stress rotor because the creep is due to two factors: the temperature and the centrifugal stress. Because of those two things combined, we’re able to achieve the highest benchmark for rotor creep life temperature in the industry,” she said.

Furthermore, the company has worked on thermal optimization of the turbopump platform. “That means putting in thermal isolation where needed to try to help keep the rotor and motor cool. At the same time, we also need to keep the gas path hot to stop byproducts from depositing. We have also released a high emissivity rotor coating that helps keep the rotor cool,” Stephenson said. A corrosion resistant, black ceramic rotor coating is used to maximize heat radiation, which helps keep the rotor cool and gives more headroom on gas flowrate before the creep life temperature is reached.

Edwards has also developed a unique real-time rotor temperature sensor: Direct, dynamic rotor temperature reporting eliminates over-conservative estimated max gas flow limits and allows pump operation at real maximum gas flow in real duty cycle while maintaining safety and lifetime reliability.

In summary, enabling higher flows at lower process pressures is becoming a critical capability for advanced Etch applications, and Edwards have addressed this need with several innovations, including optimized rotor design to minimize creep, high emissivity coating, and real time temperature monitoring.

By Dave Lammers

The semiconductor industry is collecting massive amounts of data from fab equipment and other sources. But is the trend toward using that data in a Smart Manufacturing or Industry 4.0 approach happening fast enough in what Mike Plisinski, CEO of Rudolph Technologies, calls a “very conservative” chip manufacturing sector?

“There are a lot of buzzwords being thrown around now, and much of it has existed for a long time with APC, FDC, and other existing capabilities. What was inhibiting the industry in the past was the ability to align this huge volume of data,” Plisinskisaid.

While the industry became successful at adding sensors to tools and collecting data, the ability to track that data and make use of it in predictive maintenance or other analytics thus far “has had minimal success,” he said. With fab processes and manufacturing supply chains getting more complex, customers are trying to figure out how to move beyond implementing statistical process control (SPC) on data streams.

What is the next step? Plisinski said now that individual processes are well understood, the next phase is data alignment across the fab’s systems. As control of leading-edge processes becomes more challenging, customers realize that the interactions between the process steps must be understood more deeply.

“Understanding these interactions requires aligning these digital threads and data streams. When a customer understands that when a chamber changes temperature by point one degrees Celsius, it impacts the critical dimensions of the lithography process by X, Y, and Z. Understanding those interactions has been a significant challenge and is an area that we have focused on from a variety of angles over the last five years,” Plisinski said.

Rudolph engineers have worked to integrate multiple data threads (see Figure), aligning various forms of data into one database for analysis by Rudolph’s Yield Management System (YMS). “For a number of years we’ve been able to align data. The limitation was in the database: the data storage, the speed of retrieval and analysis were limitations. Recently new types of databases have come out, so that instead of relational, columnar-type databases, the new databases have been perfect for factory data analysis, for streaming data. That’s been a huge enabler for the industry,” he said.

Rudolph engineers have worked to integrate multiple data threads into one database.

Leveraging AI’s capabilities

A decade ago, Rudolph launched an early neural-network based system designed to help customers optimize yields. The software analyzed data from across a fab to learn from variations in the data.

“The problem back then was that neural networks of this kind used non-linear math that was too new for our conservative industry, an industry accustomed to first principle analytics. As artificial intelligence has been used in other industries, AI is becoming more accepted worldwide, and our industry is also looking at ways to leverage some of the capabilities of artificial intelligence,” he said.

Collecting and making use of data with a fab is “no small feat,” Plisinskisaid, but that leads to sharing and aligning data across the value chain: the wafer fab, packaging and assembly, and others.

“To gain increased insights from the data streams or digital threads, to bring these threads all together and make sense of all of it. It is what I call weaving a fabric of knowledge: taking individual data threads, bringing them together, and weaving a much clearer picture of what’s going on.”

Security concerns run deep

One of the biggest challenges is how to securely transfer data between the different factories that make up the supply chain. “Even if they are owned by one entity, transferring that large volume of data, even if it’s over a private dedicated network, is a big challenge. If you start to pick and choose to summarize the data, you are losing some of the benefit. Finding that balance is important.”

The semiconductor industry is gaining insights from companies analyzing, for instance, streaming video. The network infrastructures, compression algorithms, transfers of information from mobile wireless devices, and other technologies are making it easier to connect semiconductor fabs.

“Security is perhaps the biggest challenge. It’s a mental challenge as much as a technical one, and by that I mean there is more than reluctance, there’s a fundamental disdain for letting the data out of a factory, for even letting data into the factory,” he said.

Within fabs, there is a tug of war between equipment vendors which want to own the data and provide value-add services, and customers who argue that since they own the tools they own the data. The contentious debate grows more intense when vendors talk about taking data out of the fab. “That’s one of the challenges that the industry has to work on — the concerns around security and competitive information getting leaked out.” Developing a front-end process is “a multibillion dollar bet, and if that data leaks out it can be devastating to market-share leadership,” Plisinski said.

Early adopter stories

The challenge facing Rudolph and other companies is to convince their customers of the value of sharing data; that “the benefits will outweigh their concerns. Thus far, the proof of the benefit has been somewhat limited.”

“At least from a Rudolph perspective, we’ve had some early adopters that have seen some significant benefits. And I think as those stories get out there and as we start to highlight what some of these early adopters have seen, others at the executive level in these companies will start to question their teams about some of their assumptions and concerns. Eventually I think we’ll find a way forward. But right now that’s a significant challenge,”Plisinski said.

It is a classic chicken-and-egg problem, making it harder to get beyond theories to case-study benefits. “What helped us is that some of the early adopters had complete control of their entire value chain. They were fully integrated. And so we were able to get over the concerns about data sharing and focus on the technical challenges of transferring all that data and centralizing it in one place for analytical purposes. From there we got to see the benefits and document them in a way that we could share with others, while protecting IP.”

Aggregating data, buying databases and analytical software, building algorithms – all cost money, in most cases adding up to millions of dollars. But if yields improve by .25 or half a percent, the payback comes in six to eight months, he said.

“It’s a very conservative industry, an applied science type of industry. Trying to prove the value of software — a kind of black magic exercise — has always been difficult. But as the industry’s problems have become so complex, it is requiring these sophisticated software solutions.”

“We will have examples of successful case studies in our booth during SEMICON West. Anyone wanting further information is invited to stop by and talk to our experts,” adds Plisinski.

SEMI today announced the re-election of 10 current members to the SEMI International Board of Directors in accordance with the association’s by-laws.

The 10 board members were re-elected for two-year terms:

  • Martin Anstice, CEO, Lam Research Corporation
  • Kevin Crofton, president, SPTS Technologies, and corp. V.P., Orbotech
  • Jon D. Kemp, vice president, DuPont
  • Mitsunobu Koshiba, president and representative director, JSR Corporation
  • Yong Han Lee, chairman, Wonik
  • Sue Lin, vice chairman, Hermes Epitek
  • Tadahiro Suhara, president, SCREEN Semiconductor Solutions Co., Ltd.
  • Tetsuo Tsuneishi, executive chairman of the board and representative director, TEL
  • Tien Wu, management director and chief operating officer, ASE Group
  • Guoming Zhang, senior V.P. and chief strategy officer, NAURA Technology Group Co., Ltd.

The SEMI Executive Committee confirmed Tetsuo Tsuneishi, chairman of the board of TEL, as chairman of the SEMI Executive Committee. SEMI also confirmed Bertrand Loy, president and CEO of Entegris, as vice-chairman.

The leadership appointments and the elected board members’ tenure become effective at the annual SEMI membership meeting on July 11, during SEMICON West 2018 in San Francisco, California.

“The SEMI Board of Directors is comprised of global business leaders who represent SEMI members and the industry, ensuring that SEMI develops and delivers member value in all regions,” said SEMI president and CEO Ajit Manocha. “We congratulate the re-elected members and greatly appreciate all of our board members’ contributions to the industry.”

SEMI’s 19 voting directors and 11 emeritus directors represent companies from Europe, China, Japan, Korea, North America, and Taiwan, reflecting the global scope of the association’s activities. SEMI directors are elected by the general membership as voting members of the board and can serve a total of five two-year terms.

By Ed Korcynzski

Industry R&D consortium imec runs a series of technology forums around the world, starting in June in Antwerp, Belgium, and including a stop in July in San Francisco in coordination with SEMICON West. Greg McIntyre, imec Director of Advanced Patterning, discussed the state-of-the-art in Extreme Ultra-Violet (EUV) lithography technology with Solid State Technology during the Antwerp event. While still focusing on “path-finding” R&D for industry, the recent technology challenges associated with commercializing EUV lithography has pulled imec into work on patterning ecosystem materials such as resists and pellicles.

With each NXE:3400B model EUV stepper from ASML valued at US$125 million it costs $1 billion to invest in a set of 8 tools to begin high-volume manufacturing, and the entire lithography materials supply-chain is engaged in improving availability and throughput of this expensive tool-set. For high performance logic ICs we need EUV to reach the smallest and most powerful FETs possible, so EUV is in pilot production for logic chips at Samsung and TSMC this year, and will likely begin pilot ramps at Intel and GlobalFoundries next year.

The first use of EUV in IC HVM will be as “cut-masks” for use in self-aligned multi-patterning (SAMP) process flows that start with argon-fluoride-immersion (ArFi) deep ultra-violet (DUV) steppers. Such a first use allows for substitution of three ArFi “multi-color” cut-masks in place of the one EUV mask, in case there are unanticipated issues with the new EUV steppers. Second use in HVM will then happen using a single-exposure of EUV to pattern metal layers, but with no ability to use multiple ArFi exposure as a back-up.

“We will not put EUV in our critical path,” commented Dr. Gary Patton, GlobalFoundries’ CTO and SVP of Worldwide R&D, during a presentation in Antwerp, “But it’s clear that it’s coming and it will offer compelling advantages.” Patton said the company is experimenting with two of ASML’s EUV steppers in a New York fab, and will launch the company’s “7-nm-node” finFET production first with ArFi and then move to EUV when the throughput and uptime of the process make it affordable in their cost models.

Figure 1 shows the extremely small patterning process window around 18nm half-pitch line arrays (P36) using EUV lithography with Dipole source-mask optimization (SMO):  micro-bridging between lines starts below 15.5nm, while breaks within lines start above 18nm. These stochastic failures (Ref:  “Waddle-room for Black Swans:  EUV Stochastics”, SemiMD.com) are caused by variations in the photons absorbed by the resist (a.k.a. “shot noise”), the quantum efficiency of photo-acid generation (PAG) and diffusion, thequencher distribution,and optical and chemical interactions with under-layers for adhesion, anti-reflective coatings, and hardmasks.

Figure 1. Stochastic failures due to atomic-scale variability are shown in top-down CD-SEM images taken from 36-nm Pitch (P36) line/space arrays of post-etched photoresist that had been patterned using EUV lithography, which define the limits of the patterning process window when plotted as Percent Not-OK (%NOK) within an inspected area. (Source: imec)

Every nanometer of resolution is difficult to achieve when patterning below 20nm half-pitch, with many parameters contributing noise to the signal. For EUV lithography using reflective optics, the mask surface causes undesired “flare” reflections from the un-patterned area, such that bright-field masks inherently distort images more than dark-field masks. Since cuts typically only expose <20% of the field, these masks will be much less noisy as dark-fields.

Given the need for dark-field cut-masks, the ideal photoresist will be positive-tone (PT) which means that reformulations of Chemically-Amplified Resists (CAR) based on organic molecules can be used. Standard organic CAR tuned for ArFi lithography provides some sensitivity to EUV, and blends of standard CAR molecules can be tuned to improve trade-offs within the inherent Resolution, Line-Edge-Roughness (LER), and Sensitivity trade-off triangle. Consequently, all of the suppliers of ArFi CAR are capable of supplying some EUV CAR. Since stochastic effects are interdependent, resist vendors have to explore integration options within the entire stack of patterning materials.

JSR co-founded with imec the EUV Resist Manufacturing & Qualification Center NV (EUV RMQC) in Leuven, Belgium, where an EUV stepper at imec is available for experiments. “RMQC is running at full speed, and shipping out production lots,” said McIntyre. “Intel’s Britt Turkot mentioned at SPIE this year that the resist qualification work being done at IMEC has been very beneficial.”

ASML now owns the critical-dimension scanning-electron microscopy (CD-SEM) technology of Hermes Microvision Inc (HMI), and Neal Callan, ASML’s Vice President of Pattern Fidelity Metrology, spoke with Solid State Technologyabout controlling EUV patterning. Electron-beams cause shrinkage in organic films like CAR, and that shrinkage results in a CD bias that can be more than one nanometer. Different CAR formulations from different vendors shrink at different rates, and the effect is more difficult to model in 2D structures. ”We’re being pushed for accurate metrology in terms that can be quantified,” explained Callan. “The biggest issues are in terms of CD-bias with 2D features. We need to build more accurate models to create better data for OPC and for computational lithography, and also for our etch modeling peers.”

“Design rules for EUV need to be stochastically aware,“ confided McIntyre. “Designers need to know how much can be sacrificed in a design rule such as tip-to-tip spacing depending on the pattern pitch. There are different ways that we can think about minimizing stochastic effects.”

While stochastics and systematic yield losses increase in relative importance with decreasing device dimensions, losses due to random defects are also more difficult to control. Figure 2 shows second-generation EUV pellicles made from carbon nano-tubes (CNT) by imec to protect EUV masks from random particles while transmitting ~95%. First-generation pellicles reportedly transmit <90%.

Figure 2. Second generation EUV pellicles based on carbon nano-tubes (CNT) demonstrate increased transmission of ~95% while maintaining sufficient mechanical stability to protect reticles. (Source: imec)

“Today, new purity challenges are not only faced by the fab but also by their materials suppliers driving sharp increases in the use of filtration and purification systems to prevent wafer defects and process excursions,” explained Clint Harris, Senior Vice President and General Manager, Microcontamination Control Division, Entegris, to Solid State Technology.“The transition from 45nm- to 10nm-node has resulted in a 2.5x increase in the changeout frequency of filters as well as a 4x reduction of maximum allowable contaminant size. This trend is expected to continue as device parametric performance becomes more sensitive to particles, gels, metals, mobile ions, and other organic contaminants.”

[As a TECHCET Analyst, Ed Korczynski writes the TECHCET Critical Materials Report (CMR) on Photoresists & Ancillaries. https://techcet.com/product/photoresists-and-photoresist-ancillaries/]