Category Archives: Semiconductors

BY PETE SINGER, Editor-in-Chief

Increasingly, the ability to stay on the path defined my Moore’s Law will depend on advanced packaging and heterogeneous integration, including photonics integration.

At The ConFab in May, Bill Bottoms, chair of the integrated photonics technical working group, and co-chair of the heterogeneous integration roadmap (HIR) spoke about the changing nature of the industry and specifically the needs of photonic integration.

Bottoms said the driving force behind photonics integration is pretty straightforward: “The technology we have today can’t keep up with the expanding generation of transport and storage of data,” he said. But doing so will be a challenge.

The integration of photonics, electronics and plasmonics at a system level is necessary.

“These require heteroge- neous integration by architecture, by device type, by materials and by manufacturing processes,” Bottoms said. “We’re changing the way we’re doing things.”
These kinds of changes are best thought of not as packaging but system level integration. “As we move the photons as close as to the transistors as possible, we’re going to be faced with integrating everything on a simple substrate,” he said.

There are a large number of devices that involve photons which share the common requirement of providing a photon path either into or out of the package or both. They include: Light emitting diodes (LEDs), laser diodes, plasmonic photon emitters, photonic Integrated circuits (PICs), MEMS optical switching devices, camera modules, optical modulators, active optical cables, E to O and O to E converters, optical sensors (photo diodes and other types), and WDM multiplexers and de‐multi- plexers. Many of these devices have unique thermal, electrical and mechanical characteristics that will require specialized materials and system integration (packaging) processes and equipment, Bottoms noted.

Of the biggest challenges might be thermal management: “We have things that make a lot of heat and things that can’t have their temperature change by more than a degree without losing their functionality,” Bottoms said.

The scope of the HIR Photonics Chapter includes defining difficult challenges and, where possible, potential solutions associated with: data systems and the global network, photonic components, integrating these components and subsystems into systems with the smallest size, lowest weight, smallest volume, lowest power and highest performance.

It will also address supply chain requirements, which may turn out to be the biggest challenge. “We will not beat the challenge of cost pressures unless we develop the supply chain that can justify high volume. It’s the only way we know how to bring down costs,” Bottoms said. Sounds like a great opportunity for today’s equipment and materials suppliers to me!

BY GRIGORI BOKERIA, MATTHIAS FRAHM, SASCHA RAHMAN, and XI BING ANG, Simon-Kucher

The semiconductor industry is facing key challenges. In recent years, M&A mega deals have led to consolidations within the market, while the industry continues to mature. This leaves rather moderate growth prospects for the next three years. Semiconductor companies will have to consistently farm limited organic growth sources whilst at the same time tapping into new and growing macrotrends. To be successful in the long term, they must recognize the potential of the disruptive technologies and new markets that the Internet of Things will bring.

How can companies relive the previous successes in the mobile consumer segment?

In the 1990s and even early 2000s, growth booms in the industry with annual sales growth of 30 to 40 percent were the norm. Thanks to the sharply increasing demand in the consumer market for PCs, laptops and mobile phones, many smaller technology companies were able to grow into giants in the semiconductor business (FIGURE 1). However, since 2011, the industry has had to manage its growth expectations for the consumer market. With an average annual growth rate of 3.4 percent expected from 2015 to 2020, the strong growth period seems to be over and the dynamic start-up atmosphere of the past appears to be more or less history. The entire industry already has a market size of over 350 billion euros, with intense rigid competition among existing players. M&A mega deals (FIGURE 2) such as Qualcomm-NXP, Avago-Broadcom, Softbank-ARM and Western Digital-SanDisk have severely consolidated the market and now these companies are deep in operations integration and rationalization mode.

Is this the end of the period of constant growth outperformance? Not at all. Simon-Kucher project experience tells us that even organic growth sources based on dynamic market trends can be tapped, meaning companies can relive the successes in the mobile consumer sector. However, two fundamental strategic questions need to be answered: Where will these new growth waves come from?

And how can the imminent stagnation be avoided? We have identified three sources of organic growth that will play a pivotal role in the future of the semiconductor industry.

1.Exploit new disruptive technologies such as silicon carbide

Semiconductors based on silicon carbide (SiC) represent a strong area for future growth. Compared to semiconductors made of regular silicon, SiC-based semiconductors can operate at much higher frequency and temperature and convert electric power at lower losses, promising increased speed, robustness and efficiency. SiC devices are capable of managing the same power level as Si devices at half the size, boosting power density and reliability.

While a handful of players have already secured a favorable starting position in the market, there continues to be strong medium-term growth forecasts which means that the current market volume in this emerging product segment (~$200 million) still offers attractive entry potential for second and third movers. Several suppliers such as Dow Corning and Nippon Steel have entered and increased activity in the SiC market while companies such as Wolfspeed/Cree are experiencing decline in market share. This goes to show that there is still room to wrangle for territory.

We anticipate that hype will become mass reality within the next five to eight years, particularly driven by the growing demand in hybrid and electric mobility, regener- ative power generation and industrial applications. Notably, SiC may have a huge impact on the automotive industry, in particular on electric vehicles and e-mobility due to the high efficiency levels. In each of these markets, customers continue to demand and expect smaller wafers and devices with increasingly better performance profiles than Si-based devices, made possible by SiC technology. According to a recent Simon-Kucher study, global demand in the SiC technology segment and its sister technology gallium nitride (GaN) will amount to more than three billion euros by 2025, with double-digit annual growth rates. Industry analysts note that SiC has gradually emerged as “mainstream” material since 2016 which will result in drop in prices for devices from 2018 onwards. This would translate to possibly large increases in volume demand.

At the moment, the technology is still relatively cost-intensive and more complex in production primarily due to lack of scale. As such, SiC and GaN remain niche markets for now. However, having achieved first significant design-wins, first-moving companies are proof of the future market potential. The remaining semiconductor companies need to adapt their innovation strategies or risk trailing the pack. To successfully implement SiC and GaN system solutions, it is essential to closely orient new product development towards emerging market needs, starting from initial development phases.

Here, semiconductor companies have to identify the appli- cations where customers already demand high switching voltage and speed, low switching losses, and a small size and weight. Only in doing so can they expect customer- oriented market success from design-in to design-win.

2. Anticipate and seize new markets materializing from the Internet of Things

The Internet of Things (IoT) has now become the catch-all phrase that encapsulates an enormous spectrum of potential applications and markets revolving around interconnected physical devices and appliances. As it continues to evolve and numerous markets around it become commercially viable, semiconductor companies have a huge opportunity to capture the underlying profit pools. By some accounts, something like 3 billion new IoT-enabled devices are manufactured per year; at the most rudimentary level, each of these devices require microcontrollers, sensors, actuators and a whole host of other semiconductor-enabled parts. Another indirect area of growth for semiconductor companies will likely emerge from the fact that the exponentially increasing amount of data generated by IoT products need to be processed and stored. This will lead to demand for more server farms and greater storage capacities.

IoT products and applications would not be possible without the continued advancements in semiconductor technology, and the demand for inexpensive chips that can be mass- produced will only continue to increase. Rather than spectating and reacting to this market macrotrend from the sidelines, semiconductor companies should see the IoT as an integral part of the future market’s DNA.

The current challenge is the fragmented nature of the market, with no clear “killer application” or common platform; rather, there is a multitude of smaller niche opportunities that in its entirety promise overall attractive growth potential. No player has yet been able to establish a market-dominant position in this highly diversified market. There are, however, specific end-markets that have taken the lead (for now) in terms of showing promise of growth, such as smart home applications, consumer wearables (e.g. fitness bracelets, smart watches), medical electronics, and connected cars (FIGURE 3). The IoT will turn these individual niche segments into potential game-changers for the semiconductor industry.

Amid these fast-evolving segments, critical for the success of semiconductor companies is their agility in swiftly responding to emerging trends and integrating hardware and software components along the value chain and ultimately, offering a seamless IoT solution. Semiconductor companies already focusing on seamless security, communication intel- ligence and user-friendliness are a step ahead in strength- ening their position. To not be left behind, semiconductor companies need to make the strategic decision of prioritising resources and investments into IoT-related growth sources and resist the inertia and temptation to solely rely on existing “bread and butter” revenue streams, regardless of how healthy the current margins are. Related to this, to get serious about this emerging opportunity, semiconductor companies should not view the IoT markets as a nebulous concept with opportunistic revenue streams, but rather conduct in-depth analyses of their current position within the changing value chains and competitive landscape to formulate concrete go-to-market plans.

3. Shift from component-centric sales to supplying system solutions

Finally, a third dimension of growth beyond new products and new markets for semiconductor companies is to move up the value chain. Increasingly, leading market players are integrating chips, drivers, software and sensors to offer partial system solutions, with the ultimate objective of being ecosystem enablers. Naturally, this requires the capability to not only sell hardware (semiconductors, wafers, etc.) but an entire system and services around it that several entities from different industries can utilise to establish their own IoT products. However, for companies traditionally built around selling components, doing this successfully is not a straightforward undertaking. Many sales forces are finding themselves lacking the organizational setup and solution-selling approach critical for success. In addition, in order to integrate products in the portfolio into systems solutions, companies have to establish effective cross-industry channel management on the sales front and at the same time develop strong alliances with partners along the value chain to ensure a stable ecosystem. Successful players will be those in the market with the capability to provide modular solutions that can readily interlink products with security, software and system consulting services.

As a result, we believe that the desire of companies to move towards being system suppliers and ecosystem enablers will further increase M&A activity due to the need to acquire specialised knowledge. Notably, Intel has acquired three companies within the space of a year from different parts of the industry to assimilate specific expertise related to IoT i.e. Altera (designer and manufacturer of program- mable logic devices), Nervana Systems (artificial intelligence software developer) and Itseez (specialist in computer vision technology and algorithms).

In summary, despite some notions otherwise, we are bullish about the imminent growth potential in the semiconductor market driven by very powerful macrotrends in product technology, emerging applications and also value chain shifts. Semiconductor companies thirsty for new waves of exponential growth would do well to heed the signposts from these trends and re-orient their product development, industry alliances and sales approaches rapidly in order to capitalise on these opportunities before the winner takes all.

Grigori Bokeria is a Partner in Simon-Kucher’s Cologne office, where Sascha Rahman is a Director; Matthias Frahm is a Senior Director in the Bonn office and Xi Bing Ang is a Director based in the London office. All four authors work within Simon-Kucher’s Global Technology & Industrial practice.

Process-induced overlay errors from outside the litho cell have become a significant contributor to the overlay error budget including non-uniform wafer stress.

BY HONGGOO LEEa, SANGJUN HANa, JAESON WOOa, JUNBEOM PARKa, CHANGROCK SONGa, FATIMA ANISb, PRADEEP VUKKADALAb, SANGHUCK JEONc, DONGSUB CHOIc, KEVIN HUANGb, HOYOUNG HEOb, MARK D SMITHb, JOHN C. ROBINSONb

aSK Hynix, Korea
bKLA-Tencor Corp., Milpitas, CA cKLA-Tencor Korea, Korea

As ground rules shrink, advanced technology nodes in semiconductor manufacturing demand smaller process margins and hence require improved process control. Overlay control has become one of the most critical parameters due to the shrinking tolerances and strong correlation to yield. Process-induced overlay errors, from outside the litho cell, including non-uniform wafer stress, has become a significant contributor to the error budget. Previous studies have shown the correlation between process-induced stress and overlay and the opportunity for improvement in process control [1, 2]. Patterned wafer geometry (PWG) metrology has been used to reduce stress-induced overlay signatures by monitoring and improving non-litho process steps or by compensation for these signatures by feed forward corrections to the litho cell [3,4]. Of paramount impor- tance for volume semiconductor manufacturing is how to improve the magnitude of these signatures, and the wafer to wafer variability. Standard advanced process control (APC) techniques provide a single set of control parameters for all wafers in a lot, and thereby only provide aggregate corrections on a per chuck basis. This work involves a novel technique of using PWG metrology to provide improved litho-control by wafer- level grouping based on incoming process induced overlay.

Wafer stress induced overlay is becoming a major challenge in semiconductor manufacturing, and the percentage contribution to the overlay budget is increasing. Addressing non-litho overlay is paramount to reducing wafer level variability. The amplitude of stress and the overlay budget differ by market segment. We observe from FIGURE 1 that the 3D NAND, for example, has the largest magnitude of wafer shape induced stress, but also has a relatively large overlay budget of 8 to 20 nm. DRAM, on the other hand, has less stress, but has a much tighter overlay spec of 2 to 3 nm. The relative stress level and overlay budget dictate different process control use cases. For the case of 3D NAND, the improved overlay can be achieved using the PWG stress data for process monitoring as mentioned earlier, or by directly providing the stress based feed forward corrections to the litho cell [3, 4]. In this work, we will focus on the DRAM device application. Key topics include identifying process signatures in the shape data, and using those signatures to reduce within lot variability.

Firstly, we will discuss the connection between wafer shape and overlay. During integrated circuit manufacturing many layers are printed on a silicon wafer. There is a critical need to align precisely pattern layers to an underlying pattern. This requirement is often complicated tighter overlay spec of 2 to 3 nm. The relative stress level and overlay budget dictate different process control use cases. For the case of 3D NAND, the improved overlay can be achieved using the PWG stress data for process monitoring as mentioned earlier, or by directly providing the stress based feed forward corrections to the litho cell [3, 4]. In this work, we will focus on the DRAM device application. Key topics include identifying process signa- tures in the shape data, and using those signatures to reduce within lot variability.

Firstly, we will discuss the connection between wafer shape and overlay. During integrated circuit manufac- turing many layers are printed on a silicon wafer. There is a critical need to align precisely pattern layers to an underlying pattern. This requirement is often complicated by process induced stress variations distorting the under- layer pattern, as illustrated in FIGURE 2 [5, 6]. A reference layer pattern is formed at a certain level N (or layer N) and the pattern is initially defined by the characteristic length L shown. To form level N+1, a film is first deposited on top of level N. Film stress causes the wafer to warp in free-state resulting in a change to shape of wafer. This is typically manifested as both out-of-plane displacement (OPD) and in-plane displacement (IPD), affecting lateral placement of the under-layer pattern (level N). To print the level N+1 pattern the wafer is forced flat (e.g. lithog- raphy vacuum chucked). For the most part, chucking the wafer fully reverses the out-of-plane displacement but the in-plane displacement is only partially reversed. Thus, the under-layer pattern is now displaced relative to where it was originally printed. If level N+1 pattern is printed without correcting for the under-layer distortion, it results in misalignment or overlay error between the two layers. Such an overlay error is known as process- induced or process-stress induced overlay error and it can be caused by any type of stress inducing semiconductor process such as film deposition, thermal anneal, etch, CMP, etc.

Wafer shape is measured by a unique implementation of a dual-Fizeau interferometer on KLA-Tencor Corporation’s WaferSightTM PWG patterned wafer geometry and nanotopography metrology system [7]. Simultaneous back side and front side measurements are made with the wafer in a vertical orientation to eliminate gravitational distortion.

Overlay is measured on a KLA-Tencor Corporation ArcherTM 500 overlay metrology system using Archer AIM® optical imaging metrology targets.

It has been shown that process-induced overlay error can be accurately estimated from the change in shape induced by semiconductor processes [2, 6, 8, 9]. FIGURE 3 shows a simplified schematic of a semiconductor process flow of a single layer. To estimate potential overlay error induced by processes between the reference lithography step (e.g. level N) and the current lithography step (e.g. level N+1), it is necessary to make wafer geometry measurement at the two indicated points in the figure as “pre” and “post”, corresponding to before and after the shape or stress inducing process steps. Once wafer geometry measure- ments become available, the change in the shape induced by processing is calculated as the difference between two measurements. Process-induced overlay error can then be calculated from the shape change by using one of several algorithms that have been developed [2, 6, 8, 9]. In this paper, we use an advanced IPD algorithm based on two-dimensional plate mechanics for the accurate estimation of the process-induced overlay error referred to as GEN3 [2].

Shape based overlay for DRAM

As discussed previously, different semiconductor processes have varying levels of stress and different overlay error budgets, including 3D NAND, DRAM, logic, etc. These differences require different process control use cases, such as feedback, feed forward, grouping, etc., alone or in combination. In this work we describe an advanced grouping process control use case for DRAM in order to minimize overlay. For this investigation we look at a specific implementation of wafer grouping which is appropriate to R&D environments and ramp-up of high volume manufacturing (HVM) called here send-ahead grouping (SG). The more general grouping use case for HVM will be addressed in a future report.

In order to meet the tight overlay specifications for the next generation DRAM devices, a send-ahead grouping (SG) based on the shape data has been evaluated. The flow of the proposed SG is outlined in FIGURE 4. Firstly, all the wafers in a lot are measured with a PWG tool for both “pre” and “post” layers. The shape data from the difference of these measurements is then used in the GEN3 algorithm to determine stress or shape based predicted overlay. The wafers are then grouped by similarity of wafer signatures. Grouping optimi- zation is performed using the predicted overlay after removing the POR scanner alignment model. The grouping optimi- zation: (i) decides the optimal number of process signatures; (ii) identifies the process signatures; and, (iii) provides a list of recommended wafers for metrology and exposure (step 2 in Fig. 4). The selected wafers are then exposed by the scanner in step 3 and the overlay measurement is performed in step 4. Finally, the correctable coefficients for each group will be calculated separately using the overlay metrology data. The exposed wafers will be reworked and then the entire lot will be exposed using the group by group corrections.

Within lot variability

The work is aimed at reducing the within lot variability. The within lot variability or wafer by wafer (WxW) variability is becoming one of the most important challenges to achieve tight overlay speci- fications for next generation DRAM devices. First we quantify within lot variability for both the shape and the overlay data using a rigorous analysis of variance (ANOVA). We analyzed seven lots individually and the results for both the overlay and PWG data are presented in FIGURES 5 and 6 respectively. The overlay data show an average of 3.6 nm WxW variation in both the X and Y direction. The shape based overlay average within lot variation is 0.55 nm in X and 0.46 nm in the Y direction.

It should be noted that the within lot variation of the overlay data is comprised of different sources and the shape based overlay explains only part of the total within lot overlay variation. FIGURE 7 shows the ratio % of the within lot variation shape based overlay versus the total overlay for both the X and Y direction. It can be seen that shape overlay can explain as much as up to 25% of the total overlay variability. These findings indicate that minimizing the impact of stress based overlay, from processes outside the litho cell, will provide potentially significant improvement, which is critical in the drive towards 2 nm overlay.

DRAM clustering results

For all of the analyses presented in this study, the GEN3 algorithm was used to calculate stress based overlay. To perform grouping the scanner alignment model was first removed from the stress based overlay for each wafer. The alignment removes some of the within lot varia- tions, however, wafer level alignment is not sufficient to remove all the wafer level variations. One useful way to visualize data variation is by performing Principle Component Analysis (PCA) of the data. By performing PCA, we express data in terms of Eigen functions of the covariance matrix of the data. Eigen values of the covariance matrix are calculated such that the first principle component explains the largest variation of the data, the second explains the second largest variation and so on. The coefficient for each principle component (PC) is referred to as the score. FIGURE 8 shows scores for the PC1 (first principle component) versus the PC2 (second principle component) for all the wafers for a single lot using stress based overlay. Two distinct groups, indicating two distinct process signatures can clearly be observed in this lot.

The same analysis was performed for the rest of the six lots as shown in FIGURE 9. For all the lots in this example, two signatures can clearly be observed in their leading scores plot. Some excursion wafers were removed from the analysis. After observing these clear process signature groupings, it was confirmed that the signatures correspond to the two stages of a process tool. This clearly proves that the stress overlay grouping method can successfully identify and distinguish significant process signatures. It should be noted that in the general case the optimal number of groups would not necessarily be two.

We quantified the stress overlay grouping by performing comprehensive send-ahead grouping (SG) simulation study. Grouping optimization was performed using the shape data to select optimal number of groups and also the send-ahead wafers for processing and metrology. Then using the send-ahead wafers for each group, ideal corrections were simulated and applied to each group in the lot. From the composite group residual, |mean|+3σ for each wafer was recorded. The residual |mean|+3σ was also calculated using the standard plan of record (POR) wafers. The root mean square for the average of the |mean|+3σ for X and Y is compared between SG and POR in FIGURE 10. The average |mean|+3σ improved by more than 0.5 nm using the SG solution.

The range is defined as the difference of the maximum and minimum |mean|+3σ per lot for both the X and Y direction. FIGURE 11 shows the comparison of the RMS of X and Y ranges for the six lots. The range has been improved by about 1 nm, underscoring the benefit of controlling wafer level variation by using shape data to identify signatures and group wafers for exposure and metrology.

Conclusions

Process induced overlay errors from outside the litho cell have become a significant contributor to the overlay error budget. It is no longer sufficient to focus exclusively on litho cell overlay improvement. Addressing non-litho overlay is key to reducing wafer level variability. We demonstrated a novel technique of using PWG metrology to provide improved litho control by wafer-level grouping based on incoming process induced overlay in a 19 nm DRAM manufacturing process driving towards a 2 nm overlay budget. Wafer to wafer variability range was reduced by around 1 nm across the lots in this study. Future directions include a full HVM implementation of the grouping methodology.

References

1. Characterization and mitigation of overlay error on silicon wafers with nonuniform stress, T. Brunner, et. al., SPIE Volume 9052: Optical Microlithography XXVII, April 2014.
2. Patterned wafer geometry (PWG) metrology for improving process-induced overlay and focus problems, Timothy A. Brunner, et. al., SPIE Volume 9780: Optical Microlithography XXIX, 97800W March 2016.
3. Improvement of process control using wafer geometry for enhanced manufacturability of advanced semiconductor devices, Honggoo Lee, et. al., SPIE Volume 9424: Metrology, Inspection, and Process Control for Microlithography XXIX, April 2015.
4. Lithography overlay control improvement using patterned wafer geometry for sub-22nm technology nodes, Joel Peterson, et. al., SPIE Volume 9424: Metrology, Inspection, and Process Control for Micro- lithography XXIX, April 2015.
5. 5. Relationship between localized wafer shape changes induced by residual stress and overlay errors, K. T. Turner, et. al., Volume 11(1), J. Micro/ Nanolithog. MEMS MOEMS, 013001 December 2012..
6. Characterization of Wafer Geometry and Overlay Error on Silicon Wafers with Nonuniform Stress, T. A. Brunner, et. al., Volume 12(4), Journal of Micro/ Nanolithography, MEMS, and MOEMS 0001, 043002-043002, September 2013.
7. “Interferometry for wafer dimensional metrology,” , K. Freischlad, S. Tang, and J. Grenfell, Proc. SPIE, 6672,667202 (2007).
8. Monitoring process-induced overlay errors through high resolution wafer geometry measurements, K. T. Turner, et. al., SPIE Volume 9050: Metrology, Inspection, and Process Control for Microlithog- raphy XXVIII, 905013, April 2014.
9. Process tool monitoring and matching using inter- ferometry technique, Doug Anberg, et. al., SPIE Volume 9778: Metrology, Inspection, and Process Control for Microlithography XXX, 977831, April 2015.

Reprinted with permission. Original source: Honggoo Lee, Sangjun Han, Jaeson Woo, Junbeom Park, Changrock Song, et al., “Patterned Wafer Geometry Grouping for Improved Overlay Control,” Metrology, Inspection, and Process Control for Microlithography XXXI, edited by Martha I. Sanchez, Vladimir A. Ukraintsev, Proc. of SPIE Vol. 10145, 101450O, (2017).

To eliminate voids, it is important to control the process to minimize moisture absorption and optimize a curing profile for die attach materials.

BY RONGWEI ZHANG and VIKAS GUPTA, Semiconductor Packaging, Texas Instruments Inc., Dallas, TX

Polymeric die attach material, either in paste or in film form, is the most common type of adhesive used to attach chips to metallic or organic substrates in plastic-encapsulated IC packages. It offers many advantages over solders such as lower processing temperatures, lower stress, ease of application, excellent adhesion and a wide variety of products to meet a specific application. As microelectronics move towards thinner, smaller form factors, increased functionality, and higher power density, void formation in die attach joints (FIGURE 1), i.e. in die attach materials and/or at die attach interfaces, is one of the key issues that pose challenges for thermal management, electrical insulation and package reliability.

Impact of voids

Voids in die attach joints have a significant impact on die attach material cracking and interfacial delamination. Voids increase moisture absorption. If plastic packages with a larger amount of absorbed moisture are subject to a reflow process, the absorbed moisture (or condensed water in the voids) will vaporize, resulting in a higher vapor pressure. Moreover, stress concentrations occur near the voids and frequently are responsible for crack initiation. On the other hand, voids at the interface can degrade adhesive strength. The combined effect of higher vapor pressure, stress concentration around the voids and decreased adhesion, as a result of void formation, will make the package more susceptible to delamination and cracking [1].

Additionally, heat is dissipated mainly through die attach layer to the exposed pad in plastic packages with an exposed pad. Voids in die attach joints can result in a higher thermal resistance and thus increase junction temperatures significantly, thereby impacting the power device performance and reliability.

And finally, voiding is known to adversely affect electrical performance. Voiding can increase the volume resistivity of electrically conductive die attach materials, while decreasing electrical isolation capability. Therefore, it is crucial to minimize or eliminate voids in die attach joints to prevent mechanical, thermal and electrical failures.

Void detection

The ability to detect voids is key to ensuring the quality and reliability of die attach joints. There are four common techniques to detect voids: (1) Scanning Acoustic Microcopy (SAM), (2) X-ray imaging, (3) cross-section or parallel polishing with optical or electron microscope, and (4) glass die/slide with optical microscope (Fig. 1). The significant advantage of SAM over other techniques lies in its ability to detect voids in different layers within a package non-destructively. Void size detection is limited by the minimal defect size detected by SAM. If the void is too small, it may not be detected at all, depending on the package and equipment used. X-ray analysis allows for non-destructive detection of voids in silver-filled die attach materials. However its limits lie in its low resolution and magnification, a low sensitivity for the detection of voids in a thick sample, and its inability to differentiate voids at different interfaces [2]. Cross-section or parallel polishing with electronic microscope provides a very high magnification image to detect small voids, although it is destructive and time-consuming. Glass die or glass substrate with an optical microscope provides a simple, quick and easy way to visualize the voids.

Potential root causes of voids and solutions

There are four major sources of voids: (1) air trapped during a thawing process, (2) moisture induced voids, (3) voids formed during die attach film (DAF) lamination, and (4) volatile induced voids.

Freeze-thaw voids When an uncured die attach paste in a plastic syringe is removed from a freezer (typically -40oC) to an ambient environment for thawing, the syringe warms and expands faster than the adhesive. This intro- duces a gap between syringe and the adhesive. Upon thawing, the adhesive will re-wet the syringe wall and air located in between the container and adhesive may become trapped. As a result, voids form. This is referred as freeze-thaw void [3]. The voids in pastes may cause incom- plete dispensing pattern leading to inconsistent bond line thickness (BLT) and die tilt, thus causing delamination. Planetary centrifugal mixer is the most commonly used and effective equipment to remove this type of void.

Moisture induced voids

Die attach material contains polar functional groups, such as hydroxyl group in epoxy resins and amide group in curing agents, which will absorb moisture from the environment during exposure in die attach process. As the industry moves to larger lead frame strips (100mm x 300mm), the total number of units on a lead frame strip increase significantly. As a result, die attach pastes may have been exposed to a production environment significantly longer before die placement. After die placement, there could also be a significant amount of waiting time (up to 24 hours) before curing. Both can result in a high moisture absorption in die attach pastes. Moreover, organic substrates can absorb moisture, while moisture may be present on metal lead frame surfaces. As temperatures increase during curing, absorbed moisture or condensed water will evolve as stream to cause voiding. Voids can also form at the DAF-substrate interface as a result of moisture uptake during the staging time between film attach and encapsulation process. Controlling moisture absorption of substrates and die attach materials at each stage before curing and production environment are critical to prevent moisture induced voids in die attach joints.

Void formation during DAF lamination

One challenge associated with DAF is voiding during DAF lamination, especially when it is applied to organic substrates [FIGURE 1(d)]. There is a correlation of void pattern with the substrate surface topography [4]. Generally, increasing temperature, pressure and press time can reduce DAF melt viscosity and enable DAF to better wet lead frame or substrates, thereby preventing entrapment of voids at die attach process. If the DAF curing percentage is high before molding, then DAF has limited flow ability, and thus cannot completely fill the large gaps on the substrate. Consequently, voids present at the interface between DAF and an organic substrate since die bonding process. But if DAF has a lower curing percentage before molding, then DAF can re-soft and flow into large gaps under heat and transfer pressure to achieve voids-free bond line post molding [4].

Volatile induced voids

Voids in die attach joints are generally formed during thermal curing since die attach pastes contain volatiles such as low molecular weight additives, diluents, and in some cases solvents for adjusting the viscosity for dispensing or printing. To study the effect of outgassing amounts on voids, we select three commercially available die attach materials with a significant difference in outgassing amounts using the same curing profile. As shown in FIGURE 2, as temperature increases, all die attach pastes outgas. DA1 shows a weight loss of 0.74wt%, DA2 3.1wt% and DA3 10.62wt%. Once volatiles start to outgas during thermal curing, they will begin to accumulate within the die attach material or at die attach interfaces. Voids begin to form by the entrapment of outgassing species or moisture. After voids initially form, voids can continue to grow until the volatiles have been consumed or the paste has been cured enough to form a highly cross- linked network. FIGURE 3 shows optical images of dices assembled onto glass slides using three die attach materials. As expected, DA1 shows no voids for both die sizes of 2.9mm x 2.9mm and of 9.0mm x 9.2mm, due to a very low amount of outgassing (0.74wt%). DA2 shows no voids for the small die size, but many small voids under the die periphery for the large die. Large voids are observed for DA3 for both die sizes since it has a very large amount of outgassing (10.62wt%). DA2 also shows voids even with a medium die size 6.4mm x 6.4mm [FIGURE 3(g)]. Differential Scanning Calorimetry (DSC) was used to further study the curing behaviors of DA2 and DA3, as shown in FIGURES 4 and 5. Comparing FIGURE 4 with FIGURE 5, it is interesting to observe the difference in thermal behavior of the two die attach materials. For DA2, as curing starts, the weight loss rate becomes slower, while the weight loss rate for DA3 accelerates as curing starts. It is very likely that the outgassing species in DA2 is reactive diluent, which has a lower weight loss rate when the reaction starts. But for DA3, outgassing is a non-reactive solvent, and possibly with other reactive species. The non-reactive solvent has a boiling point at 172.9oC, as verified in the DSC. Heat generated in the curing process accelerates evaporation of the solvent. The continuous, slow release outgassing amount during ramp and curing at 180oC explains the formation of small voids in DA2, while fast evaporation of solvent accounts for large voids in DA3. To reduce or eliminate voids during thermal curing, a simple and the most common approach is to use a two-step (or multi- step)cure.Thefirststepisdesignedtoremovevolatiles, followed by a second step of curing. With the first step at 120oC for 1h to remove more volatiles, DA2 shows significantly less voids for a die size of 6.4mm x 6.4mm [FIGURE 3(h)].

Ideally, the majority (if not all) of volatiles should be removed prior to the gelation point, which is defined as the intersection of G’ and G’’ in a rheological test. Because the viscosity of die attach, materials increases dramatically after their gelation point. A higher amount of volatiles released after gelation point (or later stage of curing) are more likely to form voids. Therefore, the combined characterization of TGA and DSC, as well as rheological test, provides a good guideline to design optimal curing profiles to minimize or eliminate voids.

Summary

This article provides an understanding of void impact in die attach joints, the techniques to detect voids, voiding mechanisms, and their corresponding solutions. To eliminate voids, it is important to control the process to minimize moisture absorption and optimize a curing profile for die attach materials. TGA, DSC and Rheometer are key analytical tools to optimize a curing profile to prevent voiding. In addition, many other properties such as modulus, coefficient of thermal expansion (CTE), and adhesion need to be considered when optimizing curing profiles. Last but not least, it is crucial to develop die attach materials with less outgassing and moisture absorption without compro- mising manufacturability, reliability and performance.

References

1. R.W.Zhang,etal., “Solving delamination in lead frame-based packages,” Chip Scale Review, 2015, pp. 44-48.
2. L. Angrisani, et al., “Detection and location of defects in electronic devices by means of scanning ultrasonic microcopy and the wavelet transform,” Measurement, 2002, Vol. 31, pp. 77-91.
3. D. Wyatt, et al., “Method for reducing freeze-thaw voids in uncured adhesives,” 2006 US 11/402,170.
4. Y. Q. Su, et al., “Effect of transfer pressure on die attach film void perfor- mance,” 2009 IEEE 11th Electronic Packaging Technology Conference, pp. 754-757.

RONGWEI ZHANG is a Packaging Engineer, and VIKAS GUPTA is an Engineering Manager, Semiconductor Packaging, Texas Instruments Inc., Dallas, TX.

Market shares of semiconductor equipment manufacturers shifted significantly in Q1 2018 as Applied Materials, the top supplier dropped, according to the report “Global Semiconductor Equipment: Markets, Market Shares, Market Forecasts,” recently published by The Information Network, a New Tripoli-based market research company.

The chart below shows shares for the first quarter (Q1) of calendar year 2017 and 2018. Market shares are for equipment only, excluding service and spare parts, and have been converted for revenues of foreign companies to U.S. dollars on a quarterly exchange rate.

Applied Materials lost significant market share YoY, from 18.4% of the $13.1 billion Q1 2017 market to 17.7% of the $17.0 billion Q1 2018 market. This drop follows a 1.8 share-point loss by Applied Materials for CY 2017 compared to 2016. The company competes with Lam Research and TEL in the deposition and etch market, and both gained share at the expense of Applied Materials.

At the other end of the spectrum, smaller semiconductor companies making up the “other” category lost 2.4 share points as a whole.

Much of the equipment revenue growth was attributed to strong growth in the DRAM and NAND sectors, as equipment was installed in memory manufacturers Intel, Micron Technology, Samsung Electronics, SK Hynix, Toshiba, and Western Digital. The memory sector, which grew grown 61.5% in 2017, is forecast to add another 28.5% in 2018 according to industry consortium WSTS (World Semiconductor Trade Statistics).

TEL recorded growth of 120.3% YoY in Korea, much of it on NAND and DRAM sales to Samsung Electronics and SK Hynix, and 69.5% YoY in Japan, much of it on NAND sales to Toshiba at its Fab 6 in Kitakami, Japan. Lam Research gained 42.2% and 70.5% YoY, respectively, in Korea and Japan.

Following the strong growth in the semiconductor equipment market, The Information Network projects another 11.5% growth in 2018 for semiconductor equipment.

Directly converting electrical power to heat is easy. It regularly happens in your toaster, that is, if you make toast regularly. The opposite, converting heat into electrical power, isn’t so easy.

Researchers from Sandia National Laboratories have developed a tiny silicon-based device that can harness what was previously called waste heat and turn it into DC power. Their advance was recently published in Physical Review Applied.

This tiny silicon-based device developed at Sandia National Laboratories can catch and convert waste heat into electrical power. The rectenna, short for rectifying antenna, is made of common aluminum, silicon and silicon dioxide using standard processes from the integrated circuit industry. Credit: Photo by Randy Montoya/Sandia National Laboratories

“We have developed a new method for essentially recovering energy from waste heat. Car engines produce a lot of heat and that heat is just waste, right? So imagine if you could convert that engine heat into electrical power for a hybrid car. This is the first step in that direction, but much more work needs to be done,” said Paul Davids, a physicist and the principal investigator for the study.

“In the short term we’re looking to make a compact infrared power supply, perhaps to replace radioisotope thermoelectric generators.” Called RTGs, the generators are used for such tasks as powering sensors for space missions that don’t get enough direct sunlight to power solar panels.

Davids’ device is made of common and abundant materials, such as aluminum, silicon and silicon dioxide — or glass — combined in very uncommon ways.

Silicon device catches, channels and converts heat into power

Smaller than a pinkie nail, the device is about 1/8 inch by 1/8 inch, half as thick as a dime and metallically shiny. The top is aluminum that is etched with stripes roughly 20 times smaller than the width of a human hair. This pattern, though far too small to be seen by eye, serves as an antenna to catch the infrared radiation.

Between the aluminum top and the silicon bottom is a very thin layer of silicon dioxide. This layer is about 20 silicon atoms thick, or 16,000 times thinner than a human hair. The patterned and etched aluminum antenna channels the infrared radiation into this thin layer.

The infrared radiation trapped in the silicon dioxide creates very fast electrical oscillations, about 50 trillion times a second. This pushes electrons back and forth between the aluminum and the silicon in an asymmetric manner. This process, called rectification, generates net DC electrical current.

The team calls its device an infrared rectenna, a portmanteau of rectifying antenna. It is a solid-state device with no moving parts to jam, bend or break, and doesn’t have to directly touch the heat source, which can cause thermal stress.

Infrared rectenna production uses common, scalable processes

Because the team makes the infrared rectenna with the same processes used by the integrated circuit industry, it’s readily scalable, said Joshua Shank, electrical engineer and the paper’s first author, who tested the devices and modeled the underlying physics while he was a Sandia postdoctoral fellow.

He added, “We’ve deliberately focused on common materials and processes that are scalable. In theory, any commercial integrated circuit fabrication facility could make these rectennas.”

That isn’t to say creating the current device was easy. Rob Jarecki, the fabrication engineer who led process development, said, “There’s immense complexity under the hood and the devices require all kinds of processing tricks to build them.”

One of the biggest fabrication challenges was inserting small amounts of other elements into the silicon, or doping it, so that it would reflect infrared light like a metal, said Jarecki. “Typically you don’t dope silicon to death, you don’t try to turn it into a metal, because you have metals for that. In this case we needed it doped as much as possible without wrecking the material.”

The devices were made at Sandia’s Microsystems Engineering, Science and Applications Complex. The team has been issued a patent for the infrared rectenna and have filed several additional patents.

The version of the infrared rectenna the team reported in Physical Review Applied produces 8 nanowatts of power per square centimeter from a specialized heat lamp at 840 degrees. For context, a typical solar-powered calculator uses about 5 microwatts, so they would need a sheet of infrared rectennas slightly larger than a standard piece of paper to power a calculator. So, the team has many ideas for future improvements to make the infrared rectenna more efficient.

Future work to improve infrared rectenna efficiency

These ideas include making the rectenna’s top pattern 2D x’s instead of 1D stripes, in order to absorb infrared light over all polarizations; redesigning the rectifying layer to be a full-wave rectifier instead of the current half-wave rectifier; and making the infrared rectenna on a thinner silicon wafer to minimize power loss due to resistance.

Through improved design and greater conversion efficiency, the power output per unit area will increase. Davids thinks that within five years, the infrared rectenna may be a good alternative to RTGs for compact power supplies.

Shank said, “We need to continue to improve in order to be comparable to RTGs, but the rectennas will be useful for any application where you need something to work reliably for a long time and where you can’t go in and just change the battery. However, we’re not going to be an alternative for solar panels as a source of grid-scale power, at least not in the near term.”

Davids added, “We’ve been whittling away at the problem and now we’re beginning to get to the point where we’re seeing relatively large gains in power conversion, and I think that there’s a path forward as an alternative to thermoelectrics. It feels good to get to this point. It would be great if we could scale it up and change the world.”

Smart technologies take center stage tomorrow as SEMICON West, the flagship U.S. event for connecting the electronics manufacturing supply chain, opens for three days of insights into leading technologies and applications that will power future industry expansion. Building on this year’s record-breaking industry growth, SEMICON West – July 10-12, 2018, at the Moscone Center in San Francisco – spotlights how cognitive learning technologies and other disruptors will transform industries and lives.

Themed BEYOND SMART and presented by SEMI, SEMICON West 2018 features top technologists and industry leaders highlighting the significance of artificial intelligence (AI) and the latest technologies and trends in smart transportation, smart manufacturing, smart medtech, smart data, big data, blockchain and the Internet of Things (IoT).

Seven keynotes and more than 250 subject matter experts will offer insights into critical opportunities and issues across the global microelectronics supply chain. The event also features new Smart Pavilions to showcase interactive technologies for immersive, virtual experiences.

Smart transportation and smart manufacturing pavilions: Applying AI to accelerate capabilities

Automotive leads all new applications in semiconductor growth and is a major demand driver for technologies inrelated segments such as MEMS and sensors. The SEMICON West Smart Transportation and Smart Manufacturing pavilions showcase AI breakthroughs that are enabling more intelligent transportation performance and manufacturing processes, increasing yields and profits, and spurring innovation across the industry.

Smart workforce pavilion: Connecting next-generation talent with the microelectronics industry

SEMICON West also tackles the vital industry issue of how to attract new talent with the skills to deliver future innovations. Reliant on a highly skilled workforce, the industry today faces thousands of job openings, fierce competition for workers and the need to strengthen its talent pipeline. Educational and engaging, the Smart Workforce Pavilion connects the microelectronics industry with college students and entry-level professionals.

In the Workforce Pavilion “Meet the Experts” Theater, recruiters from top companies are available for on-the-spot interviews, while career coaches offer mentoring, tips on cover letter and resume writing, job-search guidance, and more. SEMI will also host High Tech U (HTU) in conjunction with the SEMICON West Smart Workforce Pavilion. The highly interactive program supported by Advantest, Edwards, KLA-Tencor and TEL exposes high school students to STEM education pathways and useful insights about careers in the industry.

Releasing its Mid-Year Forecast at the annual SEMICON West exposition, SEMI, the global industry association representing the electronics manufacturing supply chain, today reported that worldwide sales of new semiconductor manufacturing equipment are projected to increase 10.8 percent to $62.7 billion in 2018, exceeding the historic high of $56.6 billion set last year. Another record-breaking year for the equipment market is expected in 2019, with 7.7 percent forecast growth to $67.6 billion.

The SEMI Mid-Year Forecast predicts wafer processing equipment will rise 11.7 percent in 2018 to $50.8 billion. The other front-end segment, consisting of fab facilities equipment, wafer manufacturing, and mask/reticle equipment, is expected to jump 12.3 percent to $2.8 billion this year. The assembly and packaging equipment segment is projected to grow 8.0 percent to $4.2 billion in 2018, while semiconductor test equipment is forecast to increase 3.5 percent to $4.9 billion this year.

In 2018, South Korea will remain the largest equipment market for the second year in a row. China will rise in the rankings to claim the second spot for the first time, dislodging Taiwan, which will fall to the third position. All regions tracked except Taiwan will experience growth. China will lead in growth with 43.5 percent, followed by Rest of World (primarily Southeast Asia) at 19.3 percent, Japan at 32.1 percent, Europe at 11.6 percent, North America at 3.8 percent and South Korea at 0.1 percent.

SEMI forecasts that, in 2019, equipment sales in China will surge 46.6 percent to $17.3 billion. In 2019, China, South Korea, and Taiwan are forecast to remain the top three markets, with China rising to the top. South Korea is forecast to become the second largest market at $16.3 billion, while Taiwan is expected to reach $12.3 billion in equipment sales.

The following results are in terms of market size in billions of U.S. dollars:

The Equipment Market Data Subscription (EMDS) from SEMI provides comprehensive market data for the global semiconductor equipment market. A subscription includes three reports: the monthly SEMI Billings Report, which offers an early perspective of the trends in the equipment market; the monthly Worldwide Semiconductor Equipment Market Statistics (SEMS), a detailed report of semiconductor equipment bookings and billings for seven regions and over 22 market segments; and the SEMI Mid-year Forecast, which provides an outlook for the semiconductor equipment market. For more information or to subscribe, please contact SEMI customer service at 1.877.746.7788 (toll free in the U.S.). For more information online, visit: http://info.semi.org/semi-equipment-market-data-subscription

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $38.7 billion for the month of May 2018, an increase of 21.0 percent compared to the May 2017 total of $32.0 billion. Global sales in May were 3 percent higher than the April 2018 total of $37.6 billion. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“The global semiconductor market has posted consistent growth of greater than 20 percent for 14 consecutive months, and May 2018 marked the industry’s highest-ever monthly sales,” said John Neuffer, president and CEO, Semiconductor Industry Association. “The Americas led the way once again, with sales increasing by more than 30 percent compared to last year, and sales were up across all major semiconductor product categories on both a year-to-year and month-to-month basis.”

Year-to-year sales increased solidly across all regions: the Americas (31.6 percent), China (28.5 percent), Europe (18.7 percent), Japan (14.7 percent), and Asia Pacific/All Other (8.7 percent). Month-to-month sales increased more modestly across all regions: China (6.3 percent), Japan (2.6 percent), Asia Pacific/All Other (1.2 percent), the Americas (1.1 percent), and Europe (1.0 percent).

If your laptop or cell phone starts to feel warm after playing hours of video games or running too many apps at one time, those devices are actually doing their job.

Whisking heat away from the circuitry in a computer’s innards to the outside environment is critical: Overheated computer chips can make programs run slower or freeze, shut the device down altogether or cause permanent damage.

As consumers demand smaller, faster and more powerful electronic devices that draw more current and generate more heat, the issue of heat management is reaching a bottleneck. With current technology, there’s a limit to the amount of heat that can be dissipated from the inside out.

Researchers at the University of Texas at Dallas and their collaborators at the University of Illinois at Urbana-Champaign and the University of Houston have created a potential solution, described in a study published online July 5 in the journal Science.

Researchers at the University of Texas at Dallas and their collaborators have created and characterized tiny crystals of boron arsenide, like the one shown here imaged with an electron microscope, that have high thermal conductivity. Because the semiconducting material efficiently transports heat, it might be used in future electronics to help keep smaller, more powerful devices from overheating. The research is described in a study published online July 5, 2018 in the journal Science. Credit: University of Texas at Dallas

Bing Lv (pronounced “love”), assistant professor of physics in the School of Natural Sciences and Mathematics at UT Dallas, and his colleagues produced crystals of a semiconducting material called boron arsenide that have an extremely high thermal conductivity, a property that describes a material’s ability to transport heat.

“Heat management is very important for industries that rely on computer chips and transistors,” said Lv, a corresponding author of the study. “For high-powered, small electronics, we cannot use metal to dissipate heat because metal can cause a short circuit. We cannot apply cooling fans because those take up space. What we need is an inexpensive semiconductor that also disperses a lot of heat.”

Most of today’s computer chips are made of the element silicon, a crystalline semiconducting material that does an adequate job of dissipating heat. But silicon, in combination with other cooling technology incorporated into devices, can handle only so much.

Diamond has the highest known thermal conductivity, around 2,200 watts per meter-kelvin, compared to about 150 watts per meter-kelvin for silicon. Although diamond has been incorporated occasionally in demanding heat-dissipation applications, the cost of natural diamonds and structural defects in manmade diamond films make the material impractical for widespread use in electronics, Lv said.

In 2013, researchers at Boston College and the Naval Research Laboratory published research that predicted boron arsenide could potentially perform as well as diamond as a heat spreader. In 2015, Lv and his colleagues at the University of Houston successfully produced such boron arsenide crystals, but the material had a fairly low thermal conductivity, around 200 watts per meter-kelvin.

Since then, Lv’s work at UT Dallas has focused on optimizing the crystal-growing process to boost the material’s performance.

“We have been working on this research for the last three years, and now have gotten the thermal conductivity up to about 1,000 watts per meter-kelvin, which is second only to diamond in bulk materials,” Lv said.

Lv worked with postdoctoral research associate Sheng Li, co-lead author of the study, and physics doctoral student Xiaoyuan Liu, also a study author, to create the high thermal conductivity crystals at UT Dallas using a technique called chemical vapor transport. The raw materials — the elements boron and arsenic — are placed in a chamber that is hot on one end and cold on the other. Inside the chamber, another chemical transports the boron and arsenic from the hot end to the cooler end, where the elements combine to form crystals.

“To jump from our previous results of 200 watts per meter-kelvin up to 1,000 watts per meter-kelvin, we needed to adjust many parameters, including the raw materials we started with, the temperature and pressure of the chamber, even the type of tubing we used and how we cleaned the equipment,” Lv said.

David Cahill and Pinshane Huang’s research groups at the University of Illinois at Urbana-Champaign played a key role in the current work, studying defects in the boron arsenide crystals by state-of-the-art electron microscopy and measuring the thermal conductivity of the very small crystals produced at UT Dallas.

“We measure the thermal conductivity using a method developed at Illinois over the past dozen years called ‘time-domain thermoreflectance’ or TDTR,” said Cahill, professor and head of the Department of Materials Science and Engineering and a corresponding author of the study. “TDTR enables us to measure the thermal conductivity of almost any material over a wide range of conditions and was essential for the success of this work.”

The way heat is dissipated in boron arsenide and other crystals is linked to the vibrations of the material. As the crystal vibrates, the motion creates packets of energy called phonons, which can be thought of as quasiparticles carrying heat. Lv said the unique features of boron arsenide crystals — including the mass difference between the boron and arsenic atoms — contribute to the ability of the phonons to travel more efficiently away from the crystals.

“I think boron arsenide has great potential for the future of electronics,” Lv said. “Its semiconducting properties are very comparable to silicon, which is why it would be ideal to incorporate boron arsenide into semiconducting devices.”

Lv said that while the element arsenic by itself can be toxic to humans, once it is incorporated into a compound like boron arsenide, the material becomes very stable and nontoxic.

The next step in the work will include trying other processes to improve the growth and properties of this material for large scale applications, Lv said.