Category Archives: Semiconductors

SEMICON West next week will host a White House-led discussion of the anticipated national leadership strategy for semiconductors, a multi-agency initiative led by top U.S. government national security and economic organizations.

On Wednesday, July 11, a panel of U.S. officials representing agencies involved in leading the strategy will address federal research and development (R&D), investment and acquisition priorities aimed at ensuring the U.S. remains the global leader in the semiconductor industry.

As global economic trends and technologies such as artificial intelligence evolve, and foreign governments increasingly lure microelectronics manufacturing investments overseas, the U.S. strategy for manufacturing advanced semiconductors and driving research and development (R&D) in technology innovation has become an economic priority.

The White House selected SEMICON West, organized by SEMI, as the site for the discussion and this urgent call to action because of the event’s central role in bringing together critical industries across the global electronics supply chain. The multi-agency panel will outline activities and new policies under development to ensure U.S. strategic leadership in microelectronics, including focused investment in innovations key to the next generation of devices for commercial and government use. The initiative also includes public-private partnerships to accelerate the capabilities of advanced semiconductors for critical applications such as artificial intelligence (AI), cyber, secure communications, the internet of things (IoT) and big data analytics.

PANEL:
National Strategy for Semiconductor and Microelectronic Innovation
TIME AND DATE:
10:30 to 11:30 a.m., Wednesday, July 11
LOCATION:
Yerba Buena Theater, 700 Howard St., San Francisco
MODERATOR:
Dr. Lloyd Whitman, Principal Assistant Director, Physical Sciences and Engineering, White House Office of Science and Technology Policy
PANELISTS:
Dr. Sankar Basu, Program Director, Computer and Information Science and Engineering, National Science Foundation
Dr. Eric W. Forsythe, Flexible Electronics Team Leader, U.S. Army Research Laboratory
Dr. Jeremy Muldavin, Deputy Director of Defense Software & Microelectronics Activities, Office of the Deputy Assistant Secretary of Defense for Systems Engineering
Dr. Robinson Pino, Acting Research Division Director, Advanced Scientific Computing Research, Office of Science, Department of Energy

 

SEMICON West is organized by SEMI Americas to connect more than 2,000 member companies and 1.3 million professionals worldwide to advance the technology and business of electronics manufacturing. SEMICON West is celebrating its 47th year as the flagship event for the semiconductor industry. Find more at www.semiconwest.org.

By integrating the design of antenna and electronics, researchers have boosted the energy and spectrum efficiency for a new class of millimeter wave transmitters, allowing improved modulation and reduced generation of waste heat. The result could be longer talk time and higher data rates in millimeter wave wireless communication devices for future 5G applications.

The new co-design technique allows simultaneous optimization of the millimeter wave antennas and electronics. The hybrid devices use conventional materials and integrated circuit (IC) technology, meaning no changes would be required to manufacture and package them. The co-design scheme allows fabrication of multiple transmitters and receivers on the same IC chip or the same package, potentially enabling multiple-input-multiple-output (MIMO) systems as well as boosting data rates and link diversity.

Researchers from the Georgia Institute of Technology presented their proof-of-concept antenna-based outphasing transmitter on June 11 at the 2018 Radio Frequency Integrated Circuits Symposium (RFIC) in Philadelphia. Their other antenna-electronics co-design work was published at the 2017 and 2018 IEEE International Solid-State Circuits Conference (ISSCC) and multiple peer-reviewed IEEE journals. The Intel Corporation and U.S. Army Research Office sponsored the research.

Georgia Tech researchers are shown with electronics equipment and antenna setup used to measure far-field radiated output signal from millimeter wave transmitters. Shown are Graduate Research Assistant Huy Thong Nguyen, Graduate Research Assistant Sensen Li, and Assistant Professor Hua Wang. (Credit: Allison Carter, Georgia Tech)

“In this proof-of-example, our electronics and antenna were designed so that they can work together to achieve a unique on-antenna outphasing active load modulation capability that significantly enhances the efficiency of the entire transmitter,” said Hua Wang, an assistant professor in Georgia Tech’s School of Electrical and Computer Engineering. “This system could replace many types of transmitters in wireless mobile devices, base stations and infrastructure links in data centers.”

Key to the new design is maintaining a high-energy efficiency regardless whether the device is operating at its peak or average output power. The efficiency of most conventional transmitters is high only at the peak power but drops substantially at low power levels, resulting in low efficiency when amplifying complex spectrally efficient modulations. Moreover, conventional transmitters often add the outputs from multiple electronics using lossy power combiner circuits, exacerbating the efficiency degradation.

“We are combining the output power though a dual-feed loop antenna, and by doing so with our innovation in the antenna and electronics, we can substantially improve the energy efficiency,” said Wang, who is the Demetrius T. Paris Professor in the School of Electrical and Computer Engineering.  “The innovation in this particular design is to merge the antenna and electronics to achieve the so-called outphasing operation that dynamically modulates and optimizes the output voltages and currents of power transistors, so that the millimeter wave transmitter maintains a high energy efficiency both at the peak and average power.”

Beyond energy efficiency, the co-design also facilitates spectrum efficiency by allowing more complex modulation protocols. That will enable transmission of a higher data rate within the fixed spectrum allocation that poses a significant challenge for 5G systems.

“Within the same channel bandwidth, the proposed transmitter can transmit six to ten times higher data rate,” Wang said. “Integrating the antenna gives us more degrees of freedom to explore design innovation, something that could not be done before.”

Sensen Li, a Georgia Tech graduate research assistant who received the Best Student Paper Award at the 2018 RFIC symposium, said the innovation resulted from bringing together two disciplines that have traditionally worked separately.

“We are merging the technologies of electronics and antennas, bringing these two disciplines together to break through limits,” he said. “These improvements could not be achieved by working on them independently. By taking advantage of this new co-design concept, we can further improve the performance of future wireless transmitters.”

The new designs have been implemented in 45-nanometer CMOS SOI IC devices and flip-chip packaged on high-frequency laminate boards, where testing has confirmed a minimum two-fold increase in energy efficiency, Wang said.

The antenna electronics co-design is enabled by exploring the unique nature of multi-feed antennas.

“An antenna structure with multiple feeds allows us to use multiple electronics to drive the antenna concurrently. Different from conventional single-feed antennas, multi-feed antennas can serve not only as radiating elements, but they can also function as signal processing units that interface among multiple electronic circuits,” Wang explained. “This opens a completely new design paradigm to have different electronic circuits driving the antenna collectively with different but optimized signal conditions, achieving unprecedented energy efficiency, spectral efficiency and reconfigurability.”

The cross-disciplinary co-design could also facilitate fabrication and operation of multiple transmitters and receivers on the same chip, allowing hundreds or even thousands of elements to work together as a whole system. “In massive MIMO systems, we need to have a lot of transmitters and receivers, so energy efficiency will become even more important,” Wang noted.

Having large numbers of elements working together becomes more practical at millimeter wave frequencies because the wavelength reduction means elements can be placed closer together to achieve compact systems, he pointed out. These factors could pave the way for new types of beamforming that are essential in future millimeter wave 5G systems.

Power demands could drive adoption of the technology for battery-powered devices, but Wang says the technology could also be useful for grid-powered systems such as base stations or wireless connections to replace cables in large data centers. In those applications, expanding data rates and reducing cooling needs could make the new devices attractive.

“Higher energy efficiency also means less energy will be converted to heat that must be removed to satisfy the thermal management,” he said. “In large data centers, even a small reduction in thermal load per device can add up. We hope to simplify the thermal requirements of these electronic devices.”

In addition to those already mentioned, the research team included Taiyun Chi, Huy Thong Nguyen and Tzu-Yuan Huang, all from Georgia Tech.

The SiC power market is now on the road, asserts Yole Développement (Yole). Therefore, since 2017, the market research and strategy consulting company identified more than 20 strategic announcements, showing the dynamism of this market and attractiveness of the technology. Rohm, Bombardier, Cree, SDK, STMicroelectronics, Infineon Technologies, Littelfuse, Ascatron and more are part of the powerful ecosystem, presenting innovative products and revealing key partnerships and/or M&A .

Today, SiC transistors are clearly being adopted, penetrating smoothly into different applications. Yole’s analysts forecast a US$1.4 billion SiC power semiconductor market by 2023. According to the Power & Wireless team at Yole, this market is showing a 29% CAGR between 2017 and 2023.
Power SiC report, 2018 edition presents Yole’s deep understanding of SiC penetration in different applications including xEV, xEV charging infrastructure, PFC/power supply, PV, UPS, motor drives, wind and rail. In addition, it highlights the state-of-the-art SiC-based devices, modules, and power stacks. Yole’s analysts also describe the SiC power industrial landscape from materials to systems, and analyze of SiC power market dynamics. This report proposes a detailed quantification of the SiC power device market until 2023, in value and volume.

SiC adoption is accelerating: is the supply chain ready? Yole’s analysts reveal today their vision of the SiC industry.

SiC market is still being driven by diodes used in PFC and PV applications. However Yole expects that in five years from now the main SiC device market driver will be transistors, with an impressive 50% CAGR for 2017-2023.

This adoption is partially thanks to the improvement of the transistor performance and reliability compared to the first generation of products, which gives confidence to customers for implementation.

Another key trend revealed by Yole’s analysts is the SiC adoption by automotive players, over the next 5-10 years. “Its implementation rate differs depending on where SiC is being used,” comments Dr. Hong Lin, Technology and Market Analyst, Compound Semiconductors at Yole. “That could be in the main inverter, in OBC or in the DC/DC converter. By 2018, more than 20 automotive companies are already using SiC SBDs or SiC MOSFET transistors for OBC, which will lead to 44% CAGR through to 2023.”

Yole expects SiC adoption in the main inverter by some pioneers, with an inspiring 108% market CAGR for 2017-2023. This will be possible because nearly all carmakers have projects to implement SiC in the main inverter in coming years. In particular, Chinese automotive players are strongly considering the adoption of SiC.

The recent SiC module developed by STMicroelectronics for Tesla and its Model 3 is a good example of this early adoption. The SiC-based inverter, analyzed by System Plus Consulting, Yole’s sister company is composed of 24 1-in-1 power modules. Each module contains two SiC MOSFETs with an innovative die attach solution and connected directly on the terminals with copper clips and thermally dissipated by copper baseplates. The thermal dissipation of the modules is performed thanks to a specifically designed pin-fin heatsink.

“SiC MOSFET is manufactured with the latest STMicroelectronics technology design,” explains Dr. Elena Barbarini, Head of Department Devices at System Plus Consulting. “This technical choice allows reduction of conduction losses and switching losses”. STMicroelectronics is strongly involved in the development of SiC-based modules for the automotive industry. During its recent Capital Markets Day, the leading player details its activities in this field (Source: Automotive & Discrete Group presentation – May 2018). STMicroelectronics is also commited in the development of innovative packaging solutions. . System Plus Consulting proposes today a complete teardown analysis including a detailed estimation of the production cost of the module and its package.

PV has also caught the attention of Yole’s analysts during recent months. China claimed almost the half of the world’s installations in the last year. However due to new governmental regulations, Yole sees a slow down of the PV market in short term and has lowered its expectation of SiC penetration for the segment.

In general, system manufacturers are interested in implementing cost effective systems which are reliable, without any technology choice, either silicon or SiC. “Today, even if it’s certified that SiC performs better than silicon, system manufacturers still get questions about long term reliability and the total cost of the SiC inverter”, comments Ana Villamor, Technology & Market Analyst, Power Electronics & Compound Semiconductors at Yole.

Yole and System Plus Consulting teams will attend SEMICON Europa 2018 (Munich, Germany – November 13-16). During the leading trade show, Dr. Milan Rosina, Senior Technology & Market Analyst, Power Electronics & Batteries at Yole proposes a dedicated WBG presentation on November 15 at 2:30 PM.

SiC and GaN devices have demonstrated their large potential for power electronic applications. During the presentation “GaN and SiC power device: market overview” taken place during the Power Electronics Session, Dr. Rosina proposes an overview of the market, technology and the industrial supply chain. More information available on i-micronews.com, Conferences & Trade Shows section.

There are limits to how accurately you can measure things. Think of an X-ray image: it is likely quite blurry and something only an expert physician can interpret properly. The contrast between different tissues is rather poor but could be improved by longer exposure times, higher intensity, or by taking several images and overlapping them. But there are considerable limitations: humans can safely be exposed to only so much radiation, and imaging takes time and resources.

A well-established rule of thumb is the so-called standard quantum limit: the precision of the measurement scales inversely with the square root of available resources. In other words, the more resources – time, radiation power, number of images, etc. – you throw in, the more accurate your measurement will be. This will, however, only get you so far: extreme precision also means using excessive resources.

A team of researchers from Aalto University, ETH Zurich, and MIPT and Landau Institute in Moscow have pushed the envelope and came up with a way to measure magnetic fields using a quantum system – with accuracy beyond the standard quantum limit.

An artificial atom realised from superconducting strips of aluminum on a silicon chip can be employed for the detection of magnetic fields. Credit: Babi Brasileiro / Aalto University

The detection of magnetic fields is important in a variety of fields, from geological prospecting to imaging brain activity. The researchers believe that their work is a first step towards of using quantum-enhanced methods for sensor technology.

‘We wanted to design a highly efficient but minimally invasive measurement technique. Imagine, for example, extremely sensitive samples: we have to either use as low intensities as possible to observe the samples or push the measurement time to a minimum,’ explains Sorin Paraoanu, leader of the Kvantti research group at Aalto University.

Their paper, published in the prestigious journal npj Quantum Information shows how to improve the accuracy of magnetic field measurements by exploiting the coherence of a superconducting artificial atom, a qubit. It is a tiny device made of overlapping strips of aluminium evaporated on a silicon chip – a technology similar to the one used to fabricate the processors of mobile phones and computers.

When the device is cooled to a very low temperature, magic happens: the electrical current flows in it without any resistance and starts to display quantum mechanical properties similar to those of real atoms. When irradiated with a microwave pulse – not unlike the ones in household microwave ovens – the state of the artificial atom changes. It turns out that this change depends on the external magnetic field applied: measure the atom and you will figure out the magnetic field.

But to surpass the standard quantum limit, yet another trick had to be performed using a technique similar to a widely-applied branch of machine learning, pattern recognition.

‘We use an adaptive technique: first, we perform a measurement, and then, depending on the result, we let our pattern recognition algorithm decide how to change a control parameter in the next step in order to achieve the fastest estimation of the magnetic field,’ explains Andrey Lebedev, corresponding author from ETH Zurich, now at MIPT in Moscow.

‘This is a nice example of quantum technology at work: by combining a quantum phenomenon with a measurement technique based on supervised machine learning, we can enhance the sensitivity of magnetic field detectors to a realm that clearly breaks the standard quantum limit,’ Lebedev says.

There are limits to how accurately you can measure things. Think of an X-ray image: it is likely quite blurry and something only an expert physician can interpret properly. The contrast between different tissues is rather poor but could be improved by longer exposure times, higher intensity, or by taking several images and overlapping them. But there are considerable limitations: humans can safely be exposed to only so much radiation, and imaging takes time and resources.

A well-established rule of thumb is the so-called standard quantum limit: the precision of the measurement scales inversely with the square root of available resources. In other words, the more resources – time, radiation power, number of images, etc. – you throw in, the more accurate your measurement will be. This will, however, only get you so far: extreme precision also means using excessive resources.

A team of researchers from Aalto University, ETH Zurich, and MIPT and Landau Institute in Moscow have pushed the envelope and came up with a way to measure magnetic fields using a quantum system – with accuracy beyond the standard quantum limit.

The detection of magnetic fields is important in a variety of fields, from geological prospecting to imaging brain activity. The researchers believe that their work is a first step towards of using quantum-enhanced methods for sensor technology.

‘We wanted to design a highly efficient but minimally invasive measurement technique. Imagine, for example, extremely sensitive samples: we have to either use as low intensities as possible to observe the samples or push the measurement time to a minimum,’ explains Sorin Paraoanu, leader of the Kvantti research group at Aalto University.

Their paper, published in the prestigious journal npj Quantum Information shows how to improve the accuracy of magnetic field measurements by exploiting the coherence of a superconducting artificial atom, a qubit. It is a tiny device made of overlapping strips of aluminium evaporated on a silicon chip – a technology similar to the one used to fabricate the processors of mobile phones and computers.

When the device is cooled to a very low temperature, magic happens: the electrical current flows in it without any resistance and starts to display quantum mechanical properties similar to those of real atoms. When irradiated with a microwave pulse – not unlike the ones in household microwave ovens – the state of the artificial atom changes. It turns out that this change depends on the external magnetic field applied: measure the atom and you will figure out the magnetic field.

But to surpass the standard quantum limit, yet another trick had to be performed using a technique similar to a widely-applied branch of machine learning, pattern recognition.

‘We use an adaptive technique: first, we perform a measurement, and then, depending on the result, we let our pattern recognition algorithm decide how to change a control parameter in the next step in order to achieve the fastest estimation of the magnetic field,’ explains Andrey Lebedev, corresponding author from ETH Zurich, now at MIPT in Moscow.

‘This is a nice example of quantum technology at work: by combining a quantum phenomenon with a measurement technique based on supervised machine learning, we can enhance the sensitivity of magnetic field detectors to a realm that clearly breaks the standard quantum limit,’ Lebedev says.

A Tokyo Institute of Technology research team has shown copper nitride acts as an n-type semiconductor, with p-type conduction provided by fluorine doping, utilizing a unique nitriding technique applicable for mass production and a computational search for appropriate doping elements, as well as atomically resolved microscopy and electronic structure analysis using synchrotron radiation. These n-type and p-type copper nitride semiconductors could potentially replace the conventional toxic or rare materials in photovoltaic cells.

Thin film photovoltaics have equivalent efficiency and can cut the cost of materials compared to market-dominating silicon solar panels. Utilizing the photovoltaic effect, thin layers of specific p-type and n-type materials are sandwiched together to produce electricity from sunlight. The technology promises a brighter future for solar energy, allowing low-cost and scalable manufacturing routes compared to crystalline silicon technology, even though toxic and rare materials are used in commercialized thin film solar cells. A Tokyo Institute of Technology team has challenged to find a new candidate material for producing cleaner, cheaper thin film photovoltaics.

(a) This is a copper and Copper Nitride. (b) Theoretical Calculation for P-type and N-type Copper Nitride. (c) Direct Observation of Fluorine Position in Fluorine-doped Copper Nitride. (a) An image of thin film copper plates before and after reacting with ammonia and oxygen. Copper metal has been transformed to copper nitride. (b) Copper insertion for an n-type semiconductor and fluorine insertion for a p-type semiconductor. (c) Nitrogen plotted in red, fluorine in green, and copper in blue. Fluorine is located at the open space of the crystal as predicted by the theoretical calculation. Credit: Advanced Materials

They have focused on a simple binary compound, copper nitride that is composed of environmentally friendly elements. However, growing a nitride crystal in a high quality form is challenging as history tells us to develop gallium nitride blue LEDs. Matsuzaki and his coworkers have overcome the difficulty by introducing a novel catalytic reaction route using ammonia and oxidant gas. This compound, pictured through the photograph in figure (a), is an n-type conductor that has excess electrons. On the other hand, by inserting fluorine element in the open space of the crystal, they found this n-type compound transformed into p-type as predicted by theoretical calculations and directly proven by atomically resolved microscopy in figures (b) and (c), respectively.

All existing thin film photovoltaics require a p-type or n-type partner in their makeup of a sandwich structure, requiring huge efforts to find the best combination. P-type and n-type conduction in the same material developed by Matsuzaki and his coworkers are beneficial to design a highly efficient solar cell structure without such efforts. This material is non-toxic, abundant, and therefore potentially cheap–ideal replacements for in use cadmium telluride and copper indium gallium diselenide thin film solar cells. With the development of these p-type and n-type semiconductors, in a scalable forming technique using simple safe and abundant elements, the positive qualities will further bring thin film technology into the light.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today unveiled the new SmartView® NT3 aligner, which is available on the company’s industry benchmark GEMINI® FB XT integrated fusion bonding system for high-volume manufacturing (HVM) applications. Developed specifically for fusion and hybrid wafer bonding, the SmartView NT3 aligner provides sub-50-nm wafer-to-wafer alignment accuracy — a 2-3X improvement — as well as significantly higher throughput (up to 20 wafers per hour) compared to the previous-generation platform.

With the new SmartView NT3 aligner, the GEMINI FB XT provides integrated device manufacturers, foundries and outsourced semiconductor assembly and test providers (OSATs) with wafer bonding performance that is unmatched in the industry and can meet their future 3D-IC packaging requirements. Applications enabled by the enhanced GEMINI FB XT include memory stacking, 3D systems on chip (SoC), backside illuminated CMOS image sensor stacking, and die partitioning.

The new SmartView® NT3 aligner on EV Group’s GEMINI® FB XT fusion bonder enables a 2-3X improvement in wafer-to-wafer alignment accuracy over EVG’s previous-generation aligner.

Wafer Bonding an Enabling Process for 3D Device Stacking

Vertical stacking of semiconductor devices has become an increasingly viable approach to enabling continuous improvements in device density and performance. Wafer-to-wafer bonding is an essential process step to enable 3D stacked devices. However, tight alignment and overlay accuracy between the wafers is required to achieve good electrical contact between the interconnected devices on the bonded wafers, as well as to minimize the interconnect area at the bond interface so that more space can be made available on the wafer for producing devices. The constant reduction in pitches that are needed to support component roadmaps is fueling tighter wafer-to-wafer bonding specifications with each new product generation.

“At imec, we believe in the power of 3D technology to create new opportunities and possibilities for the semiconductor industry, and we are devoting a great deal of energy into improving it,” stated Eric Beyne, imec fellow and program director 3D system integration. “One area of particular focus is wafer-to-wafer bonding, where we are achieving excellent results in part through our work with industry partners such as EV Group. Last year, we succeeded in reducing the distance between the chip connections, or pitch, in hybrid wafer-to-wafer bonding to 1.4 microns, which is four times smaller than the current standard pitch in the industry. This year we are working to reduce the pitch by at least half again.”

“EVG’s GEMINI FB XT fusion bonding system has consistently led the industry in not only meeting but exceeding performance requirements for advanced packaging applications, with key overlay accuracy milestones achieved with several industry partners within the last year alone,” stated Paul Lindner, executive technology director, EV Group. “With the new SmartView NT3 aligner specifically engineered for the direct bonding market and added to our widely adopted GEMINI FB XT fusion bonder, EVG once again redefines what is possible in wafer bonding — helping the industry to continue to push the envelope in enabling stacked devices with increasing density and performance, lower power consumption and smaller footprint.”

The GEMINI FB XT fusion bonder with new SmartView NT3 aligner is available for customer demonstrations and testing. More information on the product can be found on EVG’s website at https://www.evgroup.com/en/products/bonding/integrated_bonding/geminifb/.

EVG will showcase the GEMINI FB XT with new SmartView NT3 aligner, along with its complete suite of wafer bonding, lithography and resist processing solutions for advanced packaging applications, at SEMICON West, to be held July 10-12 at the Moscone Convention Center in San Francisco, Calif. Attendees interested in learning more can visit EVG at Booth #623 in the South Hall.

In addition, Dr. Thomas Uhrmann, director of business development at EV Group, will highlight the GEMINI FB XT and other developments in wafer bonding in his presentation “Collective Bonding for Heterogeneous Integration in Advanced Packaging” at the Meet the Experts Theater Smart Manufacturing Pavilion at SEMICON West on Thursday, July 12 from 3:00-3:30 p.m. in the South Hall.

Global semiconductor industry revenue declined 3.4 percent in the first quarter of 2018 falling to $115.8 billion. Semiconductor industry performance was negatively affected by the declining sales and first-quarter seasonality in the wireless communications market. Other sectors, such as automotive and consumer semiconductors, experienced nominal market growth, according to IHS Markit (Nasdaq: INFO).

The memory category experienced the highest growth of 1.7 percent in the first quarter, reaching $39.7 billion, as demand for memory components increased in the enterprise and storage markets. In fact, DRAM pricing and shipments both increased during the quarter, as strong demand for server DRAM continued to propel the semiconductor market. However, NAND began to show signs of softening, with slight revenue declines during the quarter, mainly due to single-digit price declines. “Even with the slight revenue decline during the quarter, the NAND market still achieved its second-highest revenue quarter on record, with strong demand coming from the enterprise and client solid-state drive markets,” said Craig Stice, senior director, memory and storage, IHS Markit.

Semiconductor market share

Led by its dominant position in the memory market, Samsung Electronics led the semiconductor industry in the first quarter of 2018, with 16.1 percent of the market, followed by Intel at 13.6 percent and SK Hynix at 7.0 percent. Quarter-over-quarter market shares were relatively flat, with no change in the top-three ranking list. However, on a year-over-year basis, Samsung supplanted Intel as the leading semiconductor company, compared to the first quarter of 2017.

Analog component sales for Texas Instruments, Maxim Integrated, ON Semiconductor and other companies with a strategic focus on industrial and automotive industries managed single-digit sales increases in the first quarter. In contrast, analog component revenue declined by double digits for Qualcomm, Skyworks Solutions, Oorvo and other companies targeting the wireless industry.

Memory IC companies — Samsung Electronics, SK Hynix, Micron Technologies and Toshiba — continued to dominate the top ten semiconductor companies. Micron achieved the highest growth rate in the top ten, recording 9.8 percent growth in the first quarter, compared to the previous quarter. Qualcomm revenue fell 13.6 percent, which was the largest sequential drop, due to the weakness in the wireless communication market. Qualcomm and nVidia were the only two fabless companies remaining in the top ten.

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its full-flow digital and signoff tools have achieved certification for Samsung Foundry’s 7-nanometer (nm) Low Power Plus (LPP) process technology. The Cadence® tools were certified for the Process Design Kit (PDK) and foundation library on the 7LPP process and confirmed to meet Samsung Foundry’s accuracy requirements, enabling systems and semiconductor companies to accelerate the delivery of 7LPP designs.

The Cadence RTL-to-GDSII design flow that has been certified for the 7LPP process technology is based on the Design Methodology (DM) of Samsung Foundry using an OpenRISC OR1200 design.

The Cadence digital and signoff tools are available via a quick-start kit. The certified tools include the Innovus™ Implementation System, Genus™Synthesis Solution, Joules™ RTL Power Solution, Conformal® Equivalence Checking, Conformal Low Power, Modus™ DFT Software Solution, Voltus™IC Power Integrity Solution, Tempus™ Timing Signoff Solution, Quantus™ Extraction Solution, Cadence Physical Verification System (PVS), Cadence CMP Predictor (CCP) and Cadence Litho Physical Analyzer (LPA).

“Our 7LPP process provides the best power, performance and area that we have seen so far in advanced FinFET nodes, and we expect this will provide great benefits for our mutual customers’ next generation SoC designs,” said Ryan Sanghyun Lee, vice president of the Foundry Marketing at Samsung Electronics. “By working closely with Cadence, we have been able to ensure that our customers can get these benefits quickly and easily using the certified Cadence digital and signoff full flow.”

“Using our full RTL-to-GDSII reference flow, our customers can take advantage of the advanced-node innovation provided in the 7LPP process,” said KT Moore, vice president, product management in the Digital & Signoff Group at Cadence. “Our ongoing collaboration with Samsung Foundry enables us to provide the tools our customers require to quickly complete the most complex designs.”

Alta Devices has today announced that its most recent single junction solar cell has been certified by NREL (National Renewable Energy Laboratory) as being 28.9% efficient. This certification confirms that Alta has set a new record and continues to hold the world record efficiency for this type of solar cell. This breakthrough, combined with the unique thinness and flexibility of Alta’s cells, redefines how solar technology can be used to empower autonomy in many applications.

“Alta Devices goal is to continue to lead the industry in solar technology and to enable a broad range of autonomous systems. We believe this is the best way to support the innovations of our customers,” said Jian Ding, Alta Devices CEO.

Autonomous systems are predicted to become a part of daily life – often operating without human intervention. However, every time an autonomous system or vehicle has to stop to refuel or recharge, it requires intervention and is no longer truly autonomous. Alta focuses on developing the world’s best solar technology specifically for autonomous power, allowing vehicles to seamlessly recharge while in motion.

Alta Devices has held continuous world records for solar efficiency for most of the last decade. Alta Devices Founders, Professor Harry Atwater of Caltech and Professor Eli Yablonovitch of the University of California Berkeley explained the significance of this record:

Prof. Atwater said, “Achieving a new record for this class of devices is a landmark because a 1-sun, 1-junction cell is the archetypal solar cell. The fact that Alta is breaking its own record is also significant since many other teams have been actively attempting to break this record.”

Elaborating on the fundamental technical understanding that has driven this achievement, Professor Yablonovitch said, “Alta has the first solar cell based on Internal Luminescence Extraction, which has enabled Alta to remain ahead of others. This scientific principle will be in all future high efficiency solar cells.”

The company has recently launched its Gen4 AnyLight™ commercial technology, demonstrating a significant weight reduction from the previous version, resulting in an improved power to weight ratio of 160 percent. This is critical for tomorrow’s autonomous UAVs (unmanned aerial vehicles), electric vehicles, and sensors. It can be used to generate substantial power over small surfaces without compromising design criteria.