Category Archives: Semiconductors

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, this week released the following statement regarding the Trump Administration’s announcement on tariffs on products imported from China.

“While the U.S. semiconductor industry shares the Trump Administration’s concerns about China’s forced technology transfer and intellectual property (IP) practices, the proposed imposition of tariffs on semiconductors from China, most of which are actually researched, designed, and manufactured in the U.S., is counterproductive and fails to address the serious IP and industrial policy issues in China. We look forward to working with the Administration to explain why imposing tariffs on our products would be harmful to our competitiveness and does not address our challenges with China.”

SIA seeks to strengthen U.S. leadership of semiconductor manufacturing, design, and research by working with Congress, the Administration and other key industry stakeholders to encourage policies and regulations that fuel innovation, propel business and drive international competition. Learn more at www.semiconductors.org.

Scientists of the Far Eastern Federal University (FEFU) in cooperation with colleagues from the Russian Academy of Sciences (RAS), Australian and Lithuanian Universities have improved the technique of ultrasensitive nonperturbing spectroscopic identification of molecular fingerprints.

A group of physicists experimentally confirmed that molecular fingerprints of toxic, explosive, polluting and other dangerous substances could be reliably detected and identified by surface-enhanced Raman spectroscopy (SERS) using black silicon (b-Si) substrate. The results of the work are published in the authoritative scientific journal Nanoscale.

The needle-shaped surface structure of black silicon where needles are made of single-crystal silicon. The nanomaterial is absolutely chemically inert, non-invasive, and could support a strong and non-distorted signal Credit: FEFU press office

“When detecting the smallest molecules using SERS spectroscopy their interaction with the nanostructured substrate – the platform allowing ultrasensitive identification – is crucial”, the head of research team Alexander Kuchmizhak, Ph.D., reported. Alexander is a researcher of the Department of Theoretical and Nuclear Physics of the School of Natural Sciences of the FEFU. He also added: “Currently noble metals-based substrates are chemically active and as a result, they distort the characteristic molecules signals.”

“Due to its’ special morphology black silicon significantly enhances the signal from the molecules wanted. This nanomaterial doesn’t support catalytic conversion of the analyte as it could be in the case of the metal-based substrates applying. The ‘black silicon’- based substrate is unique: being absolutely chemically inert and non-invasive it could support a strong and non-distorted signal,” told Alexander Kuchmizhak.

The substrate can be fabricated by using the easy-to-implement scalable technology of plasma etching, thus has good prospects for commercial implementation. Such inexpensive non-metallic substrates with high accuracy of detection can be promising for routine SERS applications, where the non-invasiveness is of high importance.

Valuable properties of black silicon were discovered thanks to extensive scientific cooperation. Samples of the material were developed and provided by Australian colleagues, experimental work was carried out in the laboratories of the Institute of Chemistry and the Institute of Automation and Control Processes of the Far Eastern Branch of the RAS, as well as in the Scientific and Educational Center “Nanotechnologies” of the Engineering School of the FEFU.

The way that electrons paired as composite particles or arranged in lines interact with each other within a semiconductor provides new design opportunities for electronics, according to recent findings in Nature Communications.

What this means for semiconductor components, such as those that send information throughout electronic devices, is not yet clear, but hydrostatic pressure can be used to tune the interaction so that electrons paired as composite particles switch between paired, or “superconductor-like,” and lined-up, or “nematic,” phases. Forcing these phases to interact also suggests that they can influence each other’s properties, like stability – opening up possibilities for manipulation in electronic devices and quantum computing.

Two different kinds of electron arrangements in a semiconductor, paired as composite particles or lined-up, can interact with and tweak each other in the presence of hydrostatic pressure. Credit: Purdue University image/Gábor Csáthy

“You can literally have hundreds of different phases of electrons organizing themselves in different ways in a semiconductor,” said Gábor Csáthy, Purdue professor of physics and astronomy. “We found that two in particular can actually talk to each other in the presence of hydrostatic pressure.”

Csáthy’s group discovered that hydrostatic pressure, which is 10,000 times stronger than ambient pressure, compresses the lattice of atoms in a semiconductor and, therefore, influences the electron arrangement within a two-dimensional electron gas hosted by the semiconductor. The strength of the pressure determines which arrangement is favored and tunes the transition between the paired and lined-up phases, making them more tailorable for an application. Of the two phases, the paired phase may support a certain type of quantum computing.

“We can also tune the interaction by engineering the semiconductor,” Csáthy said. “Say, for example, we grew a semiconductor with a particular width and electron density that we estimated could stabilize the nematic phase. Then we’ve tuned the electron-electron interaction as a result.”

Michael Manfra, Purdue professor of physics and astronomy, electrical and computer engineering and materials engineering, and researchers Loren Pfeiffer and Kenneth West at Princeton University grew the semiconductor samples for this study. Yuli Lyanda-Geller, Purdue associate professor of physics and astronomy, provided theoretical support for the understanding on how these electron-electron interactions took place.

North America-based manufacturers of semiconductor equipment posted $2.70 billion in billings worldwide in May 2018 (three-month average basis), according to the May Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI. The billings figure is 0.6 percent higher than the final April 2018 level of $2.69 billion, and is 19.2 percent higher than the May 2017 billings level of $2.27 billion.

“May 2018 monthly global billings of North American equipment manufacturers exceeded last month’s level to set yet another record,” said Ajit Manocha, president and CEO of SEMI. “Demand for semiconductor equipment remains strong on the back of smart, data-centric applications such as artificial intelligence (AI), Internet of Things (IoT), big data, and edge computing.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.
Billings
(3-mo. avg)
Year-Over-Year
December 2017
$2,398.4
28.3%
January 2018
$2,370.1
27.5%
February 2018
$2,417.8
22.5%
March 2018
$2,431.8
16.9%
April 2018 (final)
$2,689.9
25.9%
May 2018 (prelim)
$2,705.8
19.2%

Source: SEMI (www.semi.org), June 2018

At this week’s 2018 Symposia on VLSI Technology and Circuits, imec, the research and innovation hub in nanoelectronics and digital technology presented considerable progress in enabling germanium nanowire pFET devices as a practical solution to extend scaling beyond the 5nm node. In a first paper, the research center unveiled an in-depth study of the electrical properties of strained germanium nanowire pFETs. A second paper presents the first demonstration of vertically-stacked gate-all-around highly-strained germanium nanowire pFETs.

“With a number of scaling boosters, the industry will be able to extend FinFET technology to the 7- or even 5nm node,” says An Steegen, EVP at imec’s Semiconductor Technology and Systems division. “Beyond, the gate-all-around (GAA) architecture appears as a practical solution since it reuses most of the FinFET process steps. But one important challenge of using lateral nanowires is the significant decrease of the channel cross-section compared to conventional FinFETs. To improve the drive per footprint, several nanowires have to be stacked, but this comes with a serious penalty of increased parasitic capacitance and resistance. A solution is to replace the silicon nanowires by a high-mobility channel material such as germanium (Ge), providing the necessary current boost per footprint”, adds Steegen, “These new studies show that solution is indeed feasible, reaching the cost, area and performance requirements for nodes beyond 5nm.”

The first study of high-performing strained Ge nanowire pFETs gives insight in the device performance these new devices may offer for high-end analog and high-performance digital solutions. One conclusion is that dedicated optimizations of key process steps make these devices a serious contender for the GAA technology. The second paper reports on Ge GAA FETs with single nanowires, achieving a performance that matches state-of-the-art SiGe and Ge FinFETs. Moreover, for the first time, strained p-type Ge GAA FETs with stacked nanowires were demonstrated on a 14/16nm platform. The GAA nanowire technology appears as a promising high-performance solution for future nodes, provided that the junctions are further optimized.

“These complimentary studies establish germanium GAA nanowire technology as a valid contender for the sustained scaling that will be required to fulfill the requirements for the data-driven IoT-era requiring huge computational power,” concludes Steegen.

These results will be presented on June 20 at the VLSI Technology Symposium, in session T8: Advanced FinFET and GAA. This research is performed in cooperation with imec’s key program partners including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions, TOSHIBA Memory, TSMC and Western Digital.

FormFactor, Inc. (NASDAQ:FORM), an electrical test and measurement supplier to the semiconductor industry, announced today the company has deployed an integrated CM300xi probing solution for wafer-level testing of silicon photonics (SiPh) devices. Teams from GLOBALFOUNDRIES, FormFactor and Keysight worked together to ensure the system is flexible to meet engineering needs and to deliver high throughput in volume production.

Silicon photonics can enable the transfer of enormous amounts of data at high speeds using optical signals instead of electrical signals. The silicon photonics market is gaining momentum for data center, automotive, and other applications because it allows optical devices to be made cost effectively –reducing power and size — using silicon semiconductor fabrication techniques. The global silicon photonics market is expected to grow at a CAGR of 22.3% between 2017 and 2025, according to Inkwood Research.

The Cascade CM300xi from FormFactor, combined with Keysight Technologies’ Photonics Application Suite measurement software, provides industry-first capabilities of automated alignment and simultaneous optical-optical and optical-electrical device tests.  Key features of the system include:

  • Six-axis automated optical fiber positioning for precision alignment
  • Two-stage solution for both coarse and fine alignment
  • Optical alignment algorithms integrated with high-speed hardware control to shorten test times
  • FormFactor’s SiPh software to simplify integration with Keysight’s Photonics Applications Suite and optical instrumentation
  • Customized scripting and test programs to optimize the system for fast, accurate measurements
  • Keysight’s high speed, single sweep polarization-dependent-loss (PDL) test that enables high accuracy and repeatability testing without prior polarization alignment.

“GF’s silicon photonics leverages standard silicon manufacturing techniques to improve production efficiency and reduce cost for customers deploying optical interconnect systems,” said Jeffrey Lam, Vice President of product, test and failure analysis, at GF. “We’re excited to be at the forefront in deploying new test capabilities, including wafer level solutions to ramp this important technology.”

“With our long history of working with FormFactor to deliver wafer measurement solutions and decades of experience in photonic testing we are pleased to further equip the silicon photonics industry,” said Joachim Peerlings, Vice President and General Manager Networks & Data Centers, Keysight Technologies. “With Keysight’s Photonics Application Suite and instrumentation, we’ve built a proven, integrated measurement system that enables customers to quickly develop test routines that provide deep insight into photonics devices during R&D and design validation and has the flexibility and scalability for cost effective high-volume production.”

“Emerging technologies like silicon photonics offer FormFactor the opportunity to develop fully integrated probe systems. GF is a forward-thinking company in their adoption of these new test technologies,” said Mike Slessor, President and CEO of FormFactor. “Our collaboration with both Keysight and GF Singapore delivers a solution that truly addresses the unique test and measurement challenges of silicon photonics devices.”

An international team of scientists, including NUST MISIS’s Professor Gotthard Seifert, have made an important step towards the control of excitonic effects in two-dimensional van der Waals heterostructures. In the future, this research will help to create electronics with more controlled properties. The research has been published in Nature Physics.

The creation of two-dimensional semiconductor materials is one of the most important areas of modern materials science. These materials can be the basis for elements needed to create the next generation of electronics.

One two-dimensional material with suitable electronic characteristics is two-dimensional molybdenum disulfide (MoS2), which has a single-layer structure (one atom layer) of molybdenum located between two sulfur layers: this material has a high charge mobility and high on/off in the transistor element.

In 2017, Professor Gotthard Seifert described the mechanism of defect germination in the structure of two-dimensional molybdenum disulfide as a process that will make it possible for scientists to capitalize on two-dimensional MoS2’s full potential use in microelectronics. This work was published in the leading journal, ACS Nano.

The study of other two-dimensional materials’ properties for their application in electronics has become the next step in this field. Monolayers of molybdenum disulfide (and, for example, wolframite diselenides–WSe2) have shown exceptional optical properties due to excitons: tightly bound pairs of electron-hole (quasiparticles acting as a carrier of a positive charge).

At the same time, the creation of the MoS2/WSe2 heterostructure by laying separate monolayers on each other leads to the appearance of a new type of exciton in it, where the electron and the hole are spatially divided into different layers.

Scientists have shown that interlayer excitons give a very specific optical signal display when layered. This allow scientists to study quantum phenomena, making it ideal for experiments in volitronics (a field of quantum electronics, «valley», or the local minimum of an element’s conduction zone) to control electrons in the «valleys» of semiconductors. In the future, these breakthroughs could lead to the most effective way to code information (by placing an electron in one of these valleys).

“Thanks to the use of spectroscopic methods and quantum-chemical calculations from the first principles, we have revealed a partially charged electron-hole in MoS2/WSe2 heterostructures, as well as [the electron-hole’s] location. We have managed to control the radiation energy of this new exciton by changing the relative orientation of the layers”, commented Professor Gotthard Seifert, one of NUST MISIS`s leading scientists.

According to Seifert, this result is an important step towards understanding and controlling exciton effects in Van der Waals heterostructures (where these distance-dependent atomic interactions occur). The research team is continuing to study the effect of layer rotations on the material’s electronic properties. In the future, this will allow for the creation of unique new materials for solar panels or electronics.

At this week’s 2018 Symposia on VLSI Technology and Circuits, imec, the world-leading research and innovation hub in nanoelectronics and digital technology, demonstrates for the first time the possibility to fabricate spin-orbit torque MRAM (SOT-MRAM) devices on 300mm wafers using CMOS compatible processes. With an unlimited endurance (>5×1010), fast switching speed (210ps), and power consumption as low as 300pJ, the SOT-MRAM devices manufactured in a 300mm line achieve the same or better performance as lab devices. This next-generation MRAM technology targets replacement of L1/L2 SRAM cache memories in high-performance computing applications.

SOT-MRAM has recently emerged as a non-volatile memory technology that promises a high endurance and low-power, sub-ns switching speed. With these properties, it can potentially overcome the limitations of spin-transfer torque MRAM (STT-MRAM) for L1/L2 SRAM cache memory replacement. But so far, SOT-MRAM devices have only been demonstrated in the lab. Imec has now for the first time proven full-scale integration of SOT-MRAM device modules on 300mm wafers using CMOS-compatible processes.

At the core of the SOT-MRAM device is a magnetic tunnel junction in which a thin dielectric layer is sandwiched between a magnetic fixed layer and a magnetic free layer. Similar as for STT-MRAM operation, writing of the memory is performed by switching the magnetization of this free magnetic layer, by means of a current. In STT-MRAM, this current is injected perpendicularly into the magnetic tunnel junction, and the read and write operation is performed through the same path – challenging the reliability of the device. In an SOT-MRAM device, on the contrary, switching of the free magnetic layer is done by injecting an in-plane current in an adjacent SOT layer – typically made of a heavy metal. Because of the current injection geometry, the read and write path are de-coupled, significantly improving the device endurance and read stability.

Imec has compared SOT and STT switching behavior on one and the same device, fabricated on 300mm wafers. While switching speed during STT-MRAM operation was limited to 5ns, reliable switching down to 210ps was demonstrated during SOT-MRAM operation. The SOT-MRAM devices show unlimited endurance (>5×1010) and operation power as low as 300pJ. In these devices, the magnetic tunnel junction consists of a SOT/CoFeB/MgO/CoFeB/SAF perpendicularly magnetized stack, using beta-phase tungsten (W) for the SOT layer.

“STT-MRAM technology has a high potential to replace L3 cache memory in high-performance computing applications”, says Gouri Sankar Kar, Distinguished Member of Technical Staff at imec. “However, due to the challenging reliability and increased nergy at sub-ns switching speeds, they are unsuitable to replace the faster L1/L2 SRAM cache memories. SOT-MRAM technology will help us to expand MRAM operation into the SRAM application domain. By moving this next-generation MRAM technology out of the lab, we have now demonstrated the maturity of the technology.” Future work will focus on further reducing the energy  consumption, by bringing down current density and by demonstrating field-free switching operation.

These results will be presented at the VLSI Circuits Symposium on June 20 in the session C8 Emerging Memory. Imec’s research into advanced memory is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Huawei, Micron, Qualcomm, Sony Semiconductor Solutions, TSMC and Western Digital.

Qualcomm Incorporated (NASDAQ: QCOM) today announced that Qualcomm River Holdings B.V., an indirect wholly owned subsidiary of Qualcomm, has extended the offering period of its previously announced cash tender offer to purchase all of the outstanding common shares of NXP Semiconductors N.V. (NASDAQ: NXPI). The tender offer is being made pursuant to the Purchase Agreement, dated as of October 27, 2016, by and between Qualcomm River Holdings B.V. and NXP, as amended (the “Purchase Agreement”). The tender offer is now scheduled to expire at 5:00 p.m., New York City time, on June 22, 2018, unless extended or earlier terminated, in either case pursuant to the terms of the Purchase Agreement.

American Stock Transfer & Trust Company, LLC, the depositary for the tender offer, has advised Qualcomm River Holdings B.V. that as of 5:00 p.m., New York City time, on June 14, 2018, the last business day prior to the announcement of the extension of the offer, 16,319,317 NXP common shares (excluding 21,739 shares tendered pursuant to guaranteed delivery procedures that have not yet been delivered in settlement or satisfaction of such guarantee), representing approximately 4.7% of the outstanding NXP common shares, have been validly tendered pursuant to the tender offer and not properly withdrawn. Shareholders who have already tendered their common shares of NXP do not have to re-tender their shares or take any other action as a result of the extension of the expiration date of the tender offer.

Completion of the tender offer remains subject to additional conditions described in the tender offer statement on Schedule TO filed by Qualcomm River Holdings B.V. with the U.S. Securities and Exchange Commission on November 18, 2016, as amended (the “Schedule TO”). The tender offer will continue to be extended until all conditions are satisfied or waived, or until the tender offer is terminated, in either case pursuant to the terms of the Purchase Agreement by and between Qualcomm River Holdings B.V. and NXP and as described in the Schedule TO.

Micross, headquartered in Orlando, FL announced a new appointment within the company’s senior management team. Marshall (Mac) Blythe has joined Micross in the role of General Manager of Component Modification Services (CMS) located in Hatfield, PA.

Mac brings more than twenty-five years leadership experience in a variety of business development, operations & executive management roles to Micross. His career has been primarily focused in the Electronic Manufacturing Services industry, supporting customers across the Aerospace & Defense, Industrial, Healthcare and Communication sectors.

Mac comes to Micross from Creation Technologies where he served as Vice President, Business Development for Eastern North America. Previously, Mac was President of Accuspec Electronics (now 4Front Solutions) where he successfully led the team to accelerate revenue growth through improving the company’s operational effectiveness, manufacturing productivity and quality. Mac also spent over 12 years at Celestica, where he held key general management and senior sales leadership roles.

Mac earned his M.B.A. from the University of Chicago and holds a BA from UNC, Chapel Hill, NC.

“We are delighted to welcome Mac to the Micross team,” stated Richard Kingdon, CEO of Micross. “We are confident that Mac’s combination of leadership skills and industry experience will both drive Micross’ Component Modification business forward and enhance the effectiveness of our broader organization.”

Micross is the one-source, one-solution provider of Bare Die & Wafers, Advanced Interconnect Technology, Custom Packaging & Assembly, Component Modification Services, Electrical & Environmental Testing and Hi-Rel Products to manufacturers and users of semiconductor devices.