Category Archives: Semiconductors

SEMI, the global industry association representing the electronics manufacturing supply chain, today reported that worldwide semiconductor manufacturing equipment billings reached a historic quarterly high of US$17.0 billion for the first quarter of 2018, surging 59 percent in March to end the quarter with an all-time monthly high of $7.8 billion.

The US$17.0 billion in quarterly billings shatters the previous record set in the fourth quarter of 2017. First quarter 2018 billings are 12 percent higher than the previous quarter and 30 percent higher than the same quarter a year ago. The data are gathered jointly with the Semiconductor Equipment Association of Japan (SEAJ) from over 95 global equipment companies that provide data on a monthly basis.

The quarterly billings data by region in billions of U.S. dollars, quarter-over-quarter growth and year-over-year rates by region are as follows:
1Q2018
4Q2017
1Q2017
1Q18/4Q17
(Qtr-over-Qtr)
1Q18/1Q17
(Year-over-Year)
Korea
6.26
4.64
3.53
35%
78%
China
2.64
1.77
2.01
49%
31%
Taiwan
2.27
2.89
3.48
-22%
-35%
Japan
2.13
1.96
1.25
9%
70%
Europe
1.28
1.04
0.92
23%
39%
Rest of World
1.27
1.22
0.63
4%
103%
North America
1.14
1.58
1.27
-28%
-10%
Total
16.99
15.10
13.08
12%
30%

Source: SEMI (www.semi.org) and SEAJ, June 2018

 

The Equipment Market Data Subscription (EMDS) from SEMI provides comprehensive market data for the global semiconductor equipment market. A subscription includes three reports: the monthly SEMI Billings Report, which offers a perspective of the trends in the equipment market; the monthly Worldwide Semiconductor Equipment Market Statistics (WWSEMS), a detailed report of semiconductor equipment billings for seven regions and 24 market segments; and the SEMI Semiconductor Equipment Forecast, which provides an outlook for the semiconductor equipment market. For more information or to subscribe, please contact SEMI customer service at 1.877.746.7788 (toll free in the U.S.) or 1.408.943.6901 (International Callers). More information is also available online: www.semi.org/en/MarketInfo/EquipmentMarket.

BISTel, a provider of intelligent, real-time data management, advanced analytics and predictive solutions for smart manufacturing announced today an innovative new Chamber Matching (CM) application that enables semiconductor manufacturers to better guard against events that negatively impact yield.

For semiconductor wafer manufacturers, optimizing wafer chamber performance is critical to ensuring high quality, high yield wafers. For customers to achieve this goal and maximize the performance of their fleet, analyzing variations in chamber performance and quickly recognizing which parameters are changing over time is critical to assuring the maximum possible yield from each chamber. BISTel’s new Chamber Matching (CM) application enables customers to quickly determine the best performing chamber – often referred to as the reference chamber or golden chamber. Customers can then compare the reference chamber to all other chambers to help maximize performance.

“CM is the second of four exciting new intelligent manufacturing solutions we have introduced to the market, and that will have an immediate impact on our customers wafer quality and yield,” noted W.K. Choi, Founder and CEO, BISTel. “With these advance new tools, we can perform real time monitoring and analysis to quickly identify the golden chamber and provide our customers the opportunity to maximize the performance of their equipment and processes.”

Key Features and Benefits

BISTel’s new Chamber Matching (CM) solution quickly identifies mis-matching and drifting sensors and it can analyze an unlimited number of chambers simultaneously. In addition, CM:

  • Provides real time monitoring to improve quality and yield.
  • Executes statistical analysis to quickly identify the best performing chamber or “Golden Chamber.”
  • Performs full trace analysis on all sensors and ranks chambers and parameters worse to best.
  • Enables customers to easily conduct time-based, chamber performance analysis.
  • Is completely FDC system independent

BISTel is a provider of real-time, intelligent manufacturing solutions that collect and manage big data, monitor the health of equipment, optimize process flows, analyze large data and quickly identify root cause failures to mitigate risk. BISTel solutions help customers reduce costs, improve quality, and increase yield. Founded in 2000, BISTel has more than 340 employees worldwide. The company is headquartered in South Korea, with offices in California, China, Singapore and Texas. BISTel has a deep customer following in semiconductor, FPD, and PCB/SMT manufacturing as well as automotive, Biotech and steel manufacturing. Its new A.I. based manufacturing intelligence platform will include new auto learning, predictive, self-healing, and continuous improvement features that accelerate smart manufacturing. For more information visit bistel.com

Ultra Clean Holdings, Inc. (Nasdaq: UCTT), a developer and supplier of critical subsystems for the semiconductor and display capital equipment industries, today announced that Ernest Maddock has joined the Board of Directors effective June 1, 2018. Mr. Maddock’s nearly 40 years of experience includes senior leadership roles in finance, operations, and general management. He recently retired as the SVP & CFO of Micron Technology, one of the largest memory chip makers in the world, reporting $20.3 billion in net sales for its fiscal year ended August 31, 2017.

“We are very pleased to announce that Ernie is joining the UCT board of directors. His extensive experience in the semiconductor industry and with UCT makes him a very valuable addition to the board,” said Clarence Granger, Chairman of the Board.

Prior to joining Micron in 2015, Mr. Maddock held leadership positions at multiple global companies including Riverbed Technology, where he served as Executive VP and CFO from April 2013 to April 2015. In that role, he was also responsible for worldwide operations and information technology. Prior to Riverbed, he spent 15 years at Lam Research Corporation rising to EVP & CFO in 2008 and serving in that role until April 2013. His previous roles at Lam included VP, Customer Support Business Group; Group VP and Senior VP of Global Operations.

“We are delighted to have Ernie join our board and benefit from his significant experience and success in business, operations and finance within the Semiconductor industry,” said Jim Scholhamer, President & CEO. “Ernie brings a wealth of knowledge that will be extremely valuable to UCT and its shareholders as we continue to execute on our growth strategy in this exciting market.”

Mr. Maddock has public company board and audit committee experience. He served as a member of the Board of Directors and Audit Committee for Intersil Corporation from July 2015 to February 2017 until Intersil was acquired by Renesas Electronics for $3.2 billion. During his tenure on the Intersil board, Mr. Maddock was appointed as Audit Committee Chair. Mr. Maddock will also serve as Audit Committee Chair of Ultra Clean effective with his appointment to the Board of Directors. He also has private company board experience having served on the Novaled AG board from March 2012 to August 2013; Novaled GmbH now operates as a subsidiary of Samsung SDI Co. Ltd.

Mr. Maddock holds a B.S. in Industrial Management from the Georgia Institute of Technology and an M.B.A. from Georgia State University.

BISTel, a provider of intelligent, real-time data management, advanced analytics and predictive solutions for smart manufacturing announced today its first adaptive intelligence (A.I.) based applications to enable the smart connected factory or industry 4.0 as some call it. Called Dynamic Fault Detection (DFD), BISTel’s new fault detection and classification solution offers customers full sensor trace data analysis to detect and classify faults real-time, improving quality and yield significantly.

Today, customers rely on legacy FDC systems for accurate fault detection. These systems offer only summary data analysis from sensors for fault detection. Consequently, small changes in sensor behavior can go undetected, resulting in a negative impact on yield. BISTel’s new Dynamic Fault Detection (DFD®) system overcomes these challenges by offering full trace analysis. Because BISTel’s new DFD® system establishes trace references dynamically and does not rely on the traditional control limiting methods used by FDC, it eliminates modeling completely. DFD also uses smarter algorithms to better distinguish between real alarms and false alarms resulting in 10 times fewer alarms than FDC systems.

“DFD is the first of several intelligent manufacturing applications with new machine learning that will help our customers to start to realize the full potential of A.I. for smart manufacturing,” commented W.K. Choi, Founder and CEO, BISTel. “DFD enables customers to quickly and accurately identify and classify faults. DFD helps our customers create early identification of yield related issues so that they can quickly execute the fastest possible response to solving these issues.” added Choi.

Sensor trace data contains a wealth of information that helps manufacturers identify potential yield issues, including ramp rate changes, spikes, glitches, shift and drift. BISTel’s first of its kind, online Dynamic Fault Detection (DFD®) system lowers these risks by offering manufacturers real-time monitoring and detection of full sensor trace data. Customers can now quickly detect, and analyze yield impacting events and quickly resolving yield issues. DFD® also integrates seamlessly to legacy FDC systems.

Key Features and Benefits

  • Real time monitoring Improves quality and yield.
  • Reduces risk by protecting against yield impacting events.
  • Real-time fault detection with dynamic references instead of static control limits.
  • DFD’s sensor behavior analysis enables best system drift detection
  • Intelligent alarming reduces alarms by more than 10X

Consumer demand and government mandates for electronic systems that improve vehicle performance, that add comfort and convenience, and that warn, detect, and take corrective measures to keep drivers safe and alert are being added to new cars each year. This system growth, along with rising prices for memory components within them, are expected to raise the automotive IC market 18.5% this year to a new record high of $32.3 billion, surpassing the previous record of $27.2 billion set last year (Figure 1), according to IC Insights’ soon to be released Update to the 2018 IC Market Drivers report.  If the forecast holds, it would mark the third consecutive year of double-digit growth for the automotive IC market.

Figure 1

Over the past several years, the global automotive IC market has experienced some extraordinary swings in growth. After increasing 11.5% in 2014, the automotive IC market declined 2.5% in 2015, but then rebounded with solid 10.6% growth in 2016. It is worth noting that the sales decline experienced in 2015 was primarily the result of falling ASPs across all the key automotive IC product categories—microcontrollers, analog ICs, DRAM, flash, and general- and special-purpose logic ICs, which offset steady unit growth for automotive ICs that year.

IC Insights’ recently updated automotive IC market forecast shows the automotive IC market growing to $43.6 billion in 2021, which represents a compound annual growth rate (CAGR) of 12.5% from 2017 to 2021, highest among the six major end-use applications (Figure 2).

Figure 2

Collectively, automotive ICs are forecast to account for only about 7.5% of the total IC market in 2018, although that share is forecast to increase to 9.3% in 2021.  Analog ICs—both general-purpose analog and application-specific automotive analog—are expected to account for 45% of the 2018 automotive IC market, with MCUs capturing 23% share. There are many suppliers of automotive analog devices but a rash of acquisitions among them in recent years has reduced the number of larger manufacturers. Some of the acquisitions that have impacted the automotive analog market include NXP, which acquired Freescale in 2015 and is now itself in the process of being acquired by Qualcomm; Analog Devices, which acquired Linear Technology in March 2017; and Renesas, which acquired Intersil.

Semiconductor equipment manufacturer ClassOne Technology has announced the sale of its Solstice® Electroplating Systems to the industry’s leading providers of VCSEL (Vertical-Cavity Surface-Emitting Laser) devices in recent months. The announcement was made by ClassOne Group CEO, Byron Exarcos.

“This is an important trend. We’re observing unprecedented demand for VCSEL manufacturing capacity to support 3D sensing, fiber-optic communications, and laser-based materials processing,” said Exarcos. “At the same time, we see that compound semiconductor manufacturers are migrating production from wet-benches to automated single-wafer plating. The strong upturn in our Solstice sales reflects this. Our Solstice platform provides state-of-the-art automation and control, with industry-leading uniformity and throughput. At half the cost of competitive products, Solstice has become the platform of choice for manufacturers who use smaller substrates.”

ClassOne has developed several proprietary high-performance Solstice processing chambers that are of particular interest to VCSEL manufacturers who require high-speed, high-quality cost-cutting plating using materials such as Gold, Nickel or Copper.

“Compound semiconductor makers are looking for maximum flexibility,” explained Exarcos. “They like the fact that Solstice can run multiple wafer sizes simultaneously, and that the platform can be configured for a wide variety of wet processes beyond electroplating. These include Metal Lift Off, Resist Strip, Gold Deplate, UBM Etch, KOH Etch, Anodizing, and more—all from a single automated platform. We call this Plating-Plus™, and it can eliminate the need to purchase additional downstream tools.”

Exarcos emphasized that in addition to system performance, VCSEL manufacturers are attracted to Solstice’s exceptional affordability. The ≤200mm Solstice systems are priced at roughly half the cost of comparable 300mm systems from the large equipment manufacturers.

Solstice is a family of electroplating tools that includes Solstice S8 and S4, which are 8- and 4-chamber systems that can deliver throughputs of up to 75 wph. Multiple wet-process chambers enable the tools to perform multiple processes in-line simultaneously. ClassOne also offers the semi-automated Solstice LT specifically for process development and low-volume applications.

All Solstice customers enjoy access to the services of ClassOne’s world-class applications lab, which offers advanced equipment and expert technical support in developing and optimizing customized wet-process applications.

An international team of researchers, affiliated with UNIST has discovered a novel method for the synthesis of ultrathin semiconductors. This is a unique growth mechanism, which yielded nanoscopic semiconductor ribbons that are only a few atoms thick.

This breakthrough has been jointly conducted by Distinguished Professor Feng Ding and Dr. Wen Zhao from the Center for Multidimensional Carbon Materials (CMCM), within the Institute for Basic Science (IBS) at UNIST, in collaboration with the National University of Singapore (NUS), the National Institute for Materials Science (NIMS), the National Institute of Advanced Industrial Science and Technology (AIST), and Shenzhen University.

In the study, the research team has successfully fabricated MoS2 nanoribbons via vapour-liquid-solid (VLS) growth mechanism, a type of chemical vapour deposition (CVD) process.

“Synthesis of vertically elongated structure via VLS growth mechanism.”

Chemical vapor deposition or CVD is a generic name for a group of processes whereby a solid material is deposited from a vapor by a chemical reaction occurring on or in the vicinity of a normally heated substrate surface. It is the most widely adopted industrial techniques for producing semiconducting thin films and nanostructures.

“The range of structures that can be controllably synthesized by the current methods is still limited in terms of morphology, spatial selectivity, crystal orientation, layer number and chemical composition,” the research team noted. “Therefore, developing versatile growth methods is essential to the realization of highly integrated electronic and photonic devices based on these materials.

“The current CVD-based growth process relies on the inherent dynamics of the precursors to diffuse and self-organize on the substrate surface, which results in crystallites with characteristic triangular or hexagonal shapes,” says Dr. Zhao. “This unique growth mechanism of the nanoscopic semiconductor ribbons that are only a few atoms thick is an exciting discovery.” In the study, she performed density functional theory based molecular dynamic (DFT-MD) simulations of the MoS2 precipitation process.

The proposed mechanism of VLS growth differs from commonly known CVD technique, as it involves the precursors introduced in the vapour phase form a liquid droplet intermediate before condensing into a solid product.

The team noted that the morphology of the growth product was, however, unlike what is normally expected from a VLS growth, which typically yields cylindrical or tubular structures rather than ribbons. Their observation suggests that the liquid droplet migrates on the substrate surface in a rather ordered manner, leaving behind a track of ultrathin crystal.

“Because the liquid droplet migrates on the substrate surface in a rather ordered manner, the morphology of the growth product yielded cylindrical or tubular structures rather than ribbons.” says Dr. Zhao.

This time, however, the horizontal growth of predominantly monolayer MoS2 ribbons was obtained via VLS growth, a unique growth mechanism that has not been reported until now.

Their observation revealed that the VLS growth of monolayer MoS2 is triggered by the reaction between MoO3 and NaCl, which results in the formation of molten Na-Mo-O droplets. These droplets mediate the growth of MoS2 ribbons in the ‘crawling mode’ when saturated with sulfur. The locally well-defined orientations of the ribbons reveal the regular horizontal motion of the droplets during growth.

“Assisting the growth of MoS2 ribbons, like painting with a an ink droplet.”

In order to gain insight into the liquid-solid transformation, Professor Ding’s team performed density functional theory based molecular dynamic (DFT-MD) sumulations of the precipitation process. The simulation showed the attachment of molybdenum (Mo) and sulfur (S) to the previously established MoS2.

“It is worth noting that MoS2 is not oxidized despite the presence of large numbers of oxygen atoms,” says the research team. “We also observe the nucleation of MoS2 clusters in regions that are rich in Mo and S atoms, further supporting the feasibility of liquid-mediated nucleation and growth of MoS2.”

“This study has prompted questions about surface and interface growth of nanomaterials,” says Professor Ding. “By identifying a suitable liquid-phase intermediate compound, we believe that it will be possible to realize the direct 1D growth of a range of van der Waals layered materials.”

The team anticipates that many other materials can be grown using a similar approach. Their short-term goal is to understand the growth mechanism better and to control the morphology of the ribbons.

“Our work identified many interesting questions about surface and interface growth of nanomaterials,” says Professor Goki Eda at the National University of Singapore (NUS), the corresponding author of this study. “We predict that the ability to directly grow complex structures will greatly facilitate the realization of high performance nanoelectronic circuits.”

The team noted that their results provide insight into the distinct VLS growth mode of 2D MoS2 and demonstrate the potential of their implementation in nanoelectronic devices. The findings of this study have been published in the prestigious journal, Nature Materials on April 23, 2018.

GLOBALFOUNDRIES today announced that its 180nm Ultra High Voltage (180UHV) technology platform has entered volume production for a range of client applications, including AC-DC controllers for industrial power supplies, wireless charging, solid state and LED lighting, as well as AC adapters for consumer electronics and smartphones.

The increasing demand for highly cost-effective systems requires integrated circuits (ICs) that achieve significant area savings while reducing bill-of-materials (BOM) and printed circuit board (PCB) footprint by integrating discrete components onto the same die. GF’s 180UHV platform features a 3.3V LV CMOS baseline, with options for HV18, HV30 and 700V UHV, that delivers significant area savings for both digital and analog circuit blocks, compared to the traditional 5V bipolar CMOS DMOS (BCD) technologies.

“GF’s leadership in providing high voltage solutions makes the company a perfect strategic partner for On-Bright’s power supply technologies,” said Julian Chen, CEO of On-Bright, the leading market player in AC-DC switch mode power supply products. “GF’s new 180UHV process integrates UHV components into the same IC with 180nm digital and analog by incorporating On-Bright know-how in the design. The technology has reduced On-Bright’s switched-mode power supply cost and footprint to give our AC-DC switch mode power supply products additional system-level benefits.”

As part of a modular platform based on the company’s 180nm process node, GF’s 180UHV process technology delivers a 10x increase in digital density compared to previous generations for integrated AC-DC conversion. For AC-DC conversion, the platform integrates high voltage transistors with precision analog and passive devices to control high input and output voltages of AC-DC SMPS circuits. The process is qualified up to 150°C to accommodate the high ambient temperatures of power supply and LED lighting products.

“GF continues to expand its UHV portfolio to provide competitive technology capabilities and manufacturing excellence that will enable our customers to play a critical role in bringing a new generation of highly integrated devices to real-world environments,” said Dr. Bami Bastani, senior vice president of business units at GF. “Our 180UHV is an ideal technology for customers that are looking to develop the highest-performing solutions for a new generation of integrated digital, analog and high voltage applications.”

As a part of the company’s analog and power platform, GF provides various types of HV, BCD, and UHV technologies, allowing customers to integrate power and high voltage transistors across a wide range of voltages, from 5V to 700V, to meet the diverse needs of low and high power applications. GF has a successful track record in manufacturing analog and power solutions in both its 200mm and 300mm production lines in Singapore.

Scientists from the universities of Bristol and Cambridge have found a way to create polymeric semiconductor nanostructures that absorb light and transport its energy further than previously observed.

Image showing light emission from the polymeric nanostructures and schematic of a single nanostructure. Credit: University of Bristol

This could pave the way for more flexible and more efficient solar cells and photodetectors.

The researchers, whose work appears in the journal Science, say their findings could be a “game changer” by allowing the energy from sunlight absorbed in these materials to be captured and used more efficiently.

Lightweight semiconducting plastics are now widely used in mass market electronic displays such those found in phones, tablets and flat screen televisions. However, using these materials to convert sunlight into electricity, to make solar cells, is far more complex.

The photo-excited states – which is when photons of light are absorbed by the semiconducting material – need to move so that they can be “harvested” before they lose their energy in less useful ways. These excitations typically only travel ca. 10 nanometres in polymeric semiconductors, thus requiring the construction of structures patterned on this length-scale to maximise the “harvest”.

In the chemistry labs of the University of Bristol, Dr Xu-Hui Jin and colleagues developed a novel way to make highly ordered crystalline semiconducting structures using polymers.

While in the Cavendish Laboratory in Cambridge, Dr Michael Price measured the distance that the photo-exited states can travel, which reached distances of 200 nanometres – 20 times further than was previously possible.

200 nanometres is especially significant because it is greater than the thickness of material needed to completely absorb ambient light thus making these polymers more suitable as “light harvesters” for solar cells and photodetectors.

Dr George Whittell from Bristol’s School of Chemistry, explains: “The gain in efficiency would actually be for two reasons: first, because the energetic particles travel further, they are easier to “harvest”, and second, we could now incorporate layers ca. 100 nanometres thick, which is the minimum thickness needed to absorb all the energy from light – the so-called optical absorption depth. Previously, in layers this thick, the particles were unable to travel far enough to reach the surfaces.”

Co-researcher Professor Richard Friend, from Cambridge, added: “The distance that energy can be moved in these materials comes as a big surprise and points to the role of unexpected quantum coherent transport processes.”

The research team now plans to prepare structures thicker than those in the current study and greater than the optical absorption depth, with a view to building prototype solar cells based on this technology.

They are also preparing other structures capable of using light to perform chemical reactions, such as the splitting of water into hydrogen and oxygen.

By Deb Vogler

This year’s Advanced Lithography TechXPOT at SEMICON West will explore the progress on extreme ultra-violet lithography (EUVL) and its economic viability for high-volume manufacturing (HVM), as well as other lithography solutions that can address the march to 5nm and onward to 3nm. Several session speakers offered their insights into the readiness of EUVL for 5nm and how other lithography solutions will enable 3nm. See the full list of speakers and program agenda at http://www.semiconwest.org/programs-catalog/lithography-5nm-and-below.

Diverging viewpoints on EUVL readiness for 5nm

Mike Lercel, Director of Strategic Marketing at ASML

ASML expects its first customer to start volume manufacturing with EUV at the 7nm logic node and the mid-10nm DRAM node in the 2018/2019 timeframe. “EUV will replace the most difficult layers that require multiple patterning, and many layers will continue to be allocated to immersion tools for the foreseeable future,” said Lercel. “For the 5nm logic node, more layers are expected to migrate to EUV.”

Three ASML customers have early-access versions of the next-generation TWINSCAN NXT:2000i for the development of advanced logic and DRAM nodes. “This system delivers 2.0nm cross-matched on-product overlay, achieved through several hardware advancements,” noted Lercel. “It is also significant because this mix-and-match use with EUV features a significantly different hardware platform.” TWINSCAN NXT:2000i features a new alignment sensor and improved wafer table flatness, endurance, and clamping mechanism to enhance matching to EUV.

ASML has achieved good industrialization progress of its pellicle, with tests confirming that pellicles can withstand 245W source power and an offline power lifetime test indicating 400W capability. Compared to the 7nm logic node, the requirements for EUV masks will become tighter at 5nm, but Lercel noted that ASML sees good progress with the industry infrastructure to support 5nm in areas such as reducing mask blank defects. “We will continue to improve pellicle transmission for enhanced throughput, but there are no fundamental changes in pellicle requirements for 5-3nm logic nodes. We see no infrastructure showstoppers for the introduction of EUVL at the 5nm node.”

Stephen Renwick, Director of Imaging Physics at Nikon Research Corporation of America

Renwick said that the 7nm logic node is expected to be fabbed mostly using 193i lithography. “EUV will struggle to be ready for 5nm, limited by yield issues caused by stochastic effects in the resist,” said Renwick. “Ready or not, though, it will be used.” Renwick suggests that introducing multiple-patterning with EUV may be needed but would increase costs. “193i lithography will continue to be used with quadruple-patterning and in combination with other techniques – there is no single solution.”

Figure 1. Normalized cost/layer vs. lithography method. SOURCE: Nikon Research Corporation of America

When choosing between immersion lithography and EUV for different customer segments at 5nm, Renwick noted that the cost depends on the layer. “Some time ago, we calculated that the costs of either 193i triple-patterning or 193i SADP with two cuts were roughly equal to single-patterning with EUV,” explained Renwick (Figure 1). “That agreed with chipmakers’ public estimates and meant that the choice of lithography method depended more on the performance tradeoffs involved, such as 193i’s better line-edge roughness. At the 5nm node, we are probably faced with quad-patterning from 193i, double-patterning from existing EUV tools, or single-patterning from as-yet undelivered high-numerical aperture (NA) EUV tools.” Renwick believes that the competition between low-NA EUV double-patterning and 193i quad-patterning will be similar to the current situation (i.e., comparison of 193i triple-patterning or 193i SADP with two cuts vs. single-patterning with EUV), but for high-NA EUV tools he believes it’s too early to say.

Other challenges Renwick sees on the horizon for EUVL at 5nm are stochastic effects in EUV resists. “They cause yield problems on contact arrays and unacceptable line-edge roughness on line/space patterns,” said Renwick. “It’s unlikely that these effects will go away without increasing the litho dose, which will further challenge throughput performance.” He also questions whether EUV pellicles, though under development, will be “ready for prime time.”

Harry Levinson, Sr. Director of Strategic Lithography Technology and Sr. Fellow at GLOBALFOUNDRIES

Levinson said additional fundamental engineering work is needed to ready EUV lithography for 5nm. “Among the top problems are stochastics-induced resist defects, which increase significantly as dimensions shrink below those for 7nm,” explained Levinson (Figure 2). “Higher exposure doses will be required to address these issues related to stochastics at 5nm, which will require higher source output” (than 7nm).

Levinson said there will be greater motivation to use EUVL at the 5nm node vs. at 7nm to offset the large number of exposures associated with 193nm immersion multiple-patterning solutions. “The primary application of EUV lithography at 7nm will be for contact, via and cut layers,” Levinson noted. “It will be important to enable EUVL for metal masks at the 5nm node, which increases the need for an ample supply of very low defect EUV mask blanks.” Levinson added that the 7nm node is already stressing defect inspection capabilities, and no actinic defect inspection system is yet available for patterned masks. “This situation becomes more problematic with widespread application of EUVL to metal layers.”

Mask development for 5nm

Christopher C. Progler, CTO & Strategic Planning at Photronics

Progler said that the basic infrastructure for delivering EUV masks is available, especially for dark field layers and near in nodes. “The interconnected or more open frame patterns will need refinements to the processes and two to three nodes out will need certain new infrastructure,” said Progler. Overall, the main challenges for initial insertion are about creating a cost-effective and rapid-turn EUV mask process, he said. “The industry can certainly deliver EUV masks in some form. It is more a question of doing it efficiently and productively to match the stated value proposition of EUV over other lithographic methods. We don’t want a pick two of ‘cost, cycle time, capability’ sort of mask solution.”

More specifically, Progler explained that after the initial EUV mask development for 5nm focused on contacts and block layers, the major push for N5 switched to delivering single-exposure EUV metal patterning as early as possible. “This has opened some new challenges for masks given the resolution, critical pattern density and tight pitch defect requirements of the re-aggregated single-layer metal mask designs,” said Progler. “For example, on the resolution side, we are accelerating the insertion of higher dose photoresists and also driving patterning module improvements in CD control, mask LER and sidewall angle.” Progler added that at N5, the mask 3D structure itself – including the sidewall – will have a greater impact on lithography because it is tied to stochastic error rates on the wafer.

“Reliable, wide-area metrology for some of these 2D and 3D mask parameters is currently hard to come by. We may see an evolution of the blank structure at some point in N5, including hard mask options for pattern stability and expect earlier insertion of EUV mask process correction with model-based hot spot detection and rule checking as well. We also hope mask-scanner dedication is not needed, but there are some indications process sensitivity may push us earlier in this direction.” He added that to reduce metal layer defects, more attention needs to be devoted to advanced repair and model-based validation. “We are, unfortunately, still in a situation of blurry vision and high native defect counts alongside possible in situ contamination during mask changes.”

Figure 2. Resist stochastics-induced defects. Graph courtesy of Peter DeBisschop, imec; Source: GLOBALFOUNDRIES

Progler pointed out that, with the advent at 5nm, metal masks will require some level of actinic blank inspection for yield, increasing the cost of an already expensive mask technology. “So, unless we want to contend with double and triple photomasks’ starts to deliver a single metal layer, it will be very important to tighten the multi-sensor inspection, defect abatement, and repair loops,” said Progler. He does see some clouds forming around high-volume manufacturing pellicles for metal layers. “This remains an open question, mainly for thermal and materials reasons, not to mention cost and cycle time,” Progler said. “We may be pessimistic, but we do not see an HVM pellicle solution converging in the required timeframe, which means leaning even more on a wafer-level inspection in the validation loop.” He believes that streamlining validation will be a differentiator. “I can imagine one losing most of the EUV cycle time benefits by endlessly circling masks around if this is not done well.”

How does the industry get to 3nm?     

ASML plans to ship its first high-NA EUV prototope/pilot systems between 2020 and 2023 to support 3-2nm process development. “System designs are now being finalized and the platform is starting to come to life,” said Lercel. ASML supplier ZEISS is building a high-NA cleanroom for optics production. ASML believes that EUV, high-NA and DUV systems will be used together at the most advanced nodes and is designing to account for this mixed environment. “As chipmakers drive toward smaller geometries in the most advanced nodes like 3nm, they face unprecedented challenges in devices and materials. This will make the process control requirements even more challenging.” ASML is tackling these challenges with its YieldStar metrology platform, e-beam metrology (HMI) and computational lithography solutions that are designed to expand the process window, enhance process control, and improve patterning defect detection. “This ‘Holistic Lithography’ approach will become increasingly important to ensure throughput and yield at the most advanced nodes.”

Levinson said that the issues he projects for 5nm will need to be addressed further at 3nm. “The challenges associated with resists at 3nm dimensions are such that it isn’t clear that chemically amplified resists will be capable of meeting requirements,” said Levinson. “If true, we would be seeing the most significant change in resist platforms in a quarter of a century. Potentially cost-reducing technologies such as directed self-assembly (DSA) are always welcome, but EUVL will be the lithographic workhorse through the 3nm node, and likely beyond.”

At 3nm, mask makers will confront the realities of higher EUV NA tools. “We will need to implement thinner mask absorbers, new films, and perhaps hard masks,” Progler said. “This puts us in a new materials regime for masks, and history has shown us the mask industry takes a long time to refine processes and tools for new mask materials.” He explained that the small scale of the mask ecosystem and the small number of large suppliers available to address the challenges accounts for this lengthy time frame.

Still, looking ahead, Progler noted that Photronics has already done a few studies on the impact of proposed half-field, high NA anamorphic optics on masks. “We uncovered some challenges that need to be addressed, particularly at boundaries and within the overall mask flow,” said Progler. As mask resolution continues to scale down, the industry will need fundamentally higher resolution mask making and inspection processes, requiring next-generation multi-beam mask writing and electron beam inspection, he explained.

At 3nm and below, Progler noted that the metrology needs for masks, while not as severe as that for wafers at these nodes, will test the mask equipment infrastructure in ways that could challenge the relatively small mask industry. “Of course, EUV multi-patterning comes into play as well, and with that, the SRAF sizes will drop below 20nm, requiring an asymmetric compensation over a much wider influence area than the OPC people are used to considering.” With EUV multi-patterning, Progler explained that it will be increasingly important to match or pair EUV masks and to consider how 3D effects and stochastics will drive new technology to enable new requirements for high-speed metrology and simulation components. “All the justifiable hand-wringing over EPE with ArF multi-patterning today gets introduced to the EUV scene when masks are ganged together to make a single device layer,” said Progler.

Originally published on the SEMI blog.