Category Archives: Semiconductors

By Emmy Yi, SEMI Taiwan Marketing

Emboldened by advances in self-driving and Internet of Vehicles (IoV) technologies, Taiwan’s microelectronics sector is investing heavily in manufacturing processes and equipment as engines of innovation and growth for autonomous driving, the world’s next market goldmine. But breaking into the self-driving vehicle industry can be an uphill struggle. Semiconductor players bent on securing their piece of the potentially massive market must know how to navigate the automotive industry’s unique ecosystem of suppliers, not to mention its lofty standards for safety and reliability.

To explore opportunities and challenges in the automotive semiconductor market, SEMI recently organized Mobility Tech Talk – a gathering of invited professionals from Strategy Analysis, Yole Développement, Renesas, X-FAB and IHS Markit to examine the evolution of sensors for autonomous cars, advanced driver-assisted system (ADAS) applications, and new energy vehicles (NEVs) in China. Nearly 200 participants exchanged in-depth, forward-looking insights and perspectives as the event successfully reinforced connections among different segments. Here are four key takeaways from the event.

Lidar: The hottest sensing technology for smart automotive

Lidar, mmWave radar, cameras and inertial measurement units (IMUs) are the most important sensing devices for autonomous cars. As sensor and high-speed computing technologies mature, 2018 may mark the beginning for an era of autonomous cars, with 350,000 self-driving vehicles expected to hit the road by 2027. But before a single car takes to the roadways, self-driving technology must become expert at monitoring a vehicle’s environment.

That’s where Lidar, the hottest of all sensing technologies and the key to the holy grail of safe self-driving, comes into the picture. Lidar’s versatility supports multiple essential functions such as mapping, object detection and object movement, but mass production is still impossible due to its high cost. What’s more, technical issues must still be sorted out with solid-state lidar, mechanical lidar and MEMS. Both startups and traditional tier-1 semiconductor players have aggressively invested in related research and development, all hoping to pre-position themselves for the new opportunity.

Smart automotive sets new quality and safety standards

As cars become smarter, so too must silicon. Chips must support vastly more data generated by in-vehicle connectivity, ADAS, electrification, autonomous driving and a multitude of other functions that rely on advanced automotive electronics components. Demand for smarter silicon is prompting Taiwan companies to directly tap the automotive chip market or serve as OEMs for major automakers.

With quality and safety top priorities for automotive applications, in-vehicle semiconductors must meet strict requirements across areas including vehicle control, robustness, liability, cost and quality management to conform to the automotive specifications necessary to securing certifications. Smart silicon must also pass all AEC-Q liability standards promoted by automakers in North America, and score “zero defect” for the ISO/TS 16949 Automotive Quality Management System.

China’s new energy vehicles to fuel semiconductor growth

To promote NEVs and thus reduce fuel consumption by cars with internal combustion engines (ICEs), late last year the Chinese government introduced the Measures for the Parallel Administration of the Average Fuel Consumption and New Energy Vehicle Credits of Passenger Vehicle Enterprises. With China the world’s largest market for NEVs, the policy is forcing automakers in Japan, the U.S. and Europe to accelerate moves towards NEVs that, in turn, will fuel growth in the semiconductor and automotive battery industries. NEVs in China are expected to number 2 million by 2020 before more than doubling to 4.9 million by 2025. Today, most cars still run on ICEs as environmentally friendly motor drives are still under development. In unit shipments, motor drives are expected to exceed ICEs by 2025.

Cross-field collaboration is the key

The rise of smarter, fully autonomous vehicles – a disruptive “Car 2.0” – is unlikely to happen overnight. The global automotive semiconductor market will continue rapid growth, with safety and powertrain applications driving the strongest chip demand. Meanwhile, automakers are focusing more on innovations from startups and non-traditional suppliers, and some have even started developing their own IP and solutions. These paradigm industry shifts are diversifying the automotive supply chain into a cross-domain collaborative network of suppliers, pushing the closed, one-way automotive supply chain into lesser relevance. In the near future, rivals and partners may become indistinguishable as traditional turf wars begin to wane.

As ADAS and autonomous cars evolve, and the era of electric cars nears, automotive semiconductors are rising as the engine of growth for the global semiconductor industry. The automotive semiconductor market is expected to grow at a CAGR of 5.8 percent, reaching US$48.78 billion by 2022.

To help the semiconductor and automotive industries thrive in the era of self-driving vehicles, SEMI has established the Smart Automotive special interest group, a platform for better connecting elite professionals from the microelectronics and automotive sectors. Focusing on trends and innovation in the global autonomous semiconductor industry, the SEMI Smart Automotive SIG promotes industry development and cross-domain collaboration so members can create more business opportunities.

Originally published on the SEMI blog.

Engineers at the University of California, Riverside, have demonstrated prototype devices made of an exotic material that can conduct a current density 50 times greater than conventional copper interconnect technology.

Current density is the amount of electrical current per cross-sectional area at a given point. As transistors in integrated circuits become smaller and smaller, they need higher and higher current densities to perform at the desired level. Most conventional electrical conductors, such as copper, tend to break due to overheating or other factors at high current densities, presenting a barrier to creating increasingly small components.

Microscopy image of an electronic device made with 1D ZrTe3 nanoribbons. The nanoribbon channel is indicated in green color. The metal contacts are shown in yellow color. Note than owing to the nanometer scale thickness the yellow metal contacts appear to be under the green channel while in reality they are on top. Credit: Balandin lab, UC Riverside

Microscopy image of an electronic device made with 1D ZrTe3 nanoribbons. The nanoribbon channel is indicated in green color. The metal contacts are shown in yellow color. Note than owing to the nanometer scale thickness the yellow metal contacts appear to be under the green channel while in reality they are on top. Credit: Balandin lab, UC Riverside

The electronics industry needs alternatives to silicon and copper that can sustain extremely high current densities at sizes of just a few nanometers.

The advent of graphene resulted in a massive, worldwide effort directed at investigation of other two-dimensional, or 2D, layered materials that would meet the need for nanoscale electronic components that can sustain a high current density. While 2D materials consist of a single layer of atoms, 1D materials consist of individual chains of atoms weakly bound to one another, but their potential for electronics has not been as widely studied.

One can think of 2D materials as thin slices of bread while 1D materials are like spaghetti. Compared to 1D materials, 2D materials seem huge.

A group of researchers led by Alexander A. Balandin, a distinguished professor of electrical and computer engineering in the Marlan and Rosemary Bourns College of Engineering at UC Riverside, discovered that zirconium tritelluride, or ZrTe3, nanoribbons have an exceptionally high current density that far exceeds that of any conventional metals like copper.

The new strategy undertaken by the UC Riverside team pushes research from two-dimensional to one-dimensional materials­­– an important advance for the future generation of electronics.

“Conventional metals are polycrystalline. They have grain boundaries and surface roughness, which scatter electrons,” Balandin said. “Quasi-one-dimensional materials such as ZrTe3consist of single-crystal atomic chains in one direction. They do not have grain boundaries and often have atomically smooth surfaces after exfoliation. We attributed the exceptionally high current density in ZrTe3 to the single-crystal nature of quasi-1D materials.”

In principle, such quasi-1D materials could be grown directly into nanowires with a cross-section that corresponds to an individual atomic thread, or chain. In the present study the level of the current sustained by the ZrTe3 quantum wires was higher than reported for any metals or other 1D materials. It almost reaches the current density in carbon nanotubes and graphene.

Electronic devices depend on special wiring to carry information between different parts of a circuit or system. As developers miniaturize devices, their internal parts also must become smaller, and the interconnects that carry information between parts must become smallest of all. Depending on how they are configured, the ZrTe3 nanoribbons could be made into either nanometer-scale local interconnects or device channels for components of the tiniest devices.

The UC Riverside group’s experiments were conducted with nanoribbons that had been sliced from a pre-made sheet of material. Industrial applications need to grow nanoribbon directly on the wafer. This manufacturing process is already under development, and Balandin believes 1D nanomaterials hold possibilities for applications in future electronics.

“The most exciting thing about the quasi-1D materials is that they can be truly synthesized into the channels or interconnects with the ultimately small cross-section of one atomic thread– approximately one nanometer by one nanometer,” Balandin said.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that it has started construction work for the next expansion phase of its corporate headquarters. The new building will house EVG’s “Manufacturing III” facility, which will more than double the floor space for the final assembly of EVG’s systems.

“With our innovative manufacturing solutions for the high-tech industry as well as new biomedical applications, we operate in very dynamic markets with great future prospects,” stated Dr. Werner Thallner, executive operations and financial director at EV Group. “In light of the high capacity utilization in all areas of our existing facilities, as well as the positive market outlook, we decided to implement our plans for building our Manufacturing III facility this year. This will support our long-term growth targets at our corporate headquarters in St. Florian am Inn.”

EVG Manufacturing III Photo 1

The new Manufacturing III building, adjacent to the new test room site that was opened just a few months ago, will be built next to the river Inn. The ultramodern building will provide approximately 4,800 square meters of additional space in total, which will benefit not only manufacturing but other departments as well. In addition to an expansion of warehouse space, a new delivery area with a dedicated packaging site designed for cleanroom equipment will be created, along with an airfreight security zone and new truck loading docks for the shipment of the completed systems to EVG’s worldwide customers.

The construction of the new Manufacturing III building is set to be completed in early 2019.

TowerJazz today announced the release of its 300mm 65nm BCD (Bipolar-CMOS-DMOS) process, the most advanced power management platform for up to 16V operation and 24V maximum voltage.  This technology is manufactured in TowerJazz’s Uozu, Japan facility, with best-in-class quality and cycle time, and is based on the Company’s 300mm 65nm automotive qualified flows.

This platform provides significant material competitive advantages for any type of power management chip up to 16V regardless of application, including a wide variety of products such as: PMICs, load switches, DC-DC converters, LED drivers, motor drivers, battery management, analog and digital controllers, and more. IHS Markit Power IC Analyst, Kevin Anderson forecasts a $9.4 billion available market, which this technology addresses, in 2018 with continual growth.

TowerJazz’s 65nm BCD process is leading this low voltage market segment with the highest power efficiency, very small die size, best digital integration capability; and superior cost effectiveness through both the smallest aerial footprint and the lowest mask count.

The process includes four leading edge power LDMOS transistors: 5V, 7V, 12V and 16V operation, each with the best available Rdson and Qgd parameters. In addition to the new aforementioned cost and figure of merit benchmarks, multiple chips can be integrated to a single monolithic IC solution replacing a multiple chip module for an improved system cost structure and system performance.

TowerJazz’s power transistors are fully isolated to withstand high currents, all with an ultra-low Rdson, e.g. less than 1mΩ*mm² for the 5V LDMOS. For products which operate at the megahertz (MHz) switching frequencies, the 65nm BCD power transistors benefit from a very low Qgd down to 2.6mΩ*nC. In addition, very low metal resistance is achieved using a single or dual 3.3um top thick copper. The 65nm BCD also offers aggressive 113Kgate/mm² 5V digital density and an 800Kgate/mm² 1.2V digital library.

“This new 65nm BCD platform establishes TowerJazz as a technology leader in the related growing markets for up to 16V power applications,” said Shimon Greenberg, Vice President and General Manager of Power Management & Mixed-Signal/CMOS Business Unit, TowerJazz. “Best addressing the vast low voltage power management market segment, we are experiencing very high interest from early adopter customers and plan a mass production ramp by the fourth quarter of 2018.”

TowerJazz will be exhibiting at ISPSD, the 30th IEEE International Symposium on Power Semiconductor Devices and ICs on May 13-17, 2018 in Chicago, USA.

The top 10 IC suppliers in the $54.5 billion analog market last year accounted for 59% of the category’s worldwide sales in 2017, according to a recent monthly update to IC Insights’ 2018 McClean Report. Collectively, the top 10 companies generated $32.3 billion in analog IC sales last year compared to $28.4 billion in 2016, which was a 14% increase and a gain of two percentage points in marketshare during 2017, said the 50-page April Update to The McClean Report.  Eight of the top-10 suppliers exceeded the 10% growth rate of the total analog market in 2017, according to the update.

With analog sales of $9.9 billion and 18% marketshare, Texas Instruments was again the leading supplier of analog integrated circuits in 2017.  In 2016, TI’s marketshare was 17% in analog ICs.  The company’s analog sales increased by about $1.4 billion last year—rising 16%—compared to 2016 and were more than twice that of second-ranked Analog Devices (ADI). TI’s 2017 analog revenue represented 76% of its $13.0 billion in total IC sales and 71% of its $13.9 billion total semiconductor revenue, based on IC Insights’ estimates.

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Figure 1

TI was among the first companies to manufacture analog semiconductors on 300mm wafers.  TI has claimed that manufacturing analog ICs on 300mm wafers gives it a 40% cost advantage per unpackaged chip compared to using 200mm wafers.  In 2017, about half of TI’s analog revenue was generated on devices built using 300mm wafers.

Second-place ADI registered a 14% increase in analog IC sales in 2017 to $4.3 billion, according to IC Insights’ supplier ranking. The 2016 and 2017 revenue numbers shown for ADI include sales from Linear Technology, which was acquired by the company in 1Q17 for $15.8 billion.

NXP was the only supplier in the top-10 ranking that experienced a decline (-1%) in its analog sales last year.  Some of NXP’s analog revenue decline can be attributed to the sale of its Standard Products business to a consortium of Chinese investors consisting of JAC Capital and Wise Road Capital.  The $2.75 billion transaction was completed in February 2017.  The Standard Products business was renamed Nexperia and headquartered in the Netherlands.

Among the top 10, ON Semiconductor showed the largest analog sales gain in 2017, with revenues increasing 35% to $1.8 billion, which represented a 3% share of the market.  This follows a 16% rise in its analog sales in 2016. Some of the strong increases in sales during the last two years were a result of ON Semi’s acquisition of Fairchild Semiconductor in September 2016 for $2.4 billion.  ON’s analog business was also boosted in 2017 by record sales of its power management products to the automotive market, specifically for active safety, powertrain, body electronics, and lighting applications.

The Semiconductor Industry Association (SIA) today announced worldwide sales of semiconductors reached $111.1 billion during the first quarter of 2018, an increase of 20 percent compared to the first quarter of 2017, but 2.5 percent less than the fourth quarter of 2017. Sales for the month of March 2018 came in at $37.0 billion, an increase of 20 percent compared to the March 2017 total of $30.8 billion and 0.7 percent more than the February 2018 total of $36.8 billion. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“The global semiconductor market has demonstrated impressive growth through the first quarter of 2018, far exceeding sales through the same point in 2017, which was a record year for semiconductor revenues,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Sales in March increased year-to-year for the 20th consecutive month. All regional markets experienced double-digit growth compared to last year, and all major semiconductor product categories experienced year-to-year growth, with memory products continuing to lead the way.”

Year-to-year sales increased across all regions in March: the Americas (35.7 percent), Europe (20.6 percent), China (18.8 percent), Asia Pacific/All Other (13.3 percent), and Japan (12.4 percent). Month-to-month sales increased in Europe (3.9 percent), China (2.2 percent), Japan (0.5 percent), and Asia Pacific/All Other (0.2 percent), but decreased slightly in the Americas (-2.0 percent).

For comprehensive monthly semiconductor sales data and detailed WSTS Forecasts, consider purchasing the WSTS Subscription Package. For detailed data on the global and U.S. semiconductor industry and market, consider purchasing the 2017 SIA Databook.

Mar 2018

Billions

Month-to-Month Sales                              

Market

Last Month

Current Month

% Change

Americas

8.26

8.09

-2.0%

Europe

3.43

3.57

3.9%

Japan

3.18

3.19

0.5%

China

11.70

11.95

2.2%

Asia Pacific/All Other

10.19

10.22

0.2%

Total

36.76

37.02

0.7%

Year-to-Year Sales                         

Market

Last Year

Current Month

% Change

Americas

5.96

8.09

35.7%

Europe

2.96

3.57

20.6%

Japan

2.84

3.19

12.4%

China

10.06

11.95

18.8%

Asia Pacific/All Other

9.02

10.22

13.3%

Total

30.84

37.02

20.0%

Three-Month-Moving Average Sales

Market

Oct/Nov/Dec

Jan/Feb/Mar

% Change

Americas

8.95

8.09

-9.6%

Europe

3.37

3.57

5.8%

Japan

3.24

3.19

-1.5%

China

12.01

11.95

-0.5%

Asia Pacific/All Other

10.41

10.22

-1.8%

Total

37.99

37.02

-2.5%

Research appearing today in Nature Communications finds useful new information-handling potential in samples of tin(II) sulfide (SnS), a candidate “valleytronics” transistor material that might one day enable chipmakers to pack more computing power onto microchips.

Valleytronics utilizes different local energy extrema (valleys) with selection rules to store 0s and 1s. In SnS, these extrema have different shapes and responses to different polarizations of light, allowing the 0s and 1s to be directly recognized. This schematic illustrates the variation of electron energy in different states, represented by curved surfaces in space. The two valleys of the curved surface are shown. Credit: Berkeley Lab

Valleytronics utilizes different local energy extrema (valleys) with selection rules to store 0s and 1s. In SnS, these extrema have different shapes and responses to different polarizations of light, allowing the 0s and 1s to be directly recognized. This schematic illustrates the variation of electron energy in different states, represented by curved surfaces in space. The two valleys of the curved surface are shown. Credit: Berkeley Lab

The research was led by Jie Yao of the Department of Energy’s Lawrence Berkeley National Laboratory (Berkeley Lab) and Shuren Lin of UC Berkeley’s Department of Materials Science and Engineering and included scientists from Singapore and China. Berkeley Lab’s Molecular Foundry, a DOE Office of Science user facility, contributed to the work.

For several decades, improvements in conventional transistor materials have been sufficient to sustain Moore’s Law – the historical pattern of microchip manufacturers packing more transistors (and thus more information storage and handling capacity) into a given volume of silicon. Today, however, chipmakers are concerned that they might soon reach the fundamental limits of conventional materials. If they can’t continue to pack more transistors into smaller spaces, they worry that Moore’s Law would break down, preventing future circuits from becoming smaller and more powerful than their predecessors.

That’s why researchers worldwide are on the hunt for new materials that can compute in smaller spaces, primarily by taking advantage of the additional degrees of freedom that the materials offer – in other words, using a material’s unique properties to compute more 0s and 1s in the same space. Spintronics, for example, is a concept for transistors that harnesses the up and down spins of electrons in materials as the on/off transistor states.

Valleytronics, another emerging approach, utilizes the highly selective response of candidate crystalline materials under specific illumination conditions to denote their on/off states – that is, using the materials’ band structures so that the information of 0s and 1s is stored in separate energy valleys of electrons, which are dependent on the crystal structures of the materials.

In this new study, the research team has shown that tin(II) sulfide (SnS) is able to absorb different polarizations of light and then selectively reemit light of different colors at different polarizations. This is useful for concurrently accessing both the usual electronic – and the material’s valleytronic – degrees of freedom, which would substantially increase the computing power and data storage density of circuits made with the material.

“We show a new material with distinctive energy valleys that can be directly identified and separately controlled,” said Yao. “This is important because it provides us a platform to understand how valley signatures are carried by electrons and how information can be easily stored and processed between the valleys, which are of both scientific and engineering significance.”

Lin, the first author of the paper, said the material is different from previously investigated candidate valleytronics materials because it possesses such selectivity at room temperature without additional biases apart from the excitation light source, which alleviates the previously stringent requirements in controlling the valleys. Compared to its predecessor materials, SnS is also much easier to process.

With this finding, researchers will be able to develop operational valleytronic devices, which may one day be integrated into electronic circuits. The unique coupling between light and valleys in this new material may also pave the way toward future hybrid electronic/photonic chips.

Berkeley Lab’s “Beyond Moore’s Law” initiative leverages the basic science capabilities and unique user facilities of Berkeley Lab and UC Berkeley to evaluate promising candidates for next-generation electronics and computing technologies. Its objective is to build close partnerships with industry to accelerate the time it typically takes to move from the discovery of a technology to its scale-up and commercialization.

By Jamie Girard, Sr. Director, Public Policy, SEMI

Just as the annual Cherry Blossom festival wraps up, international trade has flowered as a top concern for SEMI members, requiring immediate action as 20 SEMI member executives carried the torch for the industry in recent meetings with lawmakers at the annual SEMI Washington Forum. The business leaders quickly zeroed in on the proposed Sec. 301 tariffs of 25 percent on China imports to the U.S. and their potential to drive sharp increases in the cost of doing business.

In the meetings at the two-day event in Washington, D.C., the executives expressed deep concern that the tariffs, aimed at protecting the interests of U.S. companies, would instead harm the intended beneficiaries including SEMI members around the globe. The executives also focused on the proposed 232 tariffs on steel and aluminum that would compound the damage to their businesses, spiking costs of materials that lie at the heart of their manufacturing operations.

Also crucial to their business interests, the SEMI members educated lawmakers on the talent shortage and the intense competition to fill open positions across the supply chain. With fully 77 percent of industry executives seeing talent shortfalls as a pressing business issue, the business leaders pushed for legislation that would bring more domestic talent into the STEM education pipeline – such as S. 1518, The CHANCE in Tech Act to support more apprenticeships in technology, and H.R. 4023, the Developing Tomorrow’s Engineering and Technical Workforce Act to get more students involved in engineering. The group also encouraged support of the “Immigration Innovation” or “I-Squared” bill to strengthen and expand the H1-B visa program and STEM Greencards.

The SEMI Washington Forum, a venue for SEMI members to educate lawmakers about the industry, also addressed concerns over restrictions on foreign investment in the U.S. Passage of S. 2098, the Foreign Investment Risk Review Modernization Act (FIRRMA), would usher in new operating efficiencies for the Committee for Foreign Investment in the United States (CFIUS) by adding much-needed resources to the overburdened body. However, the bill would also subject many ordinary business transactions to a lengthy and costly national security review that would hamper the ability of many companies to do business in the global marketplace.

All told, attendees at the forum held more than 30 meetings with lawmakers, reflecting the great impact of public policy on SEMI members companies. In a time when the stakes for the industry have risen to new levels, direct engagement with lawmakers in the nation’s capital by SEMI and its members is critical. The SEMI Washington Forum is a terrific way for members to more clearly understand the impact of key pieces of legislation and gain firsthand experience in influencing policy and helping lawmakers better understand the industry. If you are interested in learning more about the SEMI Washington Forum or SEMI’s public policy program, please contact Jamie Girard by email at [email protected].

Cyient Limited (“Cyient”), a global provider of engineering, manufacturing, geospatial, networks, and operations management services, today announced that its step down subsidiary Cyient Europe Ltd. has acquired AnSem N.V., a fabless, custom analog and mixed-signal application-specific integrated circuits (ASICs) design company. AnSem specializes in advanced analog, radio frequency, and mixed-signal integrated circuit design and provides custom ASICs for clients around the world across key industries, including automotive, medical, industrial, smart home, and smart grid, with long-life applications of five to ten years.

Incorporated in 1998 as a spin-off of the university of Leuven and with the support of imec – the research and innovation hub in nanoelectronics and digital technologies, AnSem has a strong team of technical and domain experts and has established itself as a well-known name in the field of analog and mixed-signal ASICs. Headquartered in Leuven, Belgium, AnSem has been certified as an ISO 9001:2015 company with a strong focus on solving complex challenges. Through its proven history of 100% first-time-functional designs, AnSem not only provides significant cost savings, but also time-to-market benefits, making this Cyient’s center of excellence. AnSem has revenue of ~$10 Million and 20%+ operating margin.

“AnSem’s leading-edge, custom mixed-signal analog integrated circuit (IC) capability allows Cyient to offer turnkey ICs, starting from concept circuit to final production. Through this acquisition, Cyient can help its clients develop smart analog sensors to capture data, while leveraging our IoT and analytics solutions to provide actionable insights,” said Suman Narayan, Senior Vice President for Semiconductor, IoT, and Analytics at Cyient.

“We are excited to become a part of the Cyient family and expand our capabilities to a larger customer base,” said AnSem’s CEO and Co-founder, Stefan Gogaert. “Over the years, AnSem has built an impeccable record of custom analog ASIC solutions delivery, a long-term customer base, and an unparalleled capability to develop, validate, and verify complex solutions. Thanks to this acquisition, our ability to deliver the volume of ASICs that our customers need to stay ahead of the competition will become even stronger. It also will enable us to be in the leading position that we were already aiming for.”

“Innovation is an integral part of imec‘s culture, and throughout the years, we have continuously supported regional start-up activities related to microelectronics and nanoelectronics. AnSem is one of the success stories that has grown to become a profitable company in analog, RF and mixed-signal design with an international customer base,” said Ludo Deferm, Executive Vice President at imec and member of the Board of Directors of AnSem. “We are delighted with the acquisition of AnSem by Cyient. This is a confirmation of AnSem’s business value and the strength of the eco-system around imec. We are hopeful that this acquisition is the beginning of a close collaboration between Cyient and imec, as well as with other Flemish companies.”

Cyient expects this transaction to be EPS accretive.

Synopsys, Inc. (Nasdaq: SNPS) today announced certification of the Synopsys Design Platform with TSMC’s latest Design Rule Manual (DRM) for advanced 7-nanometer (nm) FinFET Plus process technology. With several test chips taped out and production designs currently under development by multiple customers, this certification by TSMC enables a wide range of designs from high-performance computing and high-density to low-power mobile applications using the Synopsys Design Platform.

This certification is a milestone for TSMC’s extreme ultraviolet lithography (EUV) process that enables significant area savings while maintaining high performance when compared to non-EUV process nodes.

The Synopsys Design Platform, anchored by Design Compiler Graphical synthesis and IC Compiler™ II place-and-route tools, has been enhanced to take full advantage of TSMC’s 7-nm FinFET Plus for high-performance designs. Design Compiler Graphical is capable of automatically inserting via pillar structures to boost performance and prevent signal electromigration (EM) violations, and can pass the information to IC Compiler II for further optimization. It also automatically applies non-default rules (NDR) during synthesis and performs layer-aware optimization to improve design performance. These optimizations, including IC Compiler II bus routing, continue throughout the place-and-route flow to meet stringent delay-matching requirements of high-speed network.

PrimeTime® timing analysis advanced waveform propagation (AWP) and parametric on-chip variation (POCV) technologies have been optimized to address increased waveform distortion and non-Gaussian variation effects of higher performance and lower voltage operation. In addition, PrimeTime’s physically-aware signoff has been expanded to support via-pillars.

Synopsys has enhanced the Design Platform to perform physical implementation, parasitic extraction, physical verification, and timing analysis to support TSMC’s WoW technology. The physical implementation flow with IC Compiler II provides full support for wafer staking designs, from initial die floorplan preparation to placement and assignment of bumps to implementation of die routing. Verification is done by IC Validator for DRC/LVS checks, and Synopsys’ StarRC tool performs parasitic extraction.

“Ongoing collaboration with Synopsys and early customer engagements on TSMC’s 7-nanometer FinFET Plus process technology are delivering differentiated platform solutions that help our mutual customers bring innovative new products to market faster,” said Suk Lee, senior director of the Design Infrastructure Marketing Division at TSMC. “Certification of the Synopsys Design Platform enables our mutual customers’ designs in our first mass-production, EUV-enabled technology.”

“Our collaboration with TSMC on their mass-production 7-nanometer FinFET Plus process allows companies to confidently begin designing their increasingly large SoC and multi-die chips with the highly-differentiated Synopsys Design Platform,” said Michael Jackson, corporate vice president of marketing and business development for the Design Group at Synopsys. “Certification on TSMC’s 7-nanometer FinFET Plus process enables our customers to benefit from significant power, performance, and area improvements of an advanced EUV process, while accelerating time-to-market for their differentiated products.”