Category Archives: Semiconductors

UltraSoC today announced a significant extension of its embedded analytics architecture, allowing designers and innovators to incorporate powerful data-driven features into their products. Developers in the automotive, storage and high performance computing industries can now integrate even more sophisticated hardware-based security, safety and performance tuning capabilities within their products, as well as reaping substantial time-to-market and cost benefits of using UltraSoC in the system on chip (SoC) development cycle.

The new features allow SoC designers to build on-chip monitoring and analytics systems with up to 65,000 elements, allowing seamless support for systems with many thousands of processors. Future iterations will allow even higher numbers of processors for Exascale systems. In addition to this dramatically improved scaling capability, new System Memory Buffer (SMB) IP allows the embedded analytics infrastructure to handle the high volumes of data generated by multicore systems, and to cope with “bursty” real-world traffic.

The new UltraSoC architecture is capable of monitoring effectively unlimited numbers of the internal building blocks that make up the most complex SoC products – and to analyze the impact on system-level behavior of the interactions between them. Such heterogeneous multicore chips are becoming increasingly common, particularly in enabling the artificial intelligence and machine learning technologies required in leading edge applications such as driverless cars.

Dave Ditzel, Founder and CEO of Esperanto, commented: “Esperanto’s mission is to enable the most energy-efficient high-performance computing systems for artificial intelligence, machine learning and other emerging applications. That requires us to put over a thousand RISC-V processors and AI/ML accelerators on a single chip; UltraSoC’s ability to match that level of scaling with monitoring, analytics and debug capabilities is a vital enabler for our business.”

UltraSoC CEO, Rupert Baines, said: “Our solutions are unique in the market in their ability to deal with multiple heterogeneous processors, standard and proprietary bus structures and even custom logic. This dramatic extension of our architecture takes us even further ahead of traditional solutions – both in the debug and development arena, and in allowing our customers to incorporate in-life monitoring capabilities to ensure security, functional safety and real-world performance optimization.”

UltraSoC’s system-level monitoring and analytics capabilities extend beyond the chip’s core processing components to all parts of the system – which may include thousands of IP blocks and subsystems, buses, interconnects and software. The new features within the UltraSoC architecture allow chip designers to deploy tens of thousands of monitoring and analytics modules within a single infrastructure. By providing an integrated, coherent analysis of the behavior of the system, UltraSoC significantly reduces the development burden for next-generation machine learning and artificial intelligence applications, as well as allowing the implementation of innovative product features such as hardware-based security and functional safety.

Extension of the UltraSoC architecture to encompass effectively unlimited monitoring capabilities helps developers to address the problems of systemic complexity which are among the most pressing issues faced by the electronics industry today. In addition to the sheer size of modern SoCs, machine learning and artificial intelligence algorithms are often inherently non-deterministic: because they devise their own ways of solving problems by ‘learning’, it is impossible for the system’s original designer to predict how they will behave in the final application. In-life monitoring of the chip’s behavior is therefore the only way of getting a true picture of what is going on inside the chip, and the wider system.

The complex interactions between multiple hardware blocks, firmware and software within SoCs have already made real-time in-life monitoring an indispensable tool for SoC designers. Changes in design approaches are also making system-wide monitoring more necessary than ever. Agile software development and ad hoc programming practices inherently require high-granularity visibility of the real system. Similarly, system hardware and software may not be ‘architected’ in the traditional sense: again, engineers need clear visibility of the run-time behavior of their systems.

eSilicon, a provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today the achievement of multiple milestones related to the company’s growth in the tier one FinFET ASIC market, serving high-bandwidth networking, high-performance computing, AI and 5G infrastructure.

Critical requirements to serve these markets include leading-edge, high-performance, differentiating semiconductor IP that is validated in advanced process nodes, a track record of successful design and fabrication of complex, FinFET-class ASICs and expertise in the design and manufacture of 2.5D package assemblies, including the integration of HBM memory stacks.

In the fall of last year, eSilicon announced availability of its neuASIC™ IP platform for AI ASIC design. The innovative IP platform includes an HBM2 PHY and AI mega/giga cells, including a convolution engine and accelerator builder software, all verified in 7nm technology. In that same time frame, the company announced that its 56G long-reach 7nm DSP SerDes was available for licensing.

In January, 2019, eSilicon announced a new high-performance test system to facilitate customer validation of its SerDes IP. At the recent DesignConshow, eSilicon demonstrated the new test system and its SerDes driving a five-meter copper cable at 56Gbps with very low error rates. Several customer engagements are underway with this SerDes IP, and customer feedback is validating its best-in-class capabilities. Also in January, eSilicon announced the formation of a technical advisory board for its AI initiatives staffed by three prominent technologists from academia and industry.

The company is in active production bring-up with two FinFET designs, including 2.5D technology utilizing its HBM2 PHY. All performance parameters are being met and both designs are on track to achieve full-scale production this year. One of the designs represents the largest ASIC eSilicon has ever built. It is believed to be the largest chip the foundry has ever produced as well.

“Our customers demand best-in-class IP, advanced ASIC and packaging expertise and the resources and technical depth to facilitate production bring-up of the final device,” said Hugh Durdan, vice president of strategy and products at eSilicon. “I am pleased to say we are delivering on all fronts. Recently, a tier one customer reported that they were usually quite critical of all IP. They went on to say they could find nothing to criticize after detailed evaluation of our SerDes.”

eSilicon will be presenting “A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET” at ISSCC in San Francisco on February 18. The company will be demonstrating its SerDes live at ISSCC that day as well. You can also find eSilicon at OFC in San Diego from March 5-7 (booth #5416), where the company will present two high-speed SerDes demonstrations and a demonstration if its HBM2 PHY.

During IBM THINK 2019, IBM’s annual conference focused on technology and business, Samsung SDS announced it is continuing its collaboration with IBM in support of advancing Hyperledger Fabric, an open source cross-industry blockchain technology, with recent code contributions, research and a new white paper.

As a contributor to Hyperledger Fabric, Samsung SDS is working to improve fabric capabilities and actively contributing its new “Accelerator” code to the open source community. The new code is expected to significantly improve Hyperledger Fabric performance for specific use cases.

Samsung SDS is also making a new white paper available, “Accelerating Throughput in Permissioned Blockchain Networks,” co-written by IBM. The paper validates the applicability of Accelerator to Hyperledger Fabric, provides a roadmap and also illustrates performance improvement in terms of transactions per second. A copy of the white paper and the Innovation Sandbox environment is now available for external developers to test. (https://github.com/nexledger/accelerator)

While this technical initiative is being rigorously validated from the open source Hyperledger community, Samsung SDS will prepare to become IBM’s key go-to-market reseller partner of IBM Blockchain Platform in Korea.

Ted Kim, Vice President, Blockchain Team from Samsung SDS America has been named to the IBM Blockchain Board of Advisors. Additionally, during the IBM Think Conference in San Francisco, Kiwoon Sung, Head of Blockchain Research Lab, Samsung SDS, will discuss the company’s blockchain innovation efforts at a session entitled, “New Blockchain Solutions emerging from the IBM Blockchain ecosystem.”

Hyperledger is an open source collaborative effort created to advance cross-industry blockchain technologies. It is a global collaboration including leaders in finance, banking, Internet of Things, supply chains, manufacturing and Technology. The Linux Foundation hosts Hyperledger under the foundation. To learn more, visit: https://www.hyperledger.org/.

IC Insights recently released its new Global Wafer Capacity 2019-2023 report that provides in-depth detail, analyses, and forecasts for IC industry capacity by wafer size, process geometry, region, and product type through 2023.  Figure 1 shows the world’s installed monthly wafer production capacity by geographic region (or country) as of December 2018.  Each number represents the total installed monthly capacity of fabs located in that region regardless of the headquarters location of the company that own the fab(s).  For example, the wafer capacity that South Korea-based Samsung has installed in the U.S. is counted in the North America capacity total, not in the South Korea capacity total.  The ROW “region” consists primarily of Singapore, Israel, and Malaysia, but also includes countries/regions such as Russia, Belarus, and Australia.

Figure 1

As shown, Taiwan led all regions/countries in wafer capacity with 21.8% share, a slight increase from 21.3% in 2017 (Taiwan first became the global wafer capacity leader in 2015.)  Taiwan’s capacity share was only slightly ahead of South Korea, which accounted for 21.3% of global wafer capacity in 2018, according to the Global Wafer Capacity 2019-2023 report.  TSMC in Taiwan and Samsung and SK Hynix in South Korea accounted for the vast share of wafer fab capacity in each country and were the top three capacity leaders worldwide. TSMC held 67% of Taiwan’s capacity while Samsung and SK Hynix represented 94% of the installed IC wafer capacity in South Korea at the end of 2018.

Japan remained firmly in third place with just over 16.8% of global wafer fab capacity.  Micron’s purchase of Elpida several years ago and other recent major changes in manufacturing strategies of companies in Japan, including Panasonic spinning off some of its fabs into separate companies, means that the top two companies (Toshiba Memory and Renesas) accounted for 62% of that country’s wafer fab capacity.

China showed the largest increase in global wafer capacity share in 2018, rising 1.7 percentage points from a 10.8% share in 2017 to a 12.5% share in 2018.  It nearly tied North America as the fourth-largest country/region with installed capacity.  A lot of buzz circulated about China-based startups and their new wafer fabs during 2018. Meanwhile, other global companies expanded their manufacturing presence in China last year so it would be expected that the country’s capacity share would show a significant increase.  China’s percentage gain came mostly at the expense of ROW and North America.  The share of capacity in the ROW region slipped 0.8 percentage points from 9.5% in 2017 to 8.7% in 2018. North America’s share of capacity declined 0.4 percentage points in 2018.

Silicon Catalyst, the world’s only incubator focused exclusively on accelerating solutions in silicon, today announced Soitec (Euronext Paris), a designer and manufacturer of semiconductor materials, as its first European Strategic Partner. This agreement provides Soitec access to early-stage silicon technology innovation targeting consumer, IoT and automotive segments and applications.

Silicon Catalyst is a Silicon Valley-based incubator providing silicon-focused start-ups access to a world-class network of advisors, design tools, silicon devices, networking, access to funding and marketing acumen needed to successfully launch their businesses. Soitec will engage in this start-up ecosystem to gain insight into the newest technologies and applications across high-growth markets, and to guide nascent technologies to successful market penetration.

“As a Strategic Partner of Silicon Catalyst, Soitec has a unique opportunity to grow our visibility among early-stage semiconductor companies,” said Thomas Piliszczuk, Executive VP of Global Strategy for Soitec. “Engineered substrates give semiconductor related start-ups a competitive edge in developing new high-performance, energy-efficient solutions. We are looking forward to supporting emerging trends and technology advancements with Silicon Catalyst’s distinguished portfolio of semiconductor entrepreneurs.”

“We are pleased to welcome Soitec as our first European Strategic Partner. Soitec is creating technical advances that are enabling the next generation of products across many market segments. Their SOI technology is a key ingredient to meet the diverse challenges for breakthrough differentiated semiconductor products, combining ultra-low power with excellent analog / mixed-signal performance,” stated Pete Rodriguez, CEO of Silicon Catalyst. “Joining our other Strategic Partners, Texas Instruments and ON Semiconductor, Soitec will participate in the selection of applicants to our incubator and provide guidance for our Portfolio Companies, contributing to the growth of startups that are creating the next generations of semiconductor innovation.”

Soitec’s substrate solutions, most notably silicon-on-insulator (SOI), address the full range of applications for electronics. SOI substrates are designed to support ultra-low power signal processing, wireless connectivity, power, image sensors and silicon photonics applications. Radio-frequency silicon-on-insulator (RF-SOI) substrates are the foundation of the RF incumbent technology for RF Front-End modules used in all smart phones manufactured today. RF-SOI and fully depleted SOI (FD-SOI) material enable ultra-low power connectivity, mobility, distributed AI and edge computing. Adding our new compound and piezo-electric on insulator substrates, Soitec offers a wide range of engineered substrates addressing numerous and fast growing segments like automotive, AI-IoT (AIoT) and 5G.

Global electronics manufacturing pillars Smart manufacturing, IoT and workforce development will come into sharp focus at SEMICON Southeast Asia (SEA) 2019, scheduled May 7-9, at the Malaysia International Trade and Exhibition Centre (MITEC) in Kuala Lumpur. Industry experts from around the world will gather at the region’s premiere global electronics manufacturing supply chain for critical insights into the semiconductor ecosystem, new business opportunities and collaboration. SEMICON SEA 2019 registration is now open.

Themed “Think Smart, Make Smart,” SEMICON SEA will feature three themed pavilions, five global pavilions, insightful keynote presentations and a host of technology forums to address key issues in the electronics manufacturing supply chain.

The new Workforce Pavilion addresses the critical industry shortage of skilled workers by attracting the young talent critical to sustaining industry innovation and growth. College students will meet with industry experts to explore career paths in microelectronics as tutorials enhance university students’ understanding of semiconductor manufacturing and opportunities.

The World of IoT Pavilion showcases applications and technologies enabling the IoT revolution. Companies from across the region will demonstrate technologies that enable Smart lifestyles as start-ups showcase pioneering and disruptive products and applications powered by IoT.

At the Smart Manufacturing Pavilion, the Artificial Intelligence exhibition zone highlights critical capabilities including collaborative robots, automated guided vehicles, cybersecurity and manufacturing excellence systems. The Pavilion’s Supply Chain Management zone provides insights into key elements of manufacturing excellence such as automated material handling and automated storage and retrieval. The Pavilion also features an augmented reality (AR) interactive human-machine interface to give visitors an immersive experience in smarter manufacturing processes.

SEMICON SEA 2019 will also feature an exclusive Hosted Buyer Programme. Hosted by SEMI, the customised business matching platform connects buyers in the electronics manufacturing supply chain with international solution providers for collaboration and business opportunities.

SEMICON Southeast Asia 2019 sponsors include ADLINK, Applied Materials, Cimetrix®, Evatec, GLOBALFOUNDRIES, Kanken Techno Co Ltd, Kulicke & Soffa, First Derivatives, Lam Research, Tokyo Electron and UPS.

For more information about SEMICON SEA is available on the event website.

By Mike Russo

For public policy lovers, civic-minded, engaged U.S. citizens, and people around the world interested in the U.S. President’s positions and priorities, the annual State of the Union address (SOTU) is “must-see TV.” This year, the anticipation and expectations were different than with past presidents. Trump is the first U.S. president who has used social media to the extreme that he has. Indeed, his Twitter feed is the most followed in history.

President Trump’s prolific Twitter feed has had an interesting impact on the SOTU. U.S. citizens and people from around the world already know President Trump’s positions on issues, his policy priorities and what gets him excited. There is an ongoing, direct line to the President’s thoughts throughout each and every day. In the past we looked to the SOTU for insights into what the sitting president is really thinking and his future policy priorities. Now, there isn’t much we don’t already know.

One looming question this year was whether President Trump would reach out in a conciliatory manner to help bridge the political divide and lay the groundwork to enable some public policy wins and avoid another government shutdown. While there were moments of conciliation, the President made it clear he would not move on areas that are most contentious with the other side of the aisle.

For example, the President unequivocally reiterated his intent to build “the wall.” While the message plays well to his base, it is, in effect, a frontal assault and challenge to Democrats. It’s hard to image that his staunch stance will help move the two parties to work together on substantive policy issues. It may also mean that the “wall” issue will occupy lawmakers time for the foreseeable future, sidelining debate on other important issues.

The best hope is that a bipartisan bill finds its way to the President’s desk that he can sign and use to “declare victory.” However, many political observers believe the likelihood of the President declaring a national security emergency is rising as a maneuver to ensure funding for “the wall” and avoid a shutdown. While such a declaration would most likely face a court challenge, the President could claim that his decision was a move of last resort and leverage the moment to position Democrats as obstructionists to his base. The scenario does not bode well for the bipartisan support necessary to address other issues.

What does this mean for our industry? Were there any points raised in the SOTU that would signal a change in what we are facing regarding trade, tariffs, export controls and immigration? Were any new issues or ideas raised that could help lift the global economy? In short, no. On one hand, the President cited his good relationship with the president of China, but on the other doubled down on his attacks on China, seeming to stand firm to bolster his position at the table as the U.S. and China trade talks continue.

What do these dynamics mean for SEMI Global Advocacy? In 2018 we were heavily engaged in efforts to prevent regulations that would inhibit our members’ ability to develop and deploy technologies and maintain global market access. We advanced our global advocacy model, leveraging our regional presence around the world. Many of the potential issues we faced emanated from the U.S., including those focused on controlling technology development, limiting trade and enhancing export controls. We also intensified our efforts to address industry talent pipeline issues.

In 2019, our public policy focus will be to continue to push back on tariffs, engage members to inform the rule-making process for export controls and to attempt to influence the immigration debate as it pertains to access to talent. In addition, while the U.S. R&D tax credit was made permanent through the tax cut in 2017, some of the provisions may have unintended consequences and will need to be modified. How the law is enacted will affect how businesses can deduct qualified research and development and other expenses from their taxable income, so we anticipate activity on the tax front as well.

It will also be a big year for SEMI on the workforce developmentfront. SEMI will continue to grow its existing High Tech U (HTU), university and mentor programs. In addition, SEMI will be positioning itself as the global leader in addressing issues related to the talent pipeline by approaching the problem with a full-spectrum, holistic approach that is intended to better address more immediate needs in attracting, training and retaining qualified talent. We’ll also focus on improving the industry image and exciting students at a younger age by providing experiential learning activities throughout a defined educational pathway. Stay tuned on this front as the full program unfolds.

In general, we will continue to build our relationships and stature as a leading voice for our members and the end-to-end semiconductor supply chain in the areas of “Talent, Trade, Tax and Technology” (SEMI’s “4 Ts”) and to ensure free and fair trade, access to markets, supply chain growth, IP protections and enhanced efforts to improve cybersecurity.

Mike Russo is VP of Global Industry Advocacy at SEMI. 

Source: SEMI Blog

Quantum computers promise to be a revolutionary technology because their elementary building blocks, qubits, can hold more information than the binary, 0-or-1 bits of classical computers. But to harness this capability, hardware must be developed that can access, measure and manipulate individual quantum states.

Researchers at the University of Pennsylvania’s School of Engineering and Applied Science have now demonstrated a new hardware platform based on isolated electron spins in a two-dimensional material. The electrons are trapped by defects in sheets of hexagonal boron nitride, a one-atom-thick semiconductor material, and the researchers were able to optically detect the system’s quantum states.

Researchers at the University of Pennsylvania’s School of Engineering and Applied Science have now demonstrated a new hardware platform based on isolated electron spins in a two-dimensional material. The electrons are trapped by defects in sheets of hexagonal boron nitride, a one-atom-thick semiconductor material, and the researchers were able to optically detect the system’s quantum states. Credit: Ann Sizemore Blevins

The study was led by Lee Bassett, assistant professor in the Department of Electrical and Systems Engineering, and Annemarie Exarhos, then a postdoctoral researcher in his lab.

Fellow Bassett Lab members David Hopper and Raj Patel, along with Marcus Doherty of the Australian National University, also contributed to the study.

It was published in the journal Nature Communications, where it was selected as an Editor’s Highlight.

There are number of potential architectures for building quantum technology. One promising system involves electron spins in diamonds: these spins are also trapped at defects in diamond’s regular crystalline pattern where carbon atoms are missing or replaced by other elements. The defects act like isolated atoms or molecules, and they interact with light in a way that enables their spin to be measured and used as a qubit.

These systems are attractive for quantum technology because they can operate at room temperatures, unlike other prototypes based on ultra-cold superconductors or ions trapped in vacuum, but working with bulk diamond presents its own challenges.

“One disadvantage of using spins in 3D materials is that we can’t control exactly where they are relative to the surface” Bassett says. “Having that level of atomic scale control is one reason to work in 2D. Maybe you want to place one spin here and one spin there and have them talk them to each other. Or if you want to have a spin in a layer of one material and plop a 2D magnet layer on top and have them interact. When the spins are confined to a single atomic plane, you enable a host of new functionalities.”

With nanotechnological advances producing an expanding library of 2D materials to choose from, Bassett and his colleagues sought the one that would be most like a flat analog of bulk diamond.

“You might think the analog would be graphene, which is just a honeycomb lattice of carbon atoms, but here we care more about the electronic properties of the crystal than what type of atoms it’s made of,” says Exarhos, who is now an assistant professor of Physics at Lafayette University. “Graphene behaves like a metal, whereas diamond is a wide-bandgap semiconductor and thus acts like an insulator. Hexagonal boron nitride, on the other hand, has the same honeycomb structure as graphene, but, like diamond, it is also a wide-bandgap semiconductor and is already widely used as a dielectric layer in 2D electronics.”

With hexagonal boron nitride, or h-BN, widely available and well characterized, Bassett and his colleagues focused on one of its less well-understood aspects: defects in its honeycomb lattice that can emit light.

That the average piece of h-BN contains defects that emit light had previously been known. Bassett’s group is the first to show that, for some of those defects, the intensity of the emitted light changes in response to a magnetic field.

“We shine light of one color on the material and we get photons of another color back,” Bassett says. “The magnet controls the spin and the spin controls the number of photons that the defects in the h-BN emit. That’s a signal that you can potentially use as a qubit.”

Beyond computation, having the building block of a quantum machine’s qubits on a 2D surface enables other potential applications that depend on proximity.

“Quantum systems are super sensitive to their environments, which is why they’re so hard to isolate and control,” Bassett says. “But the flip side is that you can use that sensitivity to make new types of sensors. In principle, these little spins can be miniature nuclear magnetic resonance detectors, like the kind used in MRIs, but with the ability to operate on a single molecule.

Nuclear magnetic resonance is currently used to learn about molecular structure, but it requires millions or billions of the target molecule to be assembled into a crystal. In contrast, 2D quantum sensors could measure the structure and internal dynamics of individual molecules, for example to study chemical reactions and protein folding.

While the researchers conducted an extensive survey of h-BN defects to discover ones that have special spin-dependent optical properties, the exact nature of those defects is still unknown. Next steps for the team include understanding what makes some, but not all, defects responsive to magnetic fields, and then recreating those useful defects.

Some of that work will be enabled by Penn’s Singh Center for Nanotechnology and its new JEOL NEOARM microscope. The only transmission electron microscope of its kind in the United States, the NEOARM is capable of resolving single atoms and potentially even creating the kinds of defects the researchers want to work with.

“This study is bringing together two major areas of scientific research,” Bassett says. “On one hand, there’s been a tremendous amount of work in expanding the library of 2D materials and understanding the physics that they exhibit and the devices they can make. On the other hand, there’s the development of these different quantum architectures. And this is one of the first to bring them together to say ‘here’s a potentially room-temperature quantum architecture in a 2D material.'”

Two-dimensional transition metal dichalcogenides (2D-TMDs) such as monolayer molybdenum disulphide (MoS2) are atomically thin semiconductors in which a layer of transition metal atom is sandwiched between two layers of chalcogen atoms, in the form MX2. They can exist in both a semiconducting 1H-phase and a quasi-metallic 1T’-phase, with each having a different crystal structure. The 1T’-phase is particularly interesting as theoretical predictions show that it has potential to be used in less conventional applications, such as super capacitor electrodes and hydrogen evolution reaction catalysts. However, the quantity of 1T’-phase 2D-TMDs that can be obtained by converting them from the 1H-phase through a phase transition process is low. This potentially limits the use of such novel materials for a wide range of applications.

Molecules of monolayer molybdenum disulphide (MoS2) and tungsten diselenide (WSe2) on top of a metal substrate. Credit: National University of Singapore

A research team led by Professor Andrew Wee from the Department of Physics at the National University of Singapore’s (NUS) Faculty of Science has discovered that while different 2D-TMD materials have their own intrinsic energy barriers when transiting from the 1H to the 1T’ structural phase, the use of a metallic substrate with higher chemical reactivity can significantly increase the 1H- to 1T’- phase transition yield. This is a convenient and high-yielding method to obtain 2D-TMD materials in their 1T’ metallic phase. When the 2D-TMD material is placed in contact with the metal substrate, such as gold, silver and copper, electric charges are transferred from the metal substrate to the 2D-TMD material. Furthermore, it weakens the bond strength of the 2D-TMD structure significantly, and increases the magnitude of the interfacial binding energy. This in turn increases the susceptibility of the 1H-1T’ structural phase transition. As a result, this enhanced interfacial hybridisation at the interface of the two materials makes the 1H-1T’ structural phase transition much easier to achieve.

The NUS research team combined multiple experimental techniques and first-principles calculations in their research work. These includes optical spectroscopies, high resolution transmission electron microscopy and density functional theory based first-principles calculations to identify the phase changes – both 1H- and 1T’-phases – of the 2D-TMDs in the samples.

This study provides new insights on the influence of interfacial hybridisation affecting the phase transition dynamics of 2D-TMDs. The findings can potentially be used in a model system for the controlled growth of 2D-TMDs on metallic substrates, creating possibilities for new 2D-TMDs-based device applications.

Prof Wee said, “The controllability of the semiconductor to metal phase transition at the 2D-TMD and metal interfaces can enable new device applications such as low contact resistance electrodes.”

Robust demand for more content for mobile, Internet of Things (IoT), automotive and industrial applications will drive production of 700,000 200mm wafers from 2019 to 2022, a 14 percent increase, reports SEMI, the global industry association serving the electronics manufacturing supply chain, in its latest Global 200mm Fab Outlook. The increase brings total 200mm wafer fab capacity to 6.5 million wafers per month as many devices have found their sweet spot with 200mm wafer fabrication.

Strong 200mm wafer growth mirrors sound capacity demand seen across various industry segments. From 2019 to 2022, for example, wafer shipments for MEMS and sensors devices are expected to increase 25 percent while shipments for power devices and foundries are forecast to jump 23 percent and 18 percent, respectively, the SEMI Global 200mm Fab Outlook shows. The increases in 200mm fab count and installed capacity reflect continuing 200mm industry strength as it continues to add capacity and even open new fabs.

The SEMI Global 200mm Fab Outlook report has added seven new facilities, with 160 updates to 109 fabs, since its most recent publication in July 2018. A total of 16 new facilities or lines, 14 of them volume fabs, are expected to begin operation between 2019 and 2022. The report takes into account both equipment transferred from one fab to another and equipment revitalized after being held in storage, such as for SK Hynix and Samsung.

Across the industry, recent sudden changes in investment plans for leading-edge devices such as memory have triggered a projected double-digit decline in spending in 2019. However, with demand for mature devices using wafers 200mm and smaller stable or evening growing, it would be no surprise to see plans emerge for even more 200mm capacity and new fabs to meet growing demand.

More information about the SEMI Global 200mm Fab Outlook report from 2019 to 2022 is available here.