Category Archives: Semiconductors

No dust mops needed here. The inside of a chip factory is cleaner than about any other place you can visit on Earth. To avoid contaminating the chip-making process, the air in an Intel fab clean room is filtered to 1,000 times fewer airborne particles than a sterile hospital operating room.

The “Team Room” inside Intel’s Fab D1X in Hillsboro, Oregon, is unique.

It’s the sole conference room inside this entire multibillion-dollar factory. Though the fab sprawls over four football fields, every square foot is supremely expensive and valuable. That’s why Intel designed leading-edge Fab D1X with one and only room like this.

Intel operations leaders gather for the daily "8:20" – a morning huddle inside Fab D1X to ensure that the Hillsboro, Oregon, chip factory is running smoothly. Up to 30 people may squeeze into this room to confer on factory tool status, parts availability, operating forecasts, experts who may be needed or other urgent issues. The fab – the size of four football fields – runs 24/7/365. (Credit: Walden Kirsch/Intel Corporation)

Intel operations leaders gather for the daily “8:20” – a morning huddle inside Fab D1X to ensure that the Hillsboro, Oregon, chip factory is running smoothly. Up to 30 people may squeeze into this room to confer on factory tool status, parts availability, operating forecasts, experts who may be needed or other urgent issues. The fab – the size of four football fields – runs 24/7/365. (Credit: Walden Kirsch/Intel Corporation)

Anything entering the fab – including the Fab D1X Team Room – must be thoroughly scrubbed or swabbed. Human skin and hair must be almost entirely covered. Workers wear head-to-toe bunny suits, protective glasses, two pairs of gloves, booties, hoods, and face masks. Workers often recognize one another by their build or their gait, not their face.

In the D1X Team Room, anything that could shed particulates is verboten. No makeup, for example. Common supplies like paper and pencils are off-limits too – they both can create micro-dust. Only ink pens and special fab-approved synthetic paper are allowed in. This is the first photo inside the D1X Team Room ever shared externally. See more images from Intel’s fabs: Intel Manufacturing Images

More than Moore (MtM) wafer demand reached almost 45 million 8-inch eq wafers in 2017. The wafer demand is expected to reach more than 66 million 8-inch eq. wafers by 2023, with an almost 10% CAGR between 2017 and 2023. According to Yole Développement (Yole)’s definition, the MtM applications include MEMS & sensors, CIS , and power, along with RF devices.

For the first time, the market research and strategy consulting company Yole announces a global technology & market analysis dedicated to the MtM industry. The Wafer Starts for More Than Moore Applications report is the first part of a valuable series that will be released all year long.

“Yole’s analysts are part of the powerful semiconductor community”, explains Emilie Jolivet, Director, Semiconductor and Software at Yole. “Their daily interactions with leading companies allow them to collect a large amount of relevant data and cross their vision of market segments’ evolution and technology breakthroughs. Wafer Starts for More Than Moore Applications report is the first opportunity to get an overview of the MtM industry based on a 20-year expertise.”

“Numerous megatrend market drivers will contribute to MtM devices’ growth”, confirms Amandine Pizzagalli, Technology & Market Analyst, Semiconductor Manufacturing at Yole. “The megatrends are covering the following market segments: 5G including wireless infrastructure & mobile, mobile with additional functionalities, voice processing, smart automotive, AR/VR and AI.”

What is the status of the MtM wafer demand? Which market drivers will contribute to the growth of MtM devices? Which semiconductor substrate materials and wafer diameter dominate the MtM industry today? What are Yole’s expectations for the next 5 years? The analysts propose you a comprehensive analysis of the MtM wafer demand market.

Driven by the increasing deployment of renewable energy sources , and industrial motor drives, as well as the growing EV/HEVs industry, power devices’ wafer market size will grow at an almost 13% CAGR from 2017 to 2023. In 2017, it accounted for more than 60% of overall MtM wafer starts. According to Yole’s analysts, it will continue dominating the MtM industry.

In parallel, 5G, a hot topic today, will likely be a huge part of the MtM evolution, bringing any service to any user anywhere, but also requiring new antennas, along with filtering functionality. These stringent requirements will lead to increasing demand for RF components like RF filters, PAs , and LNAs to ensure access to tomorrow’s radio network.

Meanwhile, the demand for advanced mobile applications that integrate more functionalities will require aggregating more and more devices such as fingerprint sensors, ambient light sensors, 3D sensing, microphones, and inertial MEMS devices. This will, in the near future, contribute to strong wafer growth in the MEMS & sensors wafer market. Additionally, smart automobiles have reached a new level of complexity requiring the development and integration of new sensors. As such, Yole expects smart automobiles to drive consistent growth of CIS and sensor wafer production over the next five years, fueled by the expanding integration of high-value sensing modules like radar, imaging, and LiDAR. Although automotive will be mainly supported by these growth areas, classical MEMS & sensors such as MEMS pressure sensors and inertial MEMS will still continue growing at a reasonable rate, supporting the standard automotive world.

Yole’s investigations are based on numerous discussions with leading semiconductor players. Applied Materials Inc. is part of them. Amandine Pizzagalli recently had the opportunity to debate with Mike Rosa, Head of Marketing, 200mm Equipment Products Group (EPG) at Applied Materials. During this discussion, both exchanged their vision of the MtM industry and its evolution.

“Today, while many of these technologies exist on 200mm and below wafer sizes much of this business falls within the purview of the 200mm Equipment Product Group”, explains Mike Rosa from Applied Materials. “With the exception of Power Bipolar-CMOS-DMOS (BCD) and some Discretes, 2.5D Interposer, CMOS Image Sensors and some Photonics devices in the market – all other technologies in the MtM segment are manufactured on 200mm and 150mm wafer sizes today. So, to support our customers on current and future wafer size requirements, we work across the company to share the domain knowledge acquired, for example in the 200mm group on MEMS or Discrete Power, with the 300mm group in order to ensure continuity of technology development onto the larger wafer sizes.”

The full interview is available on i-micronews.com, semiconductor manufacturing news or click Here.

In terms of wafer size, the MtM wafer market is dominated by the 6-inch wafer format, followed by the 8-inch size, which is mostly supported by power device applications. However, though 6-inch will continue increasing in the next few years, its share will decrease compared to 8-inch. “We expect 8-inch wafer diameter to progress significantly and surpass the 6-inch wafer size by 2023”, explains Amandine Pizzagalli from Yole. And she adds: “This transition will be driven first by power and MEMS & sensor applications, where the vast majority will convert their components from 6-inch to 8-inch over the next five years due to increasing volume production.”

Nevertheless, 12-inch will represent the fastest growth from 2017 to 2023, with a 15% CAGR. The 12-inch wafer demand should also grow from 3.3 million units in 2017 to 7.5 million in 2023, mainly fueled by BSI CIS (Including 3D stacked BSI, 3D hybrid BSI).

On the other side, 4-inch wafer diameter is in large demand today for MtM applications driven by RF SAW filter products. However, 4-inch’s adoption will decrease due to the transition from 4-inch to 6-inch for these applications. Yole still sees some MtM products manufactured in wafer sizes below 4-inch, i.e. 3-inch and 2-inch wafer formats. However, these represent a very small volume, and the analysts expect such sizes to die out, aside from small volumes still used for producing MEMS, power, and RF SAW devices.

The Wafer Starts for More Than Moore Applications report is the first research performed by Yole’s analysts, gathering all the wafer starts markets for MtM applications. Yole’s market forecast methodology is based on both top bottom and a bottom up approach with dozens of interviews of companies across the entire semiconductor value chain. With this report, the company proposes an assessment of the wafers market for MEMS & Sensors, CIS, power and RF devices. This analysis reveals the market metrics at wafer market level for the whole MtM industry from 2017-2023. It evaluates market developments in terms of market size, substrate sizes/formats, and by MtM application.

Yole’s report also discloses the competitive landscape with key players in technology development and manufacturing. A detailed analysis of the key market drivers that will shape the MtM market in the future are also part of this technology & market report.

Combined sales for optoelectronics, sensors and actuators, and discrete semiconductors (known collectively as O-S-D) increased 11% in 2017—more than 1.5 times the average annual growth rate in the past 20 years—to reach an eighth consecutive record-high level of $75.3 billion, according to IC Insights’ new 2018 O-S-D Report—A Market Analysis and Forecast for Optoelectronics, Sensors/Actuators, and Discretes. Total O-S-D sales growth is expected to ease back in 2018 but still rise by an above average rate of 8% in 2018 to $81.1 billion, based on the five-year forecast of the new 375-page annual report, which became available this week.

In 2017, optoelectronics sales recovered from a rare decline of 4% in 2016, rising 9% to $36.9 billion, while the sensors/actuators market segment registered its second year in a row of 16% growth with revenues climbing to $13.8 billion, and discretes strengthened significantly, increasing 12% to $24.6 billion.  The new O-S-D Report forecast shows optoelectronics sales growing 8% in 2018, sensors/actuators rising 10%, and discretes growing 5% this year (Figure 1).

Figure 1

Figure 1

Between 2017 and 2022, sales in optoelectronics are projected to increase by a compound annual growth rate (CAGR) of 7.3% to $52.4 billion, while sensors/actuators revenues are expected to expand by a CAGR of 8.9% to $21.2 billion, and the discretes segment is seen as rising by an annual rate of 3.1% to $28.7 billion in the final year of the report’s forecast.  In the five-year forecast period, O-S-D growth will continue to be driven by strong demand for laser transmitters in optical networks and CMOS image sensors in embedded cameras, image recognition, machine vision, and automotive applications as well as the proliferation of other sensors and actuators in intelligent control systems and connections to the Internet of Things (IoT).  Power discretes (transistors and other devices) are expected to get a steady lift from the growth in mobile and battery-operated systems as well as good-to-modest global economic growth in most of the forecast years through 2022, the report says.

Combined sales of O-S-D products accounted for about 17% of the world’s $444.7 billion in total semiconductor sales compared to less than 15% in 2007 and under 13% in 1997.  Since the mid-1990s, total O-S-D sales growth has outpaced the much larger IC market segment because of strong and relatively steady increases in optoelectronics and sensors. However, this trend was reversed recently mostly due to a 77% surge in sales of DRAMs and 54% jump in NAND flash memory in 2017.

The 2017 increase for total O-S-D sales was the highest growth rate in the market group since the 37% surge in the strong 2010 recovery year from the 2009 semiconductor downturn.  In addition, 2017 was the first year since 2011 when all three O-S-D market segments reached individual record-high sales, says IC Insights’ new report.  The 2018 O-S-D Report also shows that sales of sensor and actuator products made with microelectromechanical systems (MEMS) technology grew 18% in 2017 to a record-high $11.5 billion.

The market for organic materials used to manufacture organic light-emitting diode (OLED) display panels jumped during the second half of 2017, according to IHS Markit (Nasdaq: INFO), a world leader in critical information, analytics and solutions. The market, as measured by revenue, was estimated to be $355 million in the second half of 2017, up 20 percent from the first half of the year.

According to the OLED Materials Market Tracker by IHS Markit, in 2016 and the first half of 2017, the OLED materials market seemed saturated, posting revenues at almost the same level. However, the sudden spike in growth was observed in the second half of 2017.

“The growth of OLED materials demand has been offset by price reduction, resulting in the market saturation until mid-2017.” said Jimmy Kim, Ph.D. and senior principal analyst at IHS Markit. “However, the launch of the iPhone X as well as the expansion of OLED panel manufacturing capacity boosted the demand in the second half.”

Revenue_forecast_for_OLED_materials_market

The iPhone X, Apple’s first OLED panel-using smartphone, was launched in the third quarter of 2017 and it brought a huge additional demand for OLED materials. At the same time, LG Display has set up a new E4-2 fab for OLED TV panels.

“Apple is expected to apply OLED panels to more of its products and OLED TV is also one of the most emerging products in the TV market,” Kim said. “Considering demand growth and current investment plans regarding OLED manufacturing capacities, the OLED materials market is expected to continue to grow until 2020, reaching $824 million by the second half of 2020.

The OLED Material Market Tracker by IHS Markit includes market analysis and forecasts for organic light-emitting materials, consumption of the materials by AMOLED panel makers, and the status of organic light-emitting materials suppliers.

NVIDIA and Arm today announced that they are partnering to bring deep learning inferencing to the billions of mobile, consumer electronics and Internet of Things devices that will enter the global marketplace.

Under this partnership, NVIDIA and Arm will integrate the open-source NVIDIA Deep Learning Accelerator (NVDLA) architecture into Arm’s Project Trillium platform for machine learning. The collaboration will make it simple for IoT chip companies to integrate AI into their designs and help put intelligent, affordable products into the hands of billions of consumers worldwide.

“Inferencing will become a core capability of every IoT device in the future,” said Deepu Talla, vice president and general manager of Autonomous Machines at NVIDIA. “Our partnership with Arm will help drive this wave of adoption by making it easy for hundreds of chip companies to incorporate deep learning technology.”

“Accelerating AI at the edge is critical in enabling Arm’s vision of connecting a trillion IoT devices,” said Rene Haas, executive vice president, and president of the IP Group, at Arm. “Today we are one step closer to that vision by incorporating NVDLA into the Arm Project Trillium platform, as our entire ecosystem will immediately benefit from the expertise and capabilities our two companies bring in AI and IoT.”

Based on NVIDIA® Xavier™, an autonomous machine system on a chip, NVDLA is a free, open architecture to promote a standard way to design deep learning inference accelerators. NVDLA’s modular architecture is scalable, highly configurable and designed to simplify integration and portability.

NVDLA brings a host of benefits that speed the adoption of deep learning inference. It is supported by NVIDIA’s suite of powerful developer tools, including upcoming versions of TensorRT, a programmable deep learning accelerator. The open-source design allows for cutting-edge features to be added regularly, including contributions from the research community.

The integration of NVDLA with Project Trillium will give deep learning developers the highest levels of performance as they leverage Arm’s flexibility and scalability across the wide range of IoT devices.

“This is a win/win for IoT, mobile and embedded chip companies looking to design accelerated AI inferencing solutions,” said Karl Freund, lead analyst for deep learning at Moor Insights & Strategy. “NVIDIA is the clear leader in ML training and Arm is the leader in IoT end points, so it makes a lot of sense for them to partner on IP.”

ON Semiconductor (Nasdaq: ON) today announced it has recognized 20 companies with supplier excellence awards. Selected from among the company’s extensive list of preferred global suppliers, the 2017 award winners represent partners who have demonstrated a deep commitment to ensuring high quality and supply continuity in an evolving semiconductor market.

elected from more than 3,000 active production suppliers, the finalists gathered for a two-day awards event and executive conference in Hong Kong, China, with the focus of anticipating the future of semiconductor growth and accelerating customer needs.

“As a top 20 global semiconductor design and manufacturing company, ON Semiconductor creates innovative semiconductor and general electronic component solutions to solve our customers’ design challenges and reduce their time to market,” said Jeffrey Wincel, vice president and chief procurement officer at ON Semiconductor. “All the suppliers recognized today demonstrated a similar commitment to collaboration and partnership. These strong relationships are key in delivering on our business strategy, including the areas of product innovation, customer satisfaction and growth.”

Full list of award winners:

Front End (FE) Direct Material Supplier: Konfoong Materials International Company, LTD.
Back End (BE) Direct Material Supplier: Chang Wah Technology Co., Ltd.
FE Site Supplier: Plansee SE
BE Site Supplier: KETECA Singapore (Pte) Ltd
BE External Manufacturing: King Yuan Electronics Co. Ltd.
FE External Manufacturing: JiangYin ChangDian Advanced Packaging Co., LTD
Corporate Services Supplier: DHL Supply Chain
Technology Leader Award: Mentor Graphics
BE Subcon Quality Award: GEM Services, Inc.
BE Perfect Quality Award: Indium Corporation
BE Perfect Quality Award: Henkel
FE Perfect Quality Platinum Award: Shin-Etsu Handotai Co., Ltd
FE Perfect Quality Platinum Award: Brewer Science, Inc.
FE Perfect Quality Platinum Award: JSR Micro, Inc.
FE Perfect Quality Platinum Award: JX Nippon Mining & Metals
FE Perfect Quality Gold Award: Cabot Microelectronics Corporation
FE Perfect Quality Gold Award: Grikin Advanced Materials Co., Ltd.
FE Perfect Quality Award: Tanaka Kikinzoku Kogyo K.K.
FE Perfect Quality Award: Tosoh SMD, Inc.
Pinnacle Award: Global Wafers

 

Following three years of extensive research, Hebrew University of Jerusalem (HU) physicist Dr. Uriel Levy and his team have created technology that will enable our computers–and all optic communication devices–to run 100 times faster through terahertz microchips.

Until now, two major challenges stood in the way of creating the terahertz microchip: overheating and scalability.

However, in a paper published this week in Laser and Photonics Review, Dr. Levy, head of HU’s Nano-Opto Group and HU emeritus professor Joseph Shappir have shown proof of concept for an optic technology that integrates the speed of optic (light) communications with the reliability–and manufacturing scalability–of electronics.

Optic communications encompass all technologies that use light and transmit through fiber optic cables, such as the internet, email, text messages, phone calls, the cloud and data centers, among others. Optic communications are super fast but in microchips they become unreliable and difficult to replicate in large quanitites.

Now, by using a Metal-Oxide-Nitride-Oxide-Silicon (MONOS) structure, Levy and his team have come up with a new integrated circuit that uses flash memory technology–the kind used in flash drives and discs-on-key–in microchips. If successful, this technology will enable standard 8-16 gigahertz computers to run 100 times faster and will bring all optic devices closer to the holy grail of communications: the terahertz chip.

As Dr. Uriel Levy shared, “this discovery could help fill the ‘THz gap’ and create new and more powerful wireless devices that could transmit data at significantly higher speeds than currently possible. In the world of hi-tech advances, this is game-changing technology,”

Meir Grajower, the leading HU PhD student on the project, added, “It will now be possible to manufacture any optical device with the precision and cost-effectiveness of flash technology”.

Coming soon to a chip near you…

There are many different situations in which special attention to color choices provide the potential to improve the manufacturing results of multi-patterned masks.

BY DAVID ABERCROMBIE and ALEX PEARSON, Mentor Graphics, Wilsonville, OR

Multi-patterning design rules don’t care about color (mask assignments). As long as all the spacing and alternation constraints are met, any coloring arrangement is legal. In the beginning of multi-patterning, all possible color combinations that passed the design rule checks (DRC) were considered and treated as equal. As the technology moves into more advanced nodes, however, that is no longer the case.

As it turns out, one legal coloring choice can, in fact, be significantly better than another when it comes to manufacturing success and chip performance. Designers working on multi-patterned layouts need to understand the issues and conditions that affect their color choices, so they can determine the optimal coloring scheme for their designs.

Color density

In multi-patterned designs, each color assignment represents a different manufacturing mask. Each mask is processed through a lithography operation, and the pattern is etched onto the wafer. Once all the masks are processed, the goal is to have all the shapes created from all the masks act as if they were all generated from one mask, with very similar process biases and variations.
To ensure that type of consistency, all the masks need to resemble each other in terms of the total area and distribution of shapes. Clumping shapes in one area of one mask, while distributing shapes evenly across another, is going to result in very different process bias behavior and results. Balancing the color density across each mask provides the best manufacturing result.

To explain why, let’s look at a standard cell library design. Because power rails are typically much wider than the routing tracks inside the cells, they constitute a large portion of the polygon area inside the standard cell design block. The number of tracks in the library force the power rails into certain color pairings (FIGURE 1). In the first case, the power rails are forced to opposite colors, while in the second, they are forced to the same color.

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The color ratio distribution charts tell the story of the two designs. When the power rails alternate color, the distribution of the color density ratio is well-centered around the 50% point. However, forcing the power rails to be a single color can dramatically shift the color ratio towards that single color. This distribution is more problematic to manufacture.

But uniform color density isn’t just a chip-wide, global issue—even local differences can have negative impacts, because local areas with excessive or insufficient color density can impact the biases of nearby shapes during processing. In FIGURE 2, both coloring options are legal, but the polygons within each connected component are not equal in area, so the choice of G-B-G-B vs. B-G-B-G affects how much area of each color ultimately exists within this local region. The second coloring choice results in a more uniform area density of each color.

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However, some layouts contain polygon configurations that inherently make it almost impossible to balance colors simply by changing color choices. For example, sometimes you have a very large area polygon in the midst of your layout (FIGURE 3). No matter what color you assign to the large polygon, it will dominate the color density in this region. Changing color selections in the nearby polygons doesn’t help, because they can’t all be assigned to the other color.

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In this case, a new (and perhaps unexpected) solution is needed. Placing evenly distributed polygons of the opposite color in a grid on top of the large area polygon (known as reverse tone overlay fill) adds shapes to the opposite color mask in a region that would otherwise have been empty (FIGURE 4). The smaller polygons on top don’t create openings (they merely “double” block the etch), so they have no real purpose in terms of the final wafer shape. In that regard, they are similar to dummy fill. This technique ensures the two masks have more similar color densities in this region.

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Color regularity

Specific configurations, such as those found in memory applications, may also need strongly controlled, repetitive coloring patterns to help the optical proximity correction (OPC) process generate more consistent results. FIGURE 5 shows three vertical instantiations of a repetitive pattern with horizontal color alternation constraints. On the left, a density-balanced legal coloring assignment is shown. However, by adding a few extra coloring constraints, you can also achieve a regular repetitive coloring pattern, as shown on the right. By introducing this color regularity, you can increase the chances of consistency in the post-OPC results.

Screen Shot 2018-03-28 at 7.41.58 AM

Layout symmetry is another aspect of design that benefits from color regularity. When there is a significant amount of symmetry around a central point, such as a sensitive analog circuit, the most desirable coloring solution maintains x and y axis symmetry around the central point. In FIGURE 6, the constrained coloring solution on the right adds constraints for x and y axis symmetry to generate a mirrored coloring pattern.

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DFM-aware coloring

In design for manufacturing (DFM) optimization, weak lithographic configurations are often captured as process hotspot patterns, which can be used with DFM and/or resolution enhancement technology (RET) processes to minimize the chance of a hotspot forming during manufacturing. As it turns out, the coloring of these patterns in multi-patterned designs can influence whether or not a pattern becomes a hotspot, or actually change the hotspot severity or impact of a particular pattern. If a hotspot pattern is consistently colored in all its instantiations, it may prevent that hotspot from forming, or allow a carefully tuned OPC recipe to be applied.

In FIGURE 7, a different, but still legal, coloring is applied to a rotated/reflected pattern. Because the OPC process will now affect each instance differently, the rotated pattern may become a lithographic hotspot, while the original pattern does not.

Screen Shot 2018-03-28 at 7.42.04 AM

FIGURE 8 shows the same legal coloring applied to both pattern instances, which allows the same OPC to be applied to the layout in both locations, because the coloring is the same, and the polygons that end up on each mask are consistent.

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Sometimes there are cases where information from other layers indicate a color preference for certain shapes. These preferences are typically the result of analysis on another layer, or from information the designer provides, such as for critical or high voltage nets. While these preferences may sometimes conflict with each other for neighboring shapes in the same component, applying these preferences whenever possible helps drive an optimal coloring solution. In FIGURE 9, the red markers indicate a preference for placing those shapes on the green mask. In this case, there is one component that cannot comply, but placing three of the four tagged polygons on the preferred mask maximizes the preferred placements, making this optimal coloring solution.

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Conclusion

In advanced process nodes, achieving the best performance and yield requires moving beyond the minimum requirements of the design rules to optimizing the layout. This optimization is a fundamental principle of all design for manufacturing (DFM) activities, including multi-patterning decomposition. There are many different situations in which special attention to color choices provide the potential to improve the manufacturing results of multi-patterned masks. Designers involved with generating the decomposed mask data before tapeout can expect to see more emphasis on color optimizations as the industry continues to refine and enhance multi-patterning processes.

Single crystal tin selenide (SnSe) is a semiconductor and an ideal thermoelectric material; it can directly convert waste heat to electrical energy or be used for cooling. When a group of researchers from Case Western Reserve University in Cleveland, Ohio, saw the graphene-like layered crystal structure of SnSe, they had one of those magical “aha!” moments.

Electric charges in a nanostructured tin selenide (SnSe) thin film flow from the hot end to the cold end of the material and generate a voltage. Credit: Xuan Gao

Electric charges in a nanostructured tin selenide (SnSe) thin film flow from the hot end to the cold end of the material and generate a voltage. Credit: Xuan Gao

The group reports in the Journal of Applied Physics, from AIP Publishing, that they immediately recognized this material’s potential to be fabricated in nanostructure forms. “Our lab has been working on two-dimensional semiconductors with layered structures similar to graphene,” said Xuan Gao, an associate professor at Case Western.

Nanomaterials with nanometer-scale dimensions — such as thickness and grain size — have favorable thermoelectric properties. This inspired the researchers to grow nanometer-thick nanoflakes and thin films of SnSe to further study its thermoelectric properties.

The group’s work centers on the thermoelectric effect. They study how the temperature difference in a material can cause charge carriers — electrons or holes — to redistribute and generate a voltage across the material, converting thermal energy into electricity.

“Applying a voltage on a thermoelectric material can also lead to a temperature gradient, which means you can use thermoelectric materials for cooling,” said Gao. “Generally, materials with a high figure of merit have high electrical conductivity, a high Seebeck coefficient — generated voltage per Kelvin of temperature difference within a material — and low thermal conductivity,” he said.

A thermoelectric figure of merit, ZT, indicates how efficiently a material converts thermal energy to electrical energy. The group’s work focuses on the power factor, which is proportional to ZT and indicates a material’s ability to convert energy, so they measured the power factor of the materials they made.

To grow SnSe nanostructures, they used a chemical vapor deposition (CVD) process. They thermally evaporated a tin selenide powder source inside an evacuated quartz tube. Tin and selenium atoms react on a silicon or mica growth wafer placed at the low-temperature zone of the quartz tube. This causes SnSe nanoflakes to form on the surface of the wafer. Adding a dopant element like silver to SnSe thin films during material synthesis can further optimize its thermoelectric properties.

At the start, “the nanostructure SnSe thin films we fabricated had a power factor of only ~5 percent of that of single crystal SnSe at room temperature,” said Shuhao Liu, an author on the paper. But, after trying a variety of dopants to improve the material’s power factor, they determined that “silver was the most effective — resulting in a 300 percent power factor improvement compared to undoped samples,” Liu said. “The silver-doped SnSe nanostructured thin film holds promise for a high figure of merit.”

In the future, the researcher hope that SnSe nanostructures and thin films may be useful for miniaturized, environmentally friendly, low-cost thermoelectric and cooling devices.

Thousands of miles of fiber-optic cables crisscross the globe and package everything from financial data to cat videos into light. But when the signal arrives at your local data center, it runs into a silicon bottleneck. Instead of light, computers run on electrons moving through silicon-based chips — which, despite huge advances, are still less efficient than photonics.

To break through this bottleneck, researchers are trying to integrate photonics into silicon devices. They’ve been developing lasers — a crucial component of photonic circuits — that work seamlessly on silicon. In a paper appearing this week in APL Photonics, from AIP Publishing, researchers from the University of California, Santa Barbara write that the future of silicon-based lasers may be in tiny, atomlike structures called quantum dots.

Such lasers could save a lot of energy. Replacing the electronic components that connect devices with photonic components could cut energy use by 20 to 75 percent, Justin Norman, a graduate student at UC Santa Barbara, said. “It’s a substantial cut to global energy consumption just by having a way to integrate lasers and photonic circuits with silicon.”

Silicon, however, does not have the right properties for lasers. Researchers have instead turned to a class of materials from Groups III and V of the periodic table because these materials can be integrated with silicon.

Initially, the researchers struggled to find a functional integration method, but ultimately ended up using quantum dots because they can be grown directly on silicon, Norman said. Quantum dots are semiconductor particles only a few nanometers wide — small enough that they behave like individual atoms. When driven with electrical current, electrons and positively charged holes become confined in the dots and recombine to emit light — a property that can be exploited to make lasers.

The researchers made their III-V quantum-dot lasers using a technique called molecular beam epitaxy. They deposit the III-V material onto the silicon substrate, and its atoms self-assemble into a crystalline structure. But the crystal structure of silicon differs from III-V materials, leading to defects that allow electrons and holes to escape, degrading performance. Fortunately, because quantum dots are packed together at high densities — more than 50 billion dots per square centimeter — they capture electrons and holes before the particles are lost.

These lasers have many other advantages, Norman said. For example, quantum dots are more stable in photonic circuits because they have localized atomlike energy states. They can also run on less power because they don’t need as much electric current. Moreover, they can operate at higher temperatures and be scaled down to smaller sizes.

In just the last year, researchers have made considerable progress thanks to advances in material growth, Norman said. Now, the lasers operate at 35 degrees Celsius without much degradation and the researchers report that the lifetime could be up to 10 million hours.

They are now testing lasers that can operate at 60 to 80 degrees Celsius, the more typical temperature range of a data center or supercomputer. They’re also working on designing epitaxial waveguides and other photonic components, Norman said. “Suddenly,” he said, “we’ve made so much progress that things are looking a little more near term.”