Category Archives: Semiconductors

As the world of advanced manufacturing enters the sub-nanometer scale era, it is clear that ALD, MLD and SAM represent viable options for delivering the required few-atoms-thick layers required with uniformity, conformality, and purity.

BY BARRY ARKLES, JONATHAN GOFF, Gelest Inc., Morrisville PA; ALAIN E. KALOYEROS, SUNY Polytechnic Institute, Albany, NY

Device and system technologies across several industries are on the verge of entering the sub-nanometer scale regime. This regime requires processing techniques that enable exceptional atomic level control of the thickness, uniformity, and morphology of the exceedingly thin (as thin as a few atomic layers) film structures required to form such devices and systems.[1]

In this context, atomic layer deposition (ALD) has emerged as one of the most viable contenders to deliver these requirements. This is evidenced by the flurry of research and devel- opment activities that explore the applicability of ALD to a variety of material systems,[2,3] as well as the limited introduction of ALD TaN in full-scale manufacturing of nanoscale integrated circuitry (IC) structures.[4] Both the success and inherent limitations of ALD associated with repeated dual-atom interactions have stimulated great interest in additional self-limiting deposition processes, particularly Molecular Layer Deposition (MLD) and Self- Assembled Monolayers (SAM). MLD and SAM are being explored both as replacements and extensions of ALD as well as surface modification techniques prior to ALD.[5]

ALD is a thin film growth technique in which a substrate is exposed to alternate pulses of source precursors, with intermediate purge steps typically consisting of an inert gas to evacuate any remaining precursor after reaction with the substrate surface. ALD differs from chemical vapor deposition (CVD) in that the evacuation steps ensure that the different precursors are never present in the reaction zone at the same time. Instead, the precursor doses are applied as successive, non-overlapping gaseous injections. Each does is followed by an inert gas purge that serves to remove both byproducts and unreacted precursor from the reaction zone.

The fundamental premise of ALD is based on self-limiting surface reactions, wherein each individual precursor-substrate interaction is instantaneously terminated once all surface reactive sites have been depleted through exposure to the precursor. For the growth of binary materials, each ALD cycle consists of two precursor and two purge pulses, with the thickness of the resulting binary layer per cycle (typically about a monolayer) being determined by the precursor-surface reaction mode. The low growth rates associated with each ALD cycle enable precise control of ultimate film thickness via the application of repeated ALD cycles. Concurrently, the self-limiting ALD reaction mechanisms allow excellent conformality in ultra-high-aspect-ratio nanoscale structures and geometries.[6]

A depiction of an individual ALD cycle is shown in FIGURE 1. In Fig. 1(a), a first precursor A is introduced in the reaction zone above the substrate surface.

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Precursor A then adsorbs intact or reacts (partially) with the substrate surface to form a first monolayer, as shown in Fig. 1(b), with any excess precursor and potential byproducts being evacuated from the reaction zone through a subsequent purge step. In Fig. 1(d), a second precursor Y is injected into the reaction zone and is made to react with the first monolayer to form a binary atomic layer on the substrate surface, as displayed in Fig. 1(e). Again, all excess precursors and reaction byproducts are flushed out with a second purge step 1(f). The entire process is performed repeatedly to achieve the targeted binary film thickness.

In some applications, a direct or remote plasma is used as an intermediate treatment step between the two precursor-surface interactions. This treatment has been reported to increase the probability of surface adsorption by boosting the number of active surface sites and lowering the reaction activation energy. As a result, such treatment has led to increased growth rates and reduce processing temperatures.[7]

A number of benefits have been cited for the use of ALD, including high purity films, absence of particle contami- nation and pin-holes, precise control of thickness at the atomic level, excellent thickness uniformity and step coverage in complex via and trench topographies, and the ability to grow an extensive array of binary material systems. However, issues with surface roughness and large surface grain morphology have also been reported. Another limitation of ALD is the fact that it is primarily restricted to single or binary material systems. Finally, extremely slow growth rates continue to be a challenge, which could potentially restrict ALD’s applicability to exceptionally ultrathin films and coatings.

These concerns have spurred a renewed interest in other molecular level processing technologies that share the self-limiting surface reaction characteristics of ALD. Chief among them are MLD and SAM. MLD refers principally to ALD-like processes that also involve successive precursor-surface reactions in which the various precursors never cross paths in the reaction zone. [8] However, while ALD is employed to grow inorganic material systems, MLD is mainly used to deposit organic molecular films. It should be noted that this definition of MLD, although the most common, is not yet universally accepted. An alternative characterization refers to MLD as a process for the growth of organic molecular components that may contain inorganic fragments, yet it does not exhibit the self-limiting growth features of ALD or its uniformity of film thickness and step coverage.[2]

A depiction illustrating a typical MLD cycle, according to the most common definition, is shown in FIGURE 2. In Fig. 2(a), a precursor is introduced in the reaction zone above the substrate surface. Precursor C adsorbs to the substrate surface and is confined by physisorption (Fig. 2(b)). The precursor then undergoes a quick chemisorption reaction with a significant number of active surface sites, leading to the self-limiting formation of molecular attachments in specific assemblies or regularly recurring structures, as displayed in Fig. 2(c). These structures form at significantly lower process temperatures compared to traditional deposition techniques.

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To date, MLD has been successfully applied to grow exceptionally thin films for applications as organic, inorganic, and hybrid organic-inorganic dielectrics and polymers for IC applications; [1,9] nanoprobes for in-vitro imaging and interrogation of biological cells; [10] photoluminescent devices; [7] and lithium-ion battery electrodes.[11]

SAM is a deposition technique that involves the spontaneous adherence of organized organic structures on a substrate surface. Such adherence takes place through adsorption from the vapor or liquid phase through relatively weak interactions with the substrate surface. Initially, the structures are adsorbed on the surface by physisorption through, for instance, van der Waals forces or polar interactions. Subsequently, the self-assembled monolayers become slowly confined by a chemisorption process, as depicted in FIGURE 3.

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The ability of SAM to grow layers as thin as a single molecule through chemisorption-driven interactions with the substrate has triggered enthusiasm for its potential use in the formation of “near-zero-thickness” activation or barrier layers. It has also sparked interest in its appli- cability to area-selective or area-specific deposition. Molecules can be directed to exhibit preferential reactions with specific segments of the underlying substrate rather than others to facilitate or obstruct subsequent material growth. This feature makes SAM desirable for incorpo- ration in area-selective ALD (AS-ALD) or CVD (AS-CVD), where the SAM-formed layer would serve as a foundation or blueprint to drive AS-ALD or AS-CVD. [12,13]

To date, SAM has been effectively employed to form organic layers as thin as a single molecule for applications as organic, inorganic, and hybrid organic-inorganic dielec- trics; polymers for IC applications; [13,14] encapsulation and barrier layers for IC metallization; [15] photoluminescent devices; [5] molecular and organic electronics; [16] and liquid crystal displays.[17]

As the world of advanced manufacturing enters the sub-nanometer scale era, it is clear that ALD, MLD and SAM represent viable options for delivering the required few-atoms-thick layers required with uniformity, conformality, and purity. By delivering the constituents of the material systems individually and sequentially into the processing environment, and precisely controlling the resulting chemical reactions with the substrate surface, these techniques enable excellent command of processing parameters and superb management of the target specifications of the resulting films. In order to determine whether one or more ultimately make it into full-scale manufacturing, a great deal of additional R&D is required in the areas of understanding and establishing libraries of fundamental interactions, mechanisms of source chemistries with various substrate surfaces, engineering viable solutions for surface smoothness and rough morphology, and developing protocols to enhance growth rates and overall throughput.

References

1. Belyansky, M.; Conti, R.; Khan, S.; Zhou, X.; Klymko, N.; Yao, Y.; Madan, A.; Tai, L.; Flaitz, P.; Ando, T. Silicon Compat. Mater. Process. Technol. Adv. Integr. Circuits Emerg. Appl. 4 2014, 61 (3), 39–45.
2. George, S. M.; Yoon, B. Mater. Matters 2008, 3 (2), 34–37. 3. George, S. M.; Yoon, B.; Dameron, A. A. Acc. Chem. Res.
2009, 42 (4), 498–508.
4. Graef, E.; Huizing, B. International Technology Roadmap for
Semiconductors 2.0, 2015th ed.; 2015.
5. Kim, D.; Zuidema, J. M.; Kang, J.; Pan, Y.; Wu, L.; Warther, D.; Arkles, B.; Sailor, M. J. J. Am. Chem. Soc. 2016, 138 (46),
15106–15109.
6. George, S. M. Chem. Rev. 2010, 110 (1), 111–131.
7. Provine, J.; Schindler, P.; Kim, Y.; Walch, S. P.; Kim, H. J.; Kim,
K. H.; Prinz, F. B. AIP Adv. 2016, 6 (6).
8. Räupke, A.; Albrecht, F.; Maibach, J.; Behrendt, A.; Polywka,
A.; Heiderhoff, R.; Helzel, J.; Rabe, T.; Johannes, H.-H.; Kowalsky, W.; Mankel, E.; Mayer, T.; Görrn, P.; Riedl, T. 226th Meet. Electrochem. Soc. (2014 ECS SMEQ) 2014, 64 (9), 97–105.
9. Fichtner, J.; Wu, Y.; Hitzenberger, J.; Drewello, T.; Bachmann, J. ECS J. Solid State Sci. Technol. 2017, 6 (9), N171–N175.
10. Culic-Viskota, J.; Dempsey, W. P.; Fraser, S. E.; Pantazis, P. Nat. Protoc. 2012, 7 (9), 1618–1633.
11. Loebl, A. J.; Oldham, C. J.; Devine, C. K.; Gong, B.; Atanasov, S. E.; Parsons, G. N.; Fedkiw, P. S. J. Electrochem. Soc. 2013, 160 (11), A1971–A1978.
12. Sundaram, G. M.; Lecordier, L.; Bhatia, R. ECS Trans. 2013, 58 (10), 27–37.
13. Kaufman-Osborn, T.; Wong, K. T. Self-assembled monolayer blocking with intermittent air-water exposure. US20170256402 A1, 2017.
14. Arkles, B.; Pan, Y.; Kaloyeros, A. ECS Trans. 2014, 64 (9), 243–249.
15. Tan, C. S.; Lim, D. F. In ECS Transactions; 2012; Vol. 50, pp 115–123.
16. Kong, G. D.; Yoon, H. J. J. Electrochem. Soc. 2016, 163 (9), G115–G121.
17. Wu, K. Y.; Chen, W. Y.; Wang, C.-H.; Hwang, J.; Lee, C.-Y.; Liu, Y.-L.; Huang, H. Y.; Wei, H. K.; Kou, C. S. J. Electrochem. Soc. 2008, 155 (9), J244.

SMIC, Shaoxing Government, and Shengyang Group together announced today the founding of the Semiconductor Manufacturing Electronics (Shaoxing) Corporation (planned) with joint capital contributions. The signing of the joint venture agreement marks the start of a project to bring the manufacture of MEMS and power devices to Shaoxing. The Secretary of the Shaoxing Municipal Party Committee, Mr. Ma Weiguang, the Deputy Secretary and Deputy Mayor, Mr. Sheng Yuechun, the Member of the Standing Committee and Secretary General, Mr. Zhong Hongjiang, the Chairman of SMIC, Dr. Zhou Zixue, the Chief Financial Officer of SMIC, Dr. Gao Yonggang, and Senior Vice President of Strategic Development at SMIC, Ms. Ge Hong, attended the signing ceremony.

Application fields such as Artificial Intelligence, mobile communications, the Internet of Things, automotive electronics, and industrial controls are thriving and growing in pace with the growth of our intelligent society. Specialty MEMS technologies are at the core of the intelligentization of our industry and society, while the advanced manufacturing base for MEMS and power device chips is still relatively weak in China’s domestic semiconductor ecosystem. The investment of this signed joint venture amounts to ¥5.88 Billion RMB. The joint venture will focus on the fields of MEMS and power devices with a wafer and module foundry that will continue to grow and develop with sustained R&D investment. A comprehensive foundry for specialty technologies will be achieved to win leadership in China’s domestic market.

The Chairman of SMIC, Dr. Zhou Zixue indicated in his speech, “SMIC has worked on the specialty technologies of MEMS and power devices for almost ten years. This joint venture project with Shaoxing meets our strategic objectives to build an advanced manufacturing industrial cluster in the Yangtze River Delta region. We have confidence that we will create a leading first-class semiconductor corporation focused on specialty technologies.”

The Secretary of the Shaoxing Municipal Party Committee, Mr. Ma Weiguang said, “In the 1980s, Shaoxing used to be one of the most important towns for China’s IC manufacturing industry. After 40 years the smooth landing of this project will accelerate the transformation and upgrading of the phrase ‘Made in Shaoxing’ into ‘Intelligent Manufacturing in Shaoxing’. Meanwhile, seizing the opportunity to cooperate with SMIC will help to build the IC industry for specialty technologies in Shaoxing and make contributions to Intelligent Manufacturing in China.”

Since the global economic recession of 2008-2009, the IC industry has been on a mission to pare down older capacity (i.e., ≤200mm wafers) in order to produce devices more cost-effectively on larger wafers. The spree of merger and acquisition activity and the migration to producing IC devices using sub-20nm process technology has also led suppliers to eliminate inefficient wafer fabs. From 2009-2017, semiconductor manufacturers around the world have closed or repurposed 92 wafer fabs, according to data compiled, updated, and now available in IC Insights’ Global Wafer Capacity 2018-2022 report.

Figure 1 shows that since 2009, 41% of fab closures have been 150mm fabs and 26% have been 200mm wafer fabs. 300mm wafer fabs have accounted for only 10% of total fab closures since 2009. Qimonda was the first company to close a 300mm wafer fab after it went out of business in early 2009.

Figure 1

Figure 1

More recently, ProMOS closed two 300mm memory fabs in 2013 and Renesas sold its 300mm logic fab to Sony in 2014.  Sony repurposed that fab to make image sensors.  In 2017, Samsung closed its 300mm Line 11 memory fab in Yongin, South Korea, also repurposing it to manufacture image sensors. Semiconductor suppliers in Japan have closed a total of 34 wafer fabs since 2009, more than any other country/region.   In the 2009-2017 timeframe, 30 fabs were closed in North America and 17 shuttered in Europe, and only 11 wafer fabs were closed throughout the Asia-Pacific region (Figure 2).

Figure 2

Figure 2

Worldwide fab closures surged in 2009 and 2010 partly as a result of the severe economic recession at the end of the previous decade.  A total of 25 fabs were closed in 2009, followed by 22 being shut down in 2010.  Ten fabs closed in 2012 and 2013.  Two fabs were closed in 2015, the fewest number of closures per year during the 2009-2017 time span.  In 2017, 3 wafer fabs were removed from service. IC Insights has identified three wafer fabs (two 150mm fabs, one 200mm fab) that are targeted for closure this year and next.

Given the flurry of merger and acquisition activity seen in the semiconductor industry recently, the skyrocketing cost of new wafer fabs and manufacturing equipment, and as more IC companies transition to a fab-lite or fabless business model, IC Insights expects more fab closures in the coming years—a prediction that will likely please IC foundry suppliers.

BY RYAN PEARMAN, D2S, Inc., San Jose, CA

There are big changes on the horizon for semiconductor mask manufacturing, including the imminent first production use of multi-beam mask writers, and the preparation of all phases of semiconductor manufacturing for the introduction of extreme ultra-violet (EUV) lithography within the next few years. These changes, along with the increasing use of multiple patterning and inverse- lithography technology (ILT) with 193i lithography, are driving the need for more detailed and more accurate modeling for mask manufacturing.

New solutions bring new mask modeling challenges

Both EUV and multi-beam mask writing provide solutions to many long-standing challenges for the semiconductor industry. However, they both create new challenges for mask modeling as well. Parameters once considered of negligible impact must be added to mask models targeted for use with EUV and/or multi-beam mask writers. In particular, the correct treatment of dose profiles has emerged as a critical component for mask models targeting these new technologies. This is in addition to scattering effects, such as the well-known EUV mid-range scatter, that must be included in mask models to accurately predict the final mask results. Gaussian models, which form the basis for most traditional mask models, will not be sufficient as many of these new parameters are more properly represented with arbitrary point-spread functions (PSFs).

The most obvious – and most desperately needed – benefit of EUV lithography is greater accuracy due to its enhanced resolution. However, this benefit comes along with a mask-making challenge: wafer-printing defects due to mask errors will appear more readily because of this enhanced resolution. Therefore, the introduction of EUV will require the mean-to-target (MTT) variability on photomasks to become smaller. From a mask manufacturability perspective, all sources of printing errors, systematic and random, must be improved. This means that mask models must also be more accurate, not only in predicting measurements, but also in predicting variability.

A well-known challenge for EUV mask modeling is the EUV mid-range scatter effect. The more complex topology of EUV masks leads to broader scattering effects. In addition to “classical” forward- and back-scatter effects, which dominate 193i lithography, there is a mid-range (1μm) scatter that now requires modeling. This phenomenon is non-Gaussian in nature, so cannot be simulated accurately with simple Gaussian (“1G”) models. In combination with better treatment of resist effects, a PSF-based model is a much better represen- tation of the critical lithography process.

The eagerly anticipated introduction of EUV will demand a lower-sensitivity resist to be used for EUV masks due to the smaller size of EUV features. This is one of the reasons why multi-beam mask writers have emerged as the replacement for variable shaped beam (VSB) tools for the next generation of mask writers. Slower resists require higher currents, and VSB tools today are limited thermally in ways the massively parallel multi-beam tools are not. In addition to thermal effects, VSB mask writers are runtime-limited by shot count; we are already approaching the practical limit for many advanced masks. Shot count is only expected to grow in the future as pitches shrink and complex small features become prevalent in EUV masks – and even in 193i masks due to increased use of ILT to improve process windows for 193i lithography.

In contrast to VSB mask writers, which use shaped apertures to project the shapes (usually rectangles) created by optical-proximity correction (OPC) onto the mask, multi-beam mask writers rasterize the desired mask shapes into a field of pixels, each of which are written by one of hundreds of thousands of individual beamlets (FIGURE 1). This enables multi-beam mask writers to write masks in constant time, no matter how complicated the mask shapes. Each of these beamlets can be turned on and off independently to create the desired eBeam input, which enables the fine resolution of smaller shapes. However, it also means that the dose profiles for the multi-beam writers are far more complex, leading to the need for more advanced, separable dose and shape modeling.

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Since the beamlets of a multi-beam tool are smaller than the primary length-scale of the dose blur, a key second advantage of multi-beam writers emerges: the patterns written are intrinsically curvilinear. In contrast, VSB mask writers can only print features with limited shapes – principally rectangular and 45-degree diagonals, although some tools enable circular patterns. The critical process-window enhancements for ILT also rely on curvilinear mask shapes, so a synergy appears: better treatment of curved edges at the mask writing step will lead to better wafer yield.

Dose and shape: New requirements for multi- beam and EUV mask models

Multi-beam mask writers, EUV masks, and even the proliferation of ILT will require mask models to change substantially. Until very recently, curvi-linear mask features have been ignored when characterizing masks, and models, when used, have assumed simplicity. Primary electron blur (“forward scattering”), including chemically amplified resist (CAR) effects, historically have been assumed to be a set of Gaussians, with length scales between 15nm and 300nm. All other effects of the mask making processes – long-range electron scattering (“back-scatter” and “fogging”), electron charging, devel- opment, and plasma-etching effects – have either been assumed to be constant regardless of mask shape or the dose applied, or have been accounted for approxi- mately by inline corrections in the exposure tool.

To meet the challenges posed by both EUV and multi- beam writing – especially since they are likely to be employed together – mask models will need to treat dose and shape separately, and to explicitly account for the various scattering, fogging, etch, and charging effects (FIGURE 2).

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When masks were written entirely at nominal dose, dose-based effects could be handled together with shape-based effects as a single term. Several years ago, overlapping shots were introduced by D2S for VSB tools to both improve margins and reduce shot-count for complex mask shapes. At this time, it became clear that dose modulation (including overlapping shots) required specific modeling. Some effects (like etch) varied only with respect to the resist contour shapes, while other print bias effects were based on differences in exposure slope near the contour edge. For all the complexity of VSB overlapping shots, all identical patterns were guaranteed to print in the same way. Today, with multi-beam writers, there are significant translational differences in features due to dose-profile changes as they align differently with the multi-beam pixel grid.

We discussed earlier that multi-beam tools print curvi-linear shapes. We should point out that even Manhattan designs become corner-rounded on the actual masks at line ends, corners, and jogs. Why? Physics is almost never Manhattan, and treating it as such will be inaccurate, as in the case of etching effects computed in the presence of Manhattan jogs. We need to embrace the fact that all printed mask shapes will be curvilinear and ensure that any shape-based simulation is able to predict effects at all angles, not just 0 and 90.

Increasing mask requirements drive the need for mask model accuracy

As we continue to move forward to more advanced processes with ever-smaller feature sizes, the requirement for better accuracy increases. There is quite literally less room for any defects. This increased emphasis on accuracy and precision is what drives the adoption of new technologies such as EUV and multi-beam mask writing; it drives the increased need for better model performance as well.

We have already discussed several model parameters that will need to be re-evaluated and handled differently in order to achieve greater accuracy. Accuracy also requires a more rigorous approach to the calibration and validation of models with test chips that isolate specific physics effects with specific test structures. For example, masks that include complex shapes require 2D validation. Today’s VSB mask writers are Manhattan (1D) writing instruments, so models built using these tools are by definition 1D-centric. Inaccuracies in 1D models are exacerbated when tested against a 2D validation. Physics-based models are far more likely to extrapolate to 2D shapes, and are better for ILT.

As features shrink, the accuracy of individual shapes on the mask is impacted increasingly by their proximity to other shapes. The context for each shape on the mask becomes as important as the shape itself. The solution is to model each shape within the context of its surroundings. This is driving the need for simulation-based modeling and mask-correction methodologies.

GPU acceleration: Making simulation-based mask modeling practical

Historically, simulation-based processing of mask models resulted in unacceptably long simulation runtimes. The most common approach until recently has been to use model-based or rules-based methodologies that, while providing less accuracy, result in faster runtimes. The advent of GPU-accelerated mask simulation has changed this picture. GPU acceleration is particularly suited to “single instruction, multiple data” (SIMD) computing, which makes it a very good fit for simulation of physical phenomena, and enables full- reticle mask simulation within reasonable runtimes.

An additional advantage of GPU acceleration is the ability to employ PSFs without runtime impact (FIGURE 3). As we’ve already discussed, PSFs are a natural choice for the mask-exposure model, including EUV mask mid-range scattering effects, forward-scattering details, and modeling back-scattering by construction. Using PSFs, any dose effect of any type can be exactly modeled during simulation-based processing.

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GPU acceleration opens the door for simulation-based correction of a multitude of complex mask effects based on physics-based models, affording practical simulation run times for these more complex models.

PLDC: New mask models at work in multi-beam mask writers

As with any big changes to the semiconductor manufacturing process, the industry has been preparing for EUV and multi-beam mask writing for several years. These preparations have required various members of the supply chain to work together to deploy effective solutions. One example of this collaboration in the mask-modeling realm is the introduction by NuFlare Technology of pixel-level dose correction (PLDC) in its MBM-1000 multi-beam mask writer. At the 2017 SPIE Photomask Japan conference, NuFlare and D2S jointly presented a paper [2] detailing the mask modeling – and GPU acceleration – used in this new inline mask correction.

PLDC manipulates the dose of pixels to perform short- range (effects in the 10nm scale to 3-5μm scale) linearity correction while improving the overall printability of the mask. In addition to the traditional four-Gaussian (4G) PEC model, PLDC combines for the first time an inline 10nm-100nm short-range linearity correction with a 1μm scale mid-range linearity correction (FIGURE 4). This mid-range correction is particularly useful for EUV mid-range scatter correction.

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The dose-based effects portion of the D2S mask model, TrueModel, are expressed as a PSF for an interaction range up to 3-5μm, and with a 4G PEC model for interaction range up to 40-50μm. Being able to express any arbitrary PSF as the correction model allows smoothing of “shoulders” that are often present on multiple Gaussian models, and allows proper modeling of effects that are not fundamentally Gaussian in nature (such as the EUV mid-range scatter). This ability to model physical effects and correct for them inline with mask writing results in more accurate masks, including for smaller EUV shapes and for curvilinear ILT mask shapes.

PLDC is simulation-based, so it has the ability to be very accurate regardless of targeted shape, regardless of mask type (e.g., positive, negative EUV, ArF, NIL master) with the right set of mask modeling parameters.

GPU acceleration enables fast computing of PSF convo- lutions for all dose-based effects up to 3-5μm range, performed inline in the MBM-1000, which helps to maintain turnaround time in the mask shop.

Conclusions

Mask models need some significant adaptations to meet the coming challenges. The new EUV/multi-beam mask writer era will require mask models to be more detailed and more accurate. More complex dose profiles and more complex electron scattering require PSFs be added to the industry-standard Gaussian models. More rigorous mask models with specific dose and specific shape effects are now needed. Simulation-based mask processing, made practical by GPU acceleration, is necessary to take context-based mask effects into account.

The good news is that the mask industry has been preparing for these changes for several years and stands ready with solutions to the challenges posed by these new technologies. Big changes are coming to the mask world, and mask models will be ready.

References

1. Pearman, Ryan, et al, “EUV modeling in the multi-beam mask writer era,” SPIE Photomask Japan, 2017.

2. “GPU-accelerated inline linearity correction: pixel-level dose correction (PLDC) for the MBM-1000,” Zable, Matsumoto, et al, SPIE Photomask Japan, 2017.

BY SYAHIRAH MD ZULKIFLI, BERNICE ZEE AND WEN QIU, Advanced Micro Devices, Singapore; ALLEN GU, ZEISS, Pleasanton, CA

3D integration and packaging has challenged failure analysis (FA) techniques and workflows due to the high complexity of multichip architectures, the large variety of materials, and small form factors in highly miniaturized devices [1]. The drive toward die stacking with High Bandwidth Memory (HBM) allows the ability to move higher bandwidth closer to the CPU and offers an oppor- tunity to significantly expand memory capacity and maximize local DRAM storage for high throughput in the data center. However, the integration of HBM results in more complex electrical communications, due to the emerging use of a physical layer (PHY) design to connect the chip and subsystems. FIGURE 1 shows the schematic of a 2.5D stacked die package designed so that some HBM μbumps are electrically connected to the main CPU through a PHY connection. In general, the HBM and CPU signal length needs to be minimized to reduce drive strength requirements and power consumption at the PHY.

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This requirement poses new challenges in FA fault isolation. A traditional FA workflow using electrical fault isolation (EFI) techniques to isolate the defect becomes less effective for chip-to-chip interconnects because there are no BGA balls for electrically probing the μbumps at the PHY. As a result, new defect localization techniques and FA flows must be investigated.

XRM theory

X-ray imaging is widely employed for non-destructive FA inspection because it can explore interior structures of chips and packages, such as solder balls, silver paste and lead frames. Thus, many morphological failures, such as solder-ball crack/burn-out and bumping failure inside IC packages, can be imaged and analyzed through X-ray tools. In 2D X-ray inspection, an X-ray irradiates samples and a 2D detector utilizes the projection shadow to construct 2D images. This technique, however, is not adequate for revealing true 3D structures since it projects 3D structures onto a 2D plane. As a result, important information, such as internal faulty regions of electronic packages, may remain hidden. This disadvantage can be overcome by using 3D X-ray microscopic technology, derived from the original computed tomography (CT) technique. In a 3D imaging system, a series of 2D X-ray images are captured at different angles while a sample rotates.

These 2D images are used to reconstruct 3D X-ray tomographic slices using mathematic models and algorithms. The spatial resolution of the imaging technique can be improved through the integration of an optical microscopy system. This improved technology is called 3D X-ray microscopy (XRM) [2]. FIGURE 2 shows an example 3D XRM image for a stacked die. The image clearly shows the internal structures – including the TSV, C4 bumps and μbump of the electronic components – without physically damaging or altering the sample. The high resolution and quality shown here are essential to inspect small structural defects inside electronic devices. With its non-destructive nature, 3D XRM has been useful for non-destructive FA for IC packaging devices.

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Failure analysis approach

The purpose of an FA workflow is to have a sequence of analytical techniques that can help to effectively and quickly isolate the failure and determine the root cause. Typical FA workflows for flip-chip devices consist of non-destructive techniques such as C-Mode scanning acoustic microscopy (C-SAM) and time domain reflectometry (TDR) to isolate the failure, followed by destructive physical failure analysis (PFA). However, there are limitations to each of these techniques when posed with the failure analysis of a more complex stacked die package.

C-SAM allows the inspection of abnormal bumps, delamination and any mechanical failure. A focused soundwave is directed from a transducer to a small point on a target object and is reflected when it encounters a defect, inhomogeneity or a boundary inside the material. The transducer transforms the reflected sound pulses into electromagnetic pulses, which are displayed as pixels with defined grey values thereby creating an image [3]. However, stacked die composed of a combination of multiple thin layers may complicate C-SAM analysis. This is because the thin layers have smaller spacing between the adjacent interface, and shorter delay times for ultrasound traveling from one interface to another. Therefore, failures between the die and die attach may not be easily detected, and false readings may even be expected.

TDR is an electrical fault isolation tool that enables failure localization through electrical signal data. The TDR signal carries the impedance load information of electrical circuitry; hence, the reflected signals show the discontinuity location that has caused the mismatch of impedance. In-depth theory on TDR is further discussed in Chin et al [4]. However, TDR can only estimate where the failure lies, whether it is in the substrate, die or interposer region. To pin point the exact location within the area of failure is difficult, due to limitations in separating the various small structures through the TDR signal. Additionally, some of the pulse power is reflected for every impedance change, posing challenges regarding unique defect isolation and signal complexity – especially for stacked die [5]. In cases where the failure pins reside in the HBM μbump region, no BGA ball out is available to probe and send an electrical pulse through.

Physical Failure Analysis (PFA) is a destructive method to find and image the failure once non-destructive fault isolation is complete. PFA can be done both mechanically and by focused ion beam (FIB). For stacked dies, FIB is predominantly used to image smaller interconnect structures such as TSVs and μbumps. However, the drawback is that the success of documenting the failure through PFA is largely dependent on how well the non-destructive FA techniques can isolate the failure region. Without good clear fault isolation direction, the failure region might be destroyed or missed during the PFA process, and thus no root cause can be derived.

The integration of XRM into the FA flow can help to overcome the limitations of the various analysis techniques to isolate the failure. It is a great advantage to image small structures and failures with the high spatial resolution and contrast provided by XRM and without destroying the sample. For failures in stacked die, XRM can be integrated into the FA flow for further fault isolation with high accuracy. The visualization of defects and failed material prior to destructive analysis increases FA success rates. However, the trade-off for imaging small defects at high resolution is time. For stacked die failures, C-SAM and TDR can first be performed to isolate the region of failure. With a known smaller region of interest to focus on, the time taken for XRM to visualize the area at high resolution is significantly reduced.

In cases where failures are identified in the HBM μbump, XRM is an effective technique to isolate the failure through 3D defect visualization. With the failure region isolated, XRM can then act as a guide to perform further PFA. Following are three case studies where XRM was used to image HBM packages with stacked dies.

Case studies

In the first case study, we explore the application of XRM as the primary means of defect visualization where other non-destructive testing and FA techniques are not possible. An open failure was reported for non-underfilled stacked die packages during a chip package interaction (CPI) study. The suspected open location was within the μbump joints at the HBM stack/ interposer interface. The initial approach exposed the bottom-most die of the HBM stack, followed by FIB cross-sectioning at the specified location. Performing the destructive approach to visualize the integrity of μbump joints in non-underfilled stack die packages was virtually impossible due to the fragility of silicon. The absence of underfill (UF) means that the HBM does not properly adhere to the interposer and is susceptible to peel off. In addition, there was no medium to release shear stresses experienced by the μbump joints upon bending stresses, which could not be absorbed by the package. As seen in FIGURE 3, parallel lapping of the HBM stack without UF caused die crack and peeling.

Screen Shot 2018-03-01 at 11.46.50 AM

Consequently, to avoid aggravating the damage on the sample, 3D XRM was performed to inspect and visualize the suspected location using a 0.7μm/voxel and 4X objective without any sample preparation. FIGURE 4 shows an example virtual slice where the micro-cracks throughout the row of μbump joints are visualized. The micro-cracks are measured a few microns wide. It is worth noting that the micro-cracks were visible with a short scan time of 1.5 hrs.

Screen Shot 2018-03-01 at 11.47.00 AM

With the critical defect information in 3D, PFA was performed on a sample that was underfilled to facilitate ease of sample preparation. SEM images in FIGURE 5 validated the existence of μbump micro-cracks observed by 3D XRM inspection.

In the second case study, the 3D XRM technique was applied to a stacked die package with a failure at a specific HBM/XPU physical interface (PHY) μbump connection. This μbump connection provides specific communication between the HBM stack and XPU die, and there is no package BGA ball out to enable electrical probing. Accordingly, it was not possible to verify if the failure type was an open or short. In addition, there was no means to determine if the failure was at the HBM or XPU die. Since defects from previous lots were open failures at the PHY μbump of the HBM, 3D XRM was performed at the suspected HBM open region using a 0.85μm/voxel and 4X objective.

As no defect was observed, XRM was then applied to the corresponding XPU PHY μbump. Contrary to the anticipated μbump open, a short was observed between two μbumps as shown in FIGURES 6a and 6b.

Screen Shot 2018-03-01 at 11.47.22 AM Screen Shot 2018-03-01 at 11.47.28 AM

 

The μbump short resulted from a solder extrusion bridging two adjacent μbumps. If 3D XRM had not been performed, a blind physical cross-section likely would have been performed on the initially suspected open region. As a result, the actual failure region may have been missed and/or destroyed.

In the final case study, an open failure was reported at a signal pin of a stack die package. As per the traditional FA flow, C-SAM and TDR techniques were applied to isolate the fault. C-SAM results showed an anomaly, and TDR suggested an open in the substrate as demonstrated in FIGURE 7a and 7b respectively.

Screen Shot 2018-03-01 at 11.47.10 AM Screen Shot 2018-03-01 at 11.47.16 AM

To verify the observations made by C-SAM and TDR non-destructive techniques, 3D XRM was performed using a 0.80μm/voxel and 4X objective at the region of

FIGURE 8 revealed a crack between the failure C4 bump and associated TSV. A physical cross-section was performed and the passivation cracks between the TSV and interposer backside redistribution layer (RDL) was observed as shown in FIGURE 9.

Screen Shot 2018-03-01 at 11.47.35 AM

In this case, 3D XRM provided 3D information for the FA engineer to focus on. Without the visual knowledge on the defect’s nature and location, the defect would have been missed during PFA.

Summary and conclusions

3D integration and packaging have brought about new challenges for effective defect localization, especially when traditional electrical fault isolation is not possible. 3D XRM enables 3D tomographic imaging of internal structures in chips, interconnects and packages, providing 3D structural information of failure areas without the need to destroy the sample. 3D XRM is a vital and powerful tool that helps failure analysis engineers to overcome FA challenges for novel 3D stacked-die packages.

Acknowledgement

This article is based on a paper that was presented at the 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2017).

References

  1. F. Altmann and M. Petzold, “Innovative Failure Analysis Techniques for 3-D Packaging Developments,” IEEE Design & Test, Vol. 33, No. 3, pp. 46-55, June 2016.
  2. C. Y. Liu, P. S. Kuo, C. H. Chu, A. Gu and J. Yoon, “High resolution 3D X-ray microscopy for streamlined failure analysis workflow,” 2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, 2016, pp. 216-219.
  3. M. Yazdan Mehr et al., “An overview of scanning acoustic microscope, a reliable method for non-destructive failure analysis of microelectronic components,” 2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro- electronics and Microsystems, Budapest, 2015, pp.1-4.
  4. J. M. Chin et al., “Fault isolation in semiconductor product, process, physical and package failure analysis: Importance and overview,” Microelectronics Reliability, Vol. 51, Issue 9, pp. 1440-8, Nov. 2011.
  5. W. Yuan et al., “Packaging Failure Isolation with Time-Domain Reflectometry (TDR) for Advanced BGA Packages,” 2007 8th International Conference on Electronic Packaging Technology, Shanghai, 2007, pp. 1-5.

A new progress in the scaling of semiconductor quantum dot based qubit has been achieved at Key Laboratory of Quantum Information and Synergetic Innovation Center of Quantum Information & Quantum Physics of USTC. Professor GUO Guoping with his co-workers, XIAO Ming, LI Haiou and CAO Gang, designed and fabricated a quantum processor with six quantum dots, and experimentally demonstrated quantum control of the Toffoli gate. This is the first time for the realization of the Toffoli gate in the semiconductor quantum dot system, which motivates further research on larger scale semiconductor quantum processor. The result was published as ‘Controlled Quantum Operations of a Semiconductor Three-Qubit System ‘ (Physical Review Applied 9, 024015 (2018)).

This is the Toffoli Gate in a three-qubit system. Credit: University of Science and Technology of China

This is the Toffoli Gate in a three-qubit system. Credit: University of Science and Technology of China

Developing the scalable semiconductor quantum chip that is compatible with modern semiconductor-techniques is an important research area. In this area, the fabrication, manipulation and scaling of semiconductor quantum dot based qubits are the most important core technologies. Professor GUO Guoping’s group aims to master these technologies and has been devoted to this area for a long time. Before the demonstration of the three-qubit gate, they have realized ultrafast universal control of the charge qubit based on semiconductor quantum dots in 2013(Nature Communications. 4:1401 (2013)), and achieved the controlled rotation of two charge qubits in 2015(Nature Communications. 6:7681 (2015)).

The Toffoli gate is a three-qubit operation that changed the state of a target qubit conditioned on the state of two control qubits. It can be used for universal reversible classical computation and also forms a universal set of qubit gates in quantum computation together with a Hadamard gate. Furthermore, it is a key element in quantum error correction schemes. Implementation of the Toffoli gate with only single- and two-qubit operations requires six controlled-NOT gates and ten single-qubit operations.

As a result, a single-step Toffoli gate can reduce the number of quantum operations dramatically, which can break the limit of coherence time and improve the efficiency of quantum computing. Researchers from Guo’s group found the T-shaped six quantum dot architecture with openings between control qubits and the target qubit can strengthen the coupling between qubits with different function and minimize it between qubits with the same function, which satisfies the requirements of the Toffoli gate well. Using this architecture with optimized high frequency pulses, researchers demonstrated the Toffoli gate in semiconductor quantum dot system in the world for the first time, which paves the way and lays a solid foundation for the scalable semiconductor quantum processor.

The reviewer spoke highly of this work, and thought this is an important progress in the field of semiconductor quantum dot based quantum computing.”The work is detailed and clearly demonstrates a high level of experimental technique and would be of high interest to people working in the field of electrostatically defined quantum dots for quantum computation”.

 

Samsung Electronics today announced that it broke ground on a new EUV (extreme ultraviolet) line in Hwaseong, Korea.

With this new EUV line, Samsung will be able to strengthen its leadership in single nanometer process technology by responding to market demand from various applications, including mobile, server, network, and HPC (high performance computing), for which high performance and power efficiency are critical.

The new facility is expected to be completed within the second half of 2019 and start production ramp-up in 2020. The initial investment in the new EUV line is projected to reach USD 6 billion by 2020 and additional investment will be determined depending on market circumstances.

“With the addition of the new EUV line, Hwaseong will become the center of the company’s semiconductor cluster spanning Giheung, Hwaseong and Pyeongtaek in Korea,” said Kinam Kim, President & CEO of Device Solutions at Samsung Electronics. “The line will play a pivotal role as Samsung seeks to maintain a competitive edge as an industry leader in the coming age of the Fourth Industrial Revolution.”

Samsung has decided to utilize cutting-edge EUV technology starting with its 7-nanometer (nm) LPP (Low Power Plus) process. This new line will be set up with EUV lithography equipment to overcome nano-level technology limitations. Samsung has continued to invest in EUV R&D to support its global customers for developing next-generation chips based on this leading-edge technology.

Samsung Electronics Hwaseong Campus EUV line bird’s eye view

Samsung Electronics Hwaseong Campus EUV line bird’s eye view

The research and innovation hub in nanoelectronics and digital technologies, imec, and Cadence Design Systems, Inc. today announced that its extensive, long-standing collaboration has resulted in the industry’s first 3nm test chip tapeout. The tapeout project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-oriented design rules and the Cadence Innovus Implementation System and Genus Synthesis Solution. Imec utilized a common industry 64-bit CPU for the test chip with a custom 3nm standard cell library and a TRIM metal flow, where the routing pitch was reduced to 21nm. Together, Cadence and imec have enabled the 3nm implementation flow to be fully validated in preparation for next-generation design innovation.

The Cadence Innovus Implementation System is a massively parallel physical implementation system that enables engineers to deliver high-quality designs with optimal power, performance and area (PPA) targets while accelerating time to market. The Cadence Genus Synthesis Solution is a next-generation, high-capacity RTL synthesis and physical synthesis engine that addresses the latest FinFET process node requirements, improving RTL designer productivity by up to 10X. For more information on the Innovus Implementation System, please visit www.cadence.com/go/innovus3nm, and to learn about the Genus Synthesis Solution, visit www.cadence.com/go/genus3nm.

For the project, EUV and 193i lithography rules were tested to provide the required resolution, while providing PPA comparison under two different patterning assumptions. For more information on EUV technology and 193i technology, visit https://www.imec-int.com/en/articles/imec-presents-patterning-solutions-for-n5-equivalent-metal-layers.

Post place and route layout of 21 nm pitch metal layers

Post place and route layout of 21 nm pitch metal layers

“As process dimensions reduce to the 3nm node, interconnect variation becomes much more significant,” said An Steegen, executive vice president for semiconductor technology and systems at imec. “Our work on the test chip has enabled interconnect variation to be measured and improved and the 3nm manufacturing process to be validated. Also, the Cadence digital solutions offered everything needed for this 3nm implementation. Due to Cadence’s well-integrated flow, the solutions were easy to use, which helped our engineering team stay productive when developing the 3nm rule set.”

“Imec’s state-of-the-art infrastructure enables pre-production innovations ahead of industry demands, making them a critical partner for us in the EDA industry,” said Dr. Chin-Chi Teng, corporate vice president and general manager in the Digital & Signoff Group at Cadence. “Expanding upon the work we did with imec in 2015 on the industry’s first 5nm tapeout, we are achieving new milestones together with this new 3nm tapeout, which can transform the future of mobile designs at advanced nodes.”

GLOBALFOUNDRIES and eVaderis today announced that they are co-developing an ultra-low power microcontroller (MCU) reference design using GF’s embedded magnetoresistive non-volatile memory (eMRAM) technology on the 22nm FD-SOI (22FDX®) platform. By bringing together the superior reliability and versatility of GF’s 22FDX eMRAM and eVaderis’ ultra-low power IP, the companies will deliver a technology solution that supports a broad set of applications such as battery-powered IoT products, consumer and industrial microcontrollers, and automotive controllers.

eVaderis designed their MCU to leverage the efficient power management capabilities of the 22FDX platform, achieving more than 10 times the battery life and a significantly reduced die size compared to previous generation MCUs. The technology, developed through GF’s FDXcelerator Partner Program, will help designers push performance density and flexibility to new levels to achieve a more compact, cost-effective single-chip solution for power-sensitive applications.

“The innovative architecture of eVaderis’ ultra-low power MCU IP, designed around GF’s 22FDX eMRAM technology, is well suited for normally-off IoT applications,” said Jean-Pascal Bost, President and CEO of eVaderis. “Utilizing GF’s eMRAM as a working memory allows sections of the eVaderis MCU to power cycle frequently, without incurring the typical MCU performance penalty. eVaderis looks forward to making this silicon-proven IP available to our customers by the end of this year.”

“Wearable and IoT devices require long-lasting battery life, increased processing capability, and the integration of advanced sensors,” said Dave Eggleston, VP of Embedded Memory at GF. “As an FDXcelerator partner, eVaderis is developing an optimized MCU architecture in GF’s 22FDX with eMRAM that helps customers meet demanding requirements.”

The jointly developed reference design with GF’s 22FDX with eMRAM will be available in Q4 2018. Process design kits for 22FDX with eMRAM and RF solutions are available now. Customer prototyping of 22FDX eMRAM on multi-project wafers (MPWs) is underway, with risk production planned for 2018. Off-the-shelf eMRAM macros are available now, featuring easy design-in with both eFlash and SRAM interface options.

Customers that are interested in learning more about GF’s 22FDX with eMRAM solution, co-developed in partnership with Everspin Technologies, contact your sales representative or visit globalfoundries.com.

Brewer Science, Inc., today from SPIE Advanced Lithography 2018 introduced its OptiLign commercial-quality directed self-assembly (DSA) material set developed in collaboration with Arkema. The OptiLign system currently includes three materials required for self-assembly: block copolymers, neutral layers and guiding layers. Developed together for optimal performance, these DSA materials are manufactured on Brewer Science’s commercial manufacturing equipment and provide a cost-effective path to advanced-node wafer patterning processes for feature sizes down to 12nm.

Although Moore’s law is slowing, many foundries and integrated device manufacturers are continuing efforts to scale to finer nodes. As feature sizes shrink more aggressively with each node, the limits of manufacturing equipment are being stretched, and it has become cost-prohibitive to create them using existing patterning processes like self-aligned double patterning and self-aligned quadruple patterning. While the industry is close to the commercialization of extreme ultraviolet (EUV) lithography, the tool cost will limit its use. DSA offers an alternative to existing processes and can be performed on existing, installed fab tool sets. Additionally, DSA will serve as a complement to EUV when it becomes fully available.

“Taking OptiLign materials from pilot line to commercial-scale production represents the next significant milestone in making DSA a viable option for semiconductor manufacturing,” said

Dr. Srikanth (Sri) Kommu, executive director, Semiconductor Business, Brewer Science Inc. “Historically, the industry has relied on equipment enhancements to reach the next technology node. Now, materials solutions are stepping in to provide that edge and extend tool capabilities. The OptiLign product family is an example of this paradigm shift.”

Brewer Science’s OptiLign family of DSA products provides all the materials needed for self-assembly. Block copolymers define the pattern. Neutral layers allow the pattern to be formed on each layer. Lastly, guiding layers tell the material which way and how to orient. All the materials are designed to work together for optimal performance, and are dependent on material and surface energy. Additionally, through its partnership with Arkema, Brewer Science has tapped into a way to deliver DSA materials that allows for consistent feature sizes via a unique polymer production process. This process allows for the large scale needed to support an entire technology node, as well as a unique polymer quality and reproducibility, all of which sets OptiLign materials apart from the competition.

“Feature size is built into the molecular structure of the DSA materials and can vary from batch to batch, so securing a sub-nanometric reproducibility can be challenging,” explained Dr. Ian Cayrefourcq, Director of Emerging Technologies, Arkema. “Arkema’s special process for formulating large batches of polymers of the same size allows Brewer Science to supply a fab with consistent feature sizes for the technology node’s life span.”

To learn more about OptiLign materials, visit Brewer Science’s booth #110 at SPIE Advanced Lithography 2018, February 25 – March 1, 2018 in San Jose, California.