Category Archives: Semiconductors

The top five semiconductor metrology/inspection equipment vendors grew 17.7% in 2017 according to the report “Metrology, Inspection, and Process Control in VLSI Manufacturing”, recently published by The Information Network, (www.theinformationnet.com) a New Tripoli, PA-based market research company.

The top three metrology/inspection suppliers were KLA-Tencor, Applied Materials Hitachi High Tech, Nanometrics, and Rudolph Technologies. These five companiesincreased their collective share of the overall global market to 87.0% in 2017, up from 82.4% in 2016.

metrology market

The report covers 27 different sectors and subsectors. With its large market share, KLA-Tencor led most of the sectors and subsectors. Applied Materials led the Defect Review Sector, Hitachi High Tech led the CD Inspection sector, Nanometrics held a large share of the Thin Film Metrology Sector, and Rudolph Technology led the Back-End Inspection market.

China and memory (DRAM and 3D NAND) are currently driving demand for the global wafer fab equipment market.

Orders for KLA-Tencor equipment from native Chinese customers nearly tripled in 2017 and this strong momentum is expected to continue into 2018.

China continues to be a strong focus for Rudolph Technologies. Revenue from China has more than doubled in the last two years. Rudolph’s revenue from advanced memory applications in both three DRAM and 3D NAND grew by 80% year-over-year as customers in Korea increased capacity to meet growing global demand for advanced memory used in cloud computing and mobile applications.

ClassOne Equipment, Atlanta-based provider of refurbished name-brand semiconductor processing equipment, has announced the sale of multiple systems to a major global components manufacturer as part of a significant upgrade to their UK fab. Semitool Batch Spray Solvent Tools and Tepla barrel etch processing equipment – all refurbished by ClassOne – will be installed at the customer facility in England.

“They selected ClassOne for two important reasons,” said ClassOne CEO, Byron Exarcos. “First, our refurbished tools are providing “better-than-new” performance because the equipment is completely refurbished from the frame up, replacing all older-technology elements with current state-of-the-art parts – such as the advanced Windows 7 control systems. And secondly, ClassOne is able to provide this customer with a very strong local service and support infrastructure in the UK, which is essential to their operation.”

“This is a milestone fab upgrade, and we’re proud to be playing an important role in it,” said Exarcos. “Because we’ve built a strong relationship with this particular customer for nearly a decade. Now we’re able to support their UK facility with a local team of senior product, process and field service engineers – and with the fast response times they’re looking for.”

Exarcos noted that ClassOne’s UK support group has over 100 years of combined experience specifically on Semitool equipment and single-wafer systems. He cited this as an example of ClassOne’s ongoing initiative to provide “an unbeatable level of quality products and support” across Europe for single-wafer electroplating, batch spray tools, and other process equipment.

In addition to the refurbished systems sold by ClassOne Equipment, ClassOne also sells its own brand of newprocessing systems through a sister company, ClassOne Technology. These include new Solstice electrochemical plating systems and Trident spray solvent tools (SSTs) as well as new spin rinse dryers (SRDs). The stated goal of both ClassOne companies is to provide advanced processing solutions for a broad range of budget-conscious users, many of whom are in emerging technologies.

Researchers at North Carolina State University have developed a new technique that allows them to print circuits on flexible, stretchable substrates using silver nanowires. The advance makes it possible to integrate the material into a wide array of electronic devices.

Silver nanowires have drawn significant interest in recent years for use in many applications, ranging from prosthetic devices to wearable health sensors, due to their flexibility, stretchability and conductive properties. While proof-of-concept experiments have been promising, there have been significant challenges to printing highly integrated circuits using silver nanowires.

Silver nanoparticles can be used to print circuits, but the nanoparticles produce circuits that are more brittle and less conductive than silver nanowires. But conventional techniques for printing circuits don’t work well with silver nanowires; the nanowires often clog the printing nozzles.

“Our approach uses electrohydrodynamic printing, which relies on electrostatic force to eject the ink from the nozzle and draw it to the appropriate site on the substrate,” says Jingyan Dong, co-corresponding author of a paper on the work and an associate professor in NC State’s Edward P. Fitts Department of Industrial & Systems Engineering. “This approach allows us to use a very wide nozzle – which prevents clogging – while retaining very fine printing resolution.”

“And because our ‘ink’ consists of a solvent containing silver nanowires that are typically more than 20 micrometers long, the resulting circuits have the desired conductivity, flexibility and stretchability,” says Yong Zhu, a professor of mechanical engineering at NC State and co-corresponding author of the paper.

“In addition, the solvent we use is both nontoxic and water-soluble,” says Zheng Cui, a Ph.D. student at NC State and lead author of the paper. “Once the circuit is printed, the solvent can simply be washed off.”

What’s more, the size of the printing area is limited only by the size of the printer, meaning the technique could be easily scaled up.

The researchers have used the new technique to create prototypes that make use of the silver nanowire circuits, including a glove with an internal heater and a wearable electrode for use in electrocardiography. NC State has filed a provisional patent on the technique.

“Given the technique’s efficiency, direct writing capability, and scalability, we’re optimistic that this can be used to advance the development of flexible, stretchable electronics using silver nanowires – making these devices practical from a manufacturing perspective,” Zhu says.

SILTECTRA GmbH today reports that it has validated a breakthrough capability for its COLD SPLIT technology. COLD SPLIT is a proven wafer-thinning technique for substrate materials like silicon carbide (SiC), gallium nitride (GaN), silicon (Si) and sapphire. A disruptive laser-based technology, COLD SPLIT out-performs traditional grinding methods by thinning wafers to 100 microns and below in minutes, with virtually no material loss. Now, thanks to a novel adaptation known as “twinning,” SILTECTRA has demonstrated that COLD SPLIT can reclaim substrate material generated (and previously wasted) during backside grinding, and create a second fully optimizable bonus wafer in the process.

The breakthrough enriches SILTECTRA’s wafering solution and promises substantial benefits for manufacturers of SiC-based ICs like power electronics and RF devices. SILTECTRA believes that the solution’s combined advantages which include fewer process steps, potentially lower equipment costs, and ultra-efficient use of substrate material, could reduce total device production costs by as much as 30 percent.

SILTECTRA validated the process by producing a GaN on SiC high electron-mobility power transistor (HEMT) device on a split-off (or “twinned”) wafer at its new state-of-the-art facility in Dresden. The HEMT showed results that were superior to a non- COLD- SPLIT-enabled HEMT when measured for CMP characterization, as well as GaN EPI, metal layer and gate layer outcomes.

Leading integrated device manufacturers (IDMs) are now evaluating the technology.

SILTECTRA’s CEO, Dr. Harald Binder, called “twinning” the “holy grail” on the company’s technology roadmap, and noted that the breakthrough was achieved ahead of schedule. “We were confident that we could not only produce a faster and cheaper thinning solution for substrates like SiC, but that we could double the value for customers by extending COLD SPLIT’s reach to create a twin wafer from material previously lost during backside grinding,” he said. “We’re thrilled to report the validation milestone, and excited to help leading IDMs realize new performance and cost benefits in their manufacturing operations.”

New substrate materials present new lower-cost manufacturing imperatives

SiC is expected to be the go-to substrate for the production of power electronics, RF, and other devices. Devices made from SiC have a smaller form-factor than those manufactured on silicon, and can handle higher voltages and frequencies with lower power consumption. Although SiC is substantially more expensive than silicon, the market is growing fast thanks to the substrate’s inherent enabling advantages. Not surprisingly, IDMs are seeking new technologies to cut the cost of producing devices based on SiC and other costly substrates.

Until now, the traditional method to thin wafers to less than 20 percent of the original thickness was grinding, which involves the use of expensive diamond grinding wheels. While valued as a reliable solution for silicon, certain challenges make it difficult for grinding to achieve the extreme level of thinness required for SiC-based devices. Unlike silicon, which is relatively soft, SiC is an extraordinarily hard substance (second only to the hardness of a diamond), which makes cutting and grinding arduous and expensive. What’s more, grinding is not a fast process, and the cost of consumables for the grinding wheels can be substantial. Finally, grinding generates material loss, and the process lowers overall yield, which further drives up cost.

The COLD SPLIT advantage

SILTECTRA engineered COLD SPLIT as a faster, higher-yield, lower-cost alternative to grinding for advanced substrates like SiC. The technique employs a chemical-physical process that uses thermal stress to generate a force that splits the material with exquisite precision along the desired plane. The solution accomplishes the thinning task in minutes instead of an hour like traditional grinding tools, and cuts material loss by as much as 90 percent.

The “twinning” breakthrough extends COLD SPLIT’s capabilities. The adaptation provides a simple way for IDMs to avoid expensive kerf-loss when slicing ingots or boules into wafers. It effectively replaces backside grinding processes, while producing an identical wafer primed for a second device run.

SILTECTRA is qualifying the process on customers’ SiC material at its newly extended facility in Dresden, while preparing to apply the COLD SPLIT technique to additional substrate materials. The company also provides wafering and thinning services at the same location.

Imec continues to advance the readiness of EUV lithography with particular focus on EUV single exposure of Logic N5 metal layers, and of aggressive dense hole arrays. Imec’s approach to enable EUV single patterning at these dimensions is based on the co-optimization of various lithography enablers, including materials, metrology, design rules, post processing and a fundamental understanding of critical EUV processes. The results, that will be presented in multiple papers at this week’s 2018 SPIE Advanced Lithography Conference, are aimed at significantly impacting the technology roadmap and wafer cost of near-term technology nodes for logic and memory.

With the industry making significant improvements in EUV infrastructure readiness, first insertion of EUV lithography in high-volume manufacturing is expected in the critical back-end-of-line metal and via layers of the foundry N7 Logic technology node, with metal pitches in the range of 36–40nm.  Imec’s research focuses on the next node (32nm pitch and below), where various patterning approaches are being considered. These approaches vary considerably in terms of complexity, wafer cost, and time to yield, and include variations of EUV multipatterning, hybrid EUV and immersion multipatterning, and EUV single expose. At SPIE last year, imec presented many advances in hybrid multipatterning and revealed various challenges of the more cost-effective EUV single exposure solution. This year, imec and its partners show considerable progress towards enabling these dimensions with EUV single exposure.

Imec’s path comprises a co-optimization of various lithography enablers, including resist materials, stack and post processing, metrology, computational litho and design-technology co-optimization, and a fundamental understanding of EUV resist reaction mechanisms and of stochastic effects. Based on this comprehensive approach, imec has demonstrated promising advances including initial electrical results, on EUV single exposure focusing on two primary use cases: logic N5 32nm pitch metal-2 layer and 36nm pitch contact hole arrays.

Working with its many materials partners, imec assessed different resist materials strategies, including chemically amplified resists, metal-containing resists and sensitizer-based resists.  Particular attention was paid to the resist roughness, and to nano-failures such as nanobridges, broken lines or missing contacts that are induced by the stochastic EUV patterning regime. These stochastic failures are currently limiting the minimum dimensions for single expose EUV. Based on this work, imec delved into the fundemental understanding of stochastics and identified the primary dependencies influencing failures. Additionally, various metrology techniques and hybrid strategies have been employed to ensure an accurate picture of the reality of stochastics. Imec will report on this collective work, demonstrating the performance of various line-space and contact hole resists.

As resist materials advances alone will likely be inssufient to meet the requirements, imec has also focused on co-optimizing the photomask, film stack, EUV exposures and etch towards an integrated patterning flow to achieve full patterning of the structures. This was done using computational lithography techniques such as optical proximity correction and source mask optimization, complemented by design-technology co-optimization to reduce standard library cell areas. Finally, etch-based post-processing techniques aimed at smoothing the images after the lithography steps yields encouraging results for dense features. Co-optimization of these mulitple knobs is key to achieving optimized patterning and edge placement error control.

Greg McIntyre, Director of advanced patterning at imec summarizes: “We feel these are very promising advances towards enabling EUV to reliably achieve single patterning at these aggressive dimensions.  This would significantly impact the cost effectiveness of patterning solutions for the next few technology nodes.”

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North America-based manufacturers of semiconductor equipment posted $2.36 billion in billings worldwide in January 2018 (three-month average basis), according to the January Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI.  The billings figure is 1.4 percent lower than the final December 2017 level of $2.40 billion, and is 27.2 percent higher than the January 2017 billings level of $1.86 billion.

“The strong billings levels from late 2017 have carried over into the new year,” said Ajit Manocha, president and CEO of SEMI. “We maintain a positive outlook for the 2018 market, marking three years of growth for equipment spending.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.
Billings
(3-mo. avg)
Year-Over-Year
August 2017
$2,181.8
27.7%
September 2017
$2,054.8
37.6%
October 2017
$2,019.3
23.9%
November 2017
$2,052.3
27.2%
December 2017 (final)
$2,398.4
28.3%
January 2018 (prelim)
$2.364.8
27.2%

Source: SEMI (www.semi.org), February 2018
SEMI publishes a monthly North American Billings report and issues the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) report in collaboration with the Semiconductor Equipment Association of Japan (SEAJ). The WWSEMS report currently reports billings by 24 equipment segments and by seven end market regions. SEMI also has a long history of tracking semiconductor industry fab investments in detail on a company-by-company and fab-by-fab basis in its World Fab Forecast and SEMI FabView databases. These powerful tools provide access to spending forecasts, capacity ramp, technology transitions, and other information for over 1,000 fabs worldwide. For an overview of available SEMI market data, please visit www.semi.org/en/MarketInfo.

Super Micro Computer, Inc. (NASDAQ: SMCI) today announced that it has expanded its Silicon Valley Headquarters to over two million square feet of facilities with the grand opening of its new Building 22.

The Corporate Headquarters includes engineering, manufacturing and customer service making Supermicro the only Tier 1 systems vendor to build its servers in Silicon Valley and worldwide.  Supermicro is ranked as the third largest server systems supplier in the world (Source: IDC).  In addition to the branded solution business used in the ranking, Supermicro also services large OEM and system integrator customers and shipped over 1.2 million units in 2017.

This latest building is the second of five facilities that the company plans to build on the 36-acre property formerly owned by the San Jose Mercury News. Additionally, the company continues to expand its other facilities worldwide.

“Having our design, engineering, manufacturing and service teams all here at our Silicon Valley campus gives Supermicro the agility to quickly respond to the newest technologies in the industry and to our customer’s needs and unique requirements, which is a major advantage that we have over the competition,” said Charles Liang, President and CEO of Supermicro.  “As our business continues to rapidly scale with over 1.2 million server and storage systems shipped globally last year, increasing our production capacity and capabilities is vital to keeping up with our rapid growth.  The opening of Building 22, along with the opening of two new facilities at our technology campus in Taiwan, provides the additional capacity and rack scale integration plug and play capabilities to ensure that we can provide the best possible service to our enterprise, datacenter, channel and cloud customers.”

“We’re thrilled to see an innovative, sustainable, and community-minded leader like Supermicro continuing to invest and grow in San Jose, and we look forward to their continued success now and for years to come!” said San Jose Mayor Sam Liccardo.

“The Corporation for Manufacturing Excellence – Manex would like to congratulate Supermicro for its continued growth through design and engineering excellence,” said Gene Russell, President and CEO of Manex.  “Its investments in workforce, physical plant and equipment are crucial to the Silicon Valley Ecosystem and to its global client base.  Manex, as a network member of the NIST Manufacturing Extension Partnership and the CMTC California network is a proud partner of Supermicro.”

Working closely with key partners like Intel, Supermicro leverages its strength in design and engineering to lead the way with first-to-market server and storage technology innovations. The company offers the industry’s broadest portfolio of advanced server and storage solutions including the popular BigTwin™ and SuperBlade® product lines and provides rack scale integration with rack plug and play capabilities.

In January, Gigaphoton Inc. (Head office: Oyama City, Tochigi Prefecture. President & CEO: Katsumi Uranaka), a major manufacturer of lithography light sources, announced the shipment of an ArF Excimer Laser for advanced immersion exposure (lithography) devices, the “GT65A” Unit 1, as a new product that meets the growing demand for semiconductors in recent years. The new technology of the GT65A significantly contributes to the rise in productivity of lithography equipment by providing stable operation of the laser and improvement of process margins.

The GT65A will also deliver a 50% reduction in service downtime. This key feature is realized by increasing chamber lifetime by 30% as well as improving maintenance efficiency through the utilization of extensive service data expertise acquired through many years of successful service execution.

In addition, the stabilization technology “eMPL Solid” and the control function “hMPL,” which form the spectrum control function, enable the improvement of CD uniformity as well as expanding process latitude.

Furthermore, the GT65A has successfully eliminated the need to use helium gas. Due to this, we are able to contribute to enhancing customers’ sustainability and CSR activities by not only reducing environmental impact, but also by greatly reducing risks associated with future helium gas supply deficits and price increases.

Katsumi Uranaka, President & CEO of Gigaphoton commented, “With the boom in recent years of the semiconductor market, improving the availability of lithography equipment is an important issue for each manufacturer. With the new technology in line with our new roadmap ‘RAM Enhancement,’ we have further strengthened and improved the Reliability, Availability and Maintainability of lithography light sources, contributing to the semiconductor manufacturing industry.”

Peter Trefonas, Ph.D., corporate fellow in Dow Electronic Materials, has recently been elected a Fellow of SPIE, for achievements in design for manufacturing and compact modeling.

SPIE, the international society for optics and photonics, will promote 73 new Fellows of the Society this year, to recognize the significant scientific and technical contributions of each in the multidisciplinary fields of optics, photonics, and imaging. SPIE Fellows are honored for their technical achievements and for their service to the general optics community and to SPIE in particular.

Trefonas has proven himself to be a leader in advanced lithographic technology with numerous highly cited and pioneering papers in key areas of advanced lithography. He contributed to the fundamental investigations of resist chemical mechanisms, such as polyphotolysis, a mechanism of nonlinear development and dissolution rate models based on first principles. He also contributed papers on percolation and reactive diffusion mechanisms. Trefonas authored some of the first papers on shot noise and stochastic effects, as well as the first paper on fractal analysis of development, and the first paper on information theory of lithography. He is coauthor on a simple method to measure the photoacid quantum efficiency, and contributed to a prominent paper on extreme ultraviolet (EUV) stochastics and stochastic development model. He has also published groundbreaking work on deterministic bottom-up/top-down materials designs.

Trefonas has given extensive service to the global optics community, through published literature and his role in technical conferences. He authored significant sections of the ITRS Semiconductor Roadmap, content dedicated to emerging materials. He organized and chaired a conference on emerging display materials for the Materials Research Society, chaired multiple conferences on microlithography for IEEE, and organized and chaired a conference on directed self-assembly (DSA) and block copolymers for the American Physical Society. As a lecturer, he has given full-day tutorials on lithography and antireflectant coatings at multiple locations in the US, Europe, and Asia. He is also helping to build up the next generation of innovators, responsible for hiring and mentoring over 40 scientists who are currently active and contributing to the science and materials of great interest to the optical community.

A long-time member of SPIE, Trefonas has also given significant service to the Society. He has published 41 papers in the Proceedings of SPIE and has published papers in the Journal of Micro/Nanolithography, MEMS, and MOEMS. He is currently an active reviewer of papers on lithographic materials for SPIE journals.

Trefonas’ work has been recognized with many prestigious honors and awards. Among them are the Society of Chemical Industry Perkin Medal for contributions in industrial chemistry, the American Chemical Society Heroes of Chemistry Award for organic fast plasma etch antireflectants, the C. Grant Willson Award for best oral paper at SPIE Advanced Lithography, Rohm and Haas Technology Awards for antireflectants and 248nm resists, the Shipley R&D Innovation Award for i-line photoresists, and the Monsanto Ex Obscura Award for creativity in innovation. He has also recently been elected as a member of the National Academy of Engineering.

Trefonas will be recognized as a new SPIE Fellow at SPIE Advanced Lithography later this month in San Jose, California.

Entering 2018 on solid ground


February 22, 2018

By Walt Custer, Custer Consulting Group

2017 finished on an upturn – both in the USA and globally.  Based on consolidated fourth-quarter actual and estimated revenues of 213 large, global electronic manufactures, sales rose in excess of 7 percent in 4Q’17 vs. 4Q’16 (Chart 1).  This was the highest global electronic equipment sales growth rate since the third quarter of 2011. Because some companies in our sample didn’t close their financial quarter until the end of January, final results will take a few more weeks – but all evidence points to a very strong fourth quarter of last year.

Custer1-Electronic-Equipment

 

Using regional (country specific) data (Chart 2), the normal, consumer electronics driven seasonal downturn began again in January.  However the recent year-over-year growth is still substantial.  On a total electronic equipment revenue basis, January 2018 was up almost 19.5 percent over January 2017.

Custer2-World-Electronic

Because this regional data in local currencies was converted to U.S. dollars at fluctuating exchange, the dollar denominated-growth was amplified by currency exchange effects.  At constant exchange the January growth was only 14 percent.   That is, when the stronger non-U.S. currencies were converted to weakening dollars, the dollar-denominated January 2018 fluctuating exchange growth was amplified by 5.5 percent.

Chart 3 shows 4Q’17/4Q’16 growth of the domestic electronic supply chain.  U.S. electronic equipment shipments were up 9.1 percent.  Only computer equipment and non-defense aircraft sales declined in the fourth quarter.  And of note, SEMI equipment shipments to North America rose almost 31 percent!

Custer3-US-Electronic-Supply

 

Chart 4 shows estimated fourth-quarter growth for the world electronic supply chain.  Only “Business & Office” equipment revenues declined in 4Q’17 vs. 4Q’16.

Custer4-Global-Electronic

Total global electronic equipment sales increased more than 7 percent in the fourth quarter and SEMI equipment revenues rose 32 percent.

2017 was a strong year and 2018 is off to a good start!  The 2017 lofty growth rates will temper, but this current expansion will likely continue.  Watch the monthly numbers!

Originally published on the SEMI blog.