Category Archives: Semiconductors

ProPlus Design Solutions Inc. and MPI Corporation today announced a strategic partnership agreement and immediate availability of a characterization and modeling solution that integrates ProPlus’ SPICE modeling and noise characterization solution with MPI’s advanced probing technologies.

The integrated solution offers seamless support of the MPI probe stations to perform automated measurement of DC, CV and noise characteristics, enabling MPI users easy access to the most accurate ProPlus SPICE modeling and noise characterization offerings. The advanced probing technologies developed by MPI are optimized for the latest ProPlus 9812DX noise analyzer with improved grounding and shielding technologies critical to wafer-level noise characterization.

Under the partnership agreement, ProPlus users are able to integrate MPI’s advanced semi-automatic probe stations in their characterization and modeling flow for better noise measurement quality. The close collaboration also proved that probe card wafer-level noise characterization is possible using the 9812DX noise analyzer. Previously, these measurements were performed using manipulators and easily introducing RF interferences and oscillations. The advanced probe card technology specially developed for noise measurement provides better data quality and stability, as well as improves flexibility of wafer-level noise characterization for higher throughput.

“ProPlus Design Solutions continues to invest on improving the technologies that made wafer-level noise characterization possible 20 years ago,” remarks Dr. Zhihong Liu, chairman and chief executive officer of ProPlus Design Solutions. “We brought it to the next level with a specially designed probe card for a tightly integrated noise system thus delivering the fastest and most accurate noise characterization of the highest quality. We’re pleased to work with MPI on this effort.”

“The collaboration with ProPlus Design Solutions has enabled a seamlessly integrated wafer level low-frequency noise measurement capability with guaranteed system configuration and performance,” says Dr. Stojan Kanev, general manager of Advanced Semiconductor Test Division at MPI Corporation. “We now offer the most advanced high throughput noise characterization and modeling system. MPI’s exceptional shielding technology provides world class 1/f noise measurement capability. Customers may now rest assured these systems are validated to provide reliable and accurate noise measurement capability while enjoying a reduced cost of test.”

The integrated solution has been adopted by leading semiconductor companies. ProPlus and MPI Corporation will demonstrate the joint solution globally throughout 2018.

SUNY Polytechnic Institute (SUNY Poly) Professor of Nanoengineering Bin Yu has been named a Fellow of the National Academy of Inventors (NAI), the organization announced Tuesday. Election to NAI Fellow status is one of the highest professional accolades bestowed solely to academic inventors who have demonstrated a prolific spirit of innovation in creating or facilitating outstanding inventions that have made a tangible impact on quality of life, economic development, and the welfare of society.

“I am proud to congratulate Dr. Yu on his selection as Fellow of the NAI, which is a strong reflection of his research that has helped to advance cutting-edge nanotechnologies,” said SUNY Poly Interim President Dr. Bahgat Sammakia. “Dr. Yu’s numerous patents and continued SUNY Poly-based research in exciting areas such as nanomaterials and advanced nano-devices continues to hold promise for further developments that can enhance energy efficiency and boost computing speeds to improve the technologies that our society relies on each day.”

Those elected to the rank of NAI Fellow are named inventors on U.S. patents and were nominated by their peers for outstanding contributions to innovation, as well as for patents and licensing, innovative discovery and technology, and providing significant impact on society.

Dr. Yu has a number of significant accomplishments in the areas of nano electronic devices, nano-based sensors, nano-based energy harvesting, emerging data storage devices, next-generation interconnects, and smart nano-manufacturing, including work as the lead researcher for the world’s first 10 nm gate-length 3D transistor FinFET (IEEE-IEDM’2002), and for the world’s first THz silicon logic switch (IEEE-IEDM’2001).

Dr. Yu is the recipient of multiple awards and honors, including the NASA Innovation Award and IBM Faculty Award, and was ranked #3 by the National Science Foundation for Supported Investigators with Most Patents in 2011; as an inventor, he holds more than 300 awarded U.S. patents.

“I am honored that I have been selected to become a National Academy of Inventors Fellow, a powerful recognition of the work undertaken at SUNY Poly which can help to advance technology based on a wide variety of applied nanostrucutures,” said Dr. Yu. “I congratulate my fellow inductees and appreciate the acknowledgement of the importance of these research contributions that have led to more than 300 U.S. patents. I look forward to continuing to pursue efforts utilizing SUNY Poly’s state-of-the-art resources and capabilities for research related to nano-inspired technologies targeted for the next-generation of computing, sensing, and energy generation, as well as research related to emerging nanomaterials for smart nanomanufacturing.”

Dr. Yu has published books and book chapters on topics ranging from graphene-based electronics to 2D layered semiconductor-based emerging solar photovoltaics. He has also served as Editor of IEEE Electron Device Letters from 2001-2007, Associate Editor of IEEE Transactions on Nanotechnology from 2007-2010, and is currently an Editorial Board Member for Nano-Micro Letters and an Editorial Advisory Board Member for Nanoelectronics and Spintronics, among other leadership positions. Dr. Yu has been invited as a speaker to more than 100 highlight/invited talks, seminars, and tutorials to international conferences, universities, industry national labs, and professional societies. He is also an Institute of Electrical and Electronics Engineers (IEEE) Fellow and IEEE Electronic Device Society Distinguished Lecturer. More information about Dr. Yu’s background can be found here.

With the election of the 2017 class there are now 912 NAI Fellows, representing over 250 research universities and governmental and non-profit research institutes. The 2017 Fellows are named inventors on nearly 6,000 issued U.S. patents, bringing the collective patents held by all NAI Fellows to more than 32,000 issued U.S. patents.

Included among all NAI Fellows are more than 100 presidents and senior leaders of research universities and non-profit research institutes; 439 members of the National Academies of Sciences, Engineering, and Medicine; 36 inductees of the National Inventors Hall of Fame; 52 recipients of the U.S. National Medal of Technology and Innovation and U.S. National Medal of Science; 29 Nobel Laureates; 261 AAAS Fellows; 168 IEEE Fellows; and 142 Fellows of the American Academy of Arts & Sciences, among other awards and distinctions.

In April 2018 the 2017 NAI Fellows will be inducted as part of the Seventh Annual NAI Conference of the National Academy of Inventors at the Mayflower Hotel, Autograph Collection in Washington, D.C., and Andrew H. Hirshfeld, U.S. Commissioner for Patents, will provide the keynote address for the induction ceremony.

The 2017 class of NAI Fellows was evaluated by the 2017 Selection Committee, which included 18 members comprising NAI Fellows, U.S. National Medals recipients, National Inventors Hall of Fame inductees, members of the National Academies of Sciences, Engineering, and Medicine and senior officials from the USPTO, National Institute of Standards and Technology, Association of American Universities, American Association for the Advancement of Science, Association of Public and Land-grant Universities, Association of University Technology Managers, and National Inventors Hall of Fame, among other organizations.

Today, SEMI, the global industry association representing the electronics manufacturing supply chain, released its Year-end Forecast at the annual SEMICON Japan exposition. SEMI projects that worldwide sales of new semiconductor manufacturing equipment will increase 35.6 percent to US$55.9 billion in 2017, marking the first time that the semiconductor equipment market has exceeded the previous market high of US$47.7 billion set in 2000. In 2018, 7.5 percent growth is expected to result in sales of US$60.1 billion for the global semiconductor equipment market – another record-breaking year.

The SEMI Year-end Forecast predicts a 37.5 percent increase in 2017, to $45.0 billion, for wafer processing equipment. The other front-end segment, which consists of fab facilities equipment, wafer manufacturing, and mask/reticle equipment, is expected to increase 45.8 percent to $2.6 billion. The assembly and packaging equipment segment is projected to grow by 25.8 percent to $3.8 billion in 2017, while semiconductor test equipment is forecast to increase by 22.0 percent to $4.5 billion this year.

In 2017, South Korea will be the largest equipment market for the first time. After maintaining the top spot for five years, Taiwan will place second, while China will come in third. All regions tracked will experience growth, with the exception of Rest of World (primarily Southeast Asia). South Korea will lead in growth with 132.6 percent, followed by Europe at 57.2 percent, and Japan at 29.9 percent.

SEMI forecasts that in 2018, equipment sales in China will climb the most, 49.3 percent, to $11.3 billion, following 17.5 percent growth in 2017. In 2018, South Korea, China, and Taiwan are forecast to remain the top three markets, with South Korea maintaining the top spot at $16.9 billion. China is forecast to become the second largest market at $11.3 billion, while equipment sales to Taiwan are expected to approach $11.3 billion.

The following results are in terms of market size in billions of U.S. dollars:

equipment forecast

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced it has received an order from the University of Tokyo for its EVG810LT plasma activation system for compound semiconductor research. Installed at the university’s Takagi & Takenaka Laboratory, the EVG810LT augments the laboratory’s research focused on developing novel MOSFET and electronic-photonic integrated circuits (EPICs) using III-V-on-insulator (III-V-OI) and germanium-on-insulator (GeOI) substrates. These advanced material substrates are designed to exceed the performance of conventional silicon semiconductors as well as silicon photonics, where III-V materials such as indium phosphide (InP), indium gallium arsenide (InGaAs) and germanium are bonded to silicon wafers. The EVG810LT activates a wafer surface using plasma for low-temperature direct wafer bonding, and has been utilized by other customers in high-volume manufacturing of silicon-on-insulator (SOI) wafers and backside illuminated CMOS image sensors.

“The miniaturization of semiconductor devices is reaching its physical limitations, and shrinking transistor (scaling) in line with Moore’s Law is not sufficient enough to address future demands for higher performance of LSI devices,” noted Dr. Mitsuru Takenaka, associate professor at the Takagi & Takenaka Laboratory with the University of Tokyo. “3D integrated circuits with III-V compound semiconductors or germanium stacked freely on silicon semiconductors are expected to be among the breakthroughs to enhance the performance of the LSIs after the end of Moore’s Law. In support of our efforts, we adopted EV Group’s plasma activation system, the EVG810LT, to help us achieve lower temperature and high-quality wafer bonds.”

Commenting on today’s announcement, Hiroshi Yamamoto, representative director of
EV Group Japan K.K., said, “It is a great honor that our system was selected to support the University of Tokyo’s leading-edge LSI device research. The innovative results at The Takagi & Takenaka Laboratory are expected to address the fundamental issues that the semiconductor industry currently faces. Based on our company’s Triple-i philosophy of ‘invent, innovate and implement’, EV Group has been working with universities and R&D facilities that are active in advanced fields. We will continue to provide the Takagi & Takenaka Laboratory with the technical support they need to succeed with their leading-edge research.”

The emergence of the Internet of Things (IoT), Big Data and artificial intelligence (AI) is fueling a new wave of demand for electronic devices with lower power consumption, higher performance, and greater functionality. To meet this demand, the semiconductor industry is evaluating the benefits of incorporating new materials with silicon-beyond pure silicon-based wafers. This shift is paving the way for future market growth of compound semiconductors, as well as more efficient manufacturing technologies to achieve maximum end-device performance. For example, metal-organic chemical vapor deposition (MOCVD) processes, where a thin film of II-VI or III-V material is deposited on a substrate by heteroepitaxial growth, can result in inconsistent wafer formation. This compromises the integrity of the wafer surface and ultimately impacts end-device performance. Direct wafer bonding with plasma activation is a promising solution to enable heterogeneous integration of different materials and to realize high-quality engineered substrates.

EVG will showcase the EVG810LT system at the SEMICON Japan exhibition being held December 13-15 at the Tokyo Bit Sight – Tokyo International Exhibition Center in Tokyo, Japan.

University of Alabama at Birmingham physicists have taken the first step in a five-year effort to create novel compounds that surpass diamonds in heat resistance and nearly rival them in hardness.

They are supported by a five-year, $20 million National Science Foundation award to create new materials and improve technologies using the fourth state of matter — plasma.

Plasma — unlike the other three states of matter, solid, liquid and gas — does not exist naturally on Earth. This ionized gaseous substance can be made by heating neutral gases. In the lab, Yogesh Vohra, a professor and university scholar in the UAB Department of Physics, uses plasma to create thin diamonds film. Such films have many potential uses, such as coatings to make artificial joints long-lasting or to maintain the sharpness of cutting tools, developing sensors for extreme environments or creating new super-hard materials.

To make a diamond film, Vohra and colleagues stream a mix of gases into a vacuum chamber, heating them with microwaves to create plasma. The low pressure in the chamber is equivalent to the atmosphere 14 miles above the Earth’s surface. After four hours, the vapor has deposited a thin diamond film on its target.

In a paper in the journal Materials, Vohra and colleagues in the UAB College of Arts and Sciences investigated how the addition of boron, while making a diamond film, changed properties of the diamond material.

It was already known that, if the gases are a mix of methane and hydrogen, the researchers get a microcrystalline diamond film made up of many tiny diamond crystals that average about 800 nanometers in size. If nitrogen is added to that gas mixture, the researchers get nanostructured diamond, made up of extremely tiny diamond crystals averaging just 60 nanometers in size.

In the present study, the Vohra team added boron, in the form of diborane, or B2H6, to the hydrogen/methane/nitrogen feed gas and found surprising results. The grain size in the diamond film abruptly increased from the 60-nanometer, nanostructured size seen with the hydrogen/methane/nitrogen feed gas to an 800-nanometer, microcrystalline size. Furthermore, this change occurred with just minute amounts of diborane, only 170 parts per million in the plasma.

Using optical emission spectroscopy and varying the amounts of diborane in the feed gas, Vohra’s group found that the diborane decreases the amounts of carbon-nitrogen radicals in the plasma. Thus, Vohra said, “our study has clearly identified the role of carbon-nitrogen species in the synthesis of nanostructured diamond and suppression of carbon-nitrogen species by addition of boron to the plasma.”

Since the addition of boron can also change the diamond film from a nonconductor into a semiconductor, the UAB results offer a new control of both diamond film grain size and electrical properties for various applications.

Over the next several years, Vohra and colleagues will probe the use of the microwave plasma chemical vapor deposition process to make thin films of boron carbides, boron nitrides and carbon-boron-nitrogen compounds, looking for compounds that survive heat better than diamonds and also have a diamond-like hardness. In the presence of oxygen, diamonds start to burn at about 1,100 degrees Fahrenheit.

CVD Equipment Corporation (NASDAQ: CVV), a provider of chemical vapor deposition systems and materials announced today that it has completed the purchase of the Company’s planned additional facility, located at 555 North Research Place, Central Islip, NY. This new facility will be the primary manufacturing center for the Company’s wholly owned subsidiary, CVD Materials Corporation.

Leonard A. Rosenbaum, President and Chief Executive Officer stated, “With the completion of this purchase we now have the manufacturing space to accelerate our capabilities of providing materials, coatings, and surface treatments to meet our customers’ needs. We look forward to the expansion of our carbon composites and electronic material, Tantaline®, and newly acquired MesoScribe™, product lines. We also anticipate future growth, both organically and by possible future acquisitions. With the purchase behind us, we are now focusing on bringing the new facility on-line and for additional growth opportunities enabled by this additional 180,000 square foot facility.”

CVD Equipment Corporation designs, develops, and manufactures a broad range of chemical vapor deposition, gas control, and other equipment and process solutions used to develop and manufacture materials and coatings for research and industrial applications.

Power electronics, which do things like modify voltages or convert between direct and alternating current, are everywhere. They’re in the power bricks we use to charge our portable devices; they’re in the battery packs of electric cars; and they’re in the power grid itself, where they mediate between high-voltage transmission lines and the lower voltages of household electrical sockets.

Power conversion is intrinsically inefficient: A power converter will never output quite as much power as it takes in. But recently, power converters made from gallium nitride have begun to reach the market, boasting higher efficiencies and smaller sizes than conventional, silicon-based power converters.

Commercial gallium nitride power devices can’t handle voltages above about 600 volts, however, which limits their use to household electronics.

At the Institute of Electrical and Electronics Engineers’ International Electron Devices Meeting this week, researchers from MIT, semiconductor company IQE, Columbia University, IBM, and the Singapore-MIT Alliance for Research and Technology, presented a new design that, in tests, enabled gallium nitride power devices to handle voltages of 1,200 volts.

That’s already enough capacity for use in electric vehicles, but the researchers emphasize that their device is a first prototype manufactured in an academic lab. They believe that further work can boost its capacity to the 3,300-to-5,000-volt range, to bring the efficiencies of gallium nitride to the power electronics in the electrical grid itself.

That’s because the new device uses a fundamentally different design from existing gallium nitride power electronics.

“All the devices that are commercially available are what are called lateral devices,” says Tomás Palacios, who is an MIT professor of electrical engineering and computer science, a member of the Microsystems Technology Laboratories, and senior author on the new paper. “So the entire device is fabricated on the top surface of the gallium nitride wafer, which is good for low-power applications like the laptop charger. But for medium- and high-power applications, vertical devices are much better. These are devices where the current, instead of flowing through the surface of the semiconductor, flows through the wafer, across the semiconductor. Vertical devices are much better in terms of how much voltage they can manage and how much current they control.”

For one thing, Palacios explains, current flows into one surface of a vertical device and out the other. That means that there’s simply more space in which to attach input and output wires, which enables higher current loads.

For another, Palacios says, “when you have lateral devices, all the current flows through a very narrow slab of material close to the surface. We are talking about a slab of material that could be just 50 nanometers in thickness. So all the current goes through there, and all the heat is being generated in that very narrow region, so it gets really, really, really hot. In a vertical device, the current flows through the entire wafer, so the heat dissipation is much more uniform.”

Narrowing the field

Although their advantages are well-known, vertical devices have been difficult to fabricate in gallium nitride. Power electronics depend on transistors, devices in which a charge applied to a “gate” switches a semiconductor material — such as silicon or gallium nitride — between a conductive and a nonconductive state.

For that switching to be efficient, the current flowing through the semiconductor needs to be confined to a relatively small area, where the gate’s electric field can exert an influence on it. In the past, researchers had attempted to build vertical transistors by embedding physical barriers in the gallium nitride to direct current into a channel beneath the gate.

But the barriers are built from a temperamental material that’s costly and difficult to produce, and integrating it with the surrounding gallium nitride in a way that doesn’t disrupt the transistor’s electronic properties has also proven challenging.

Palacios and his collaborators adopt a simple but effective alternative. The team includes first authors Yuhao Zhang, a postdoc in Palacios’s lab, and Min Sun, who received his MIT PhD in the Department of Electrical Engineering and Computer Science (EECS) last spring; Daniel Piedra and Yuxuan Lin, MIT graduate students in EECS; Jie Hu, a postdoc in Palacios’s group; Zhihong Liu of the Singapore-MIT Alliance for Research and Technology; Xiang Gao of IQE; and Columbia’s Ken Shepard.

Rather than using an internal barrier to route current into a narrow region of a larger device, they simply use a narrower device. Their vertical gallium nitride transistors have bladelike protrusions on top, known as “fins.” On both sides of each fin are electrical contacts that together act as a gate. Current enters the transistor through another contact, on top of the fin, and exits through the bottom of the device. The narrowness of the fin ensures that the gate electrode will be able to switch the transistor on and off.

“Yuhao and Min’s brilliant idea, I think, was to say, ‘Instead of confining the current by having multiple materials in the same wafer, let’s confine it geometrically by removing the material from those regions where we don’t want the current to flow,'” Palacios says. “Instead of doing the complicated zigzag path for the current in conventional vertical transistors, let’s change the geometry of the transistor completely.”

Leti, a research institute of CEA Tech, demonstrated significant improvements in the field of memory systems at IEDM 2017 this week.

These include reconfiguring Static Random-Access Memory (SRAM) into Content-Addressable Memory (CAM), improving non-volatile crossbar memories and using advanced Tunnel Field-Effect Transistors (TFET). Another breakthrough presents a high-density SRAM bitcell on Leti’s CoolCubeTM 3D platform, which reduces the area required for memory by 30 percent, while maintaining full device functionality. This breakthrough points the way to easing the major memory bottleneck in more complex systems on chip (SoC), where up to 90 percent of the SoC area might be taken by SRAM.

The breakthroughs were reported Dec. 5 at IEDM 2017 in a paper titled “Advanced Memory Solutions for Emerging Circuits and Systems.”

A key obstacle to shrinking SRAM on SoCs is bitcell-area limitations linked to required performance and yield, both of which become more challenging as technology scales. Lowering system power consumption is also limited by memory, as the SRAM performance and its stability scale less successfully than logic performance at lower voltages. Other memories like CAM might be affected even more by voltage scaling.

“All of these obstacles become particularly important for the Internet of Things, where ultralow-power consumption and the cost of individual nodes are crucial, and SRAM limitations have a big impact on both,” said Bastien Giraud, one of the paper authors.

Leti approached these challenges with a CoolCubeTM SRAM design focusing on the development of a compact and functional four-transistor bitcell, along with other innovations:

  • Reconfiguring memory between the CAM and SRAM, depending on the application
  • Optimizing memory using TFET, focusing on the exploitation of its negative differential-resistance effect to build ultralow-power SRAM, Flip Flops (FF) and refresh-free Dynamic Random Access Memory (DRAM)
  • A new compensation technique for crosspoint memory that reduces the voltage drop and leads to larger memory arrays.

Leti said its proposed CAM/SRAM outperforms memories, with operations at 1.56GHz and 0.13fJ/bit energy per search. In addition, the proposed TFET designs are competitive in terms of area, performance and static power consumption. Leti’s proposed compensation technique in crosspoint memory also enables the design of cost-efficient large memory arrays, while reducing the impact of temporal and spatial variations.

Short-term applications include crossbar circuits for storage-class memory and flexible SOCs with SRAM/CAM re-configurability.

“In the longer term, Leti’s CoolCubeTM technology will be able to deliver very high-density SRAM,” Giraud said. “Enabling TFET-based DRAM and integrating TFET standard cells into CMOS designs will allow circuit designers to take advantage of the best features of both technologies.”

By Inna Skvortsova, SEMI

Electromagnetic interference (EMI) is an increasingly important topic across the global electronics manufacturing supply chain.  Progressively smaller geometries of ICs, lower supply voltages, and higher data rates all make devices and processes more vulnerable to EMI. Electrical noise, EMI-induced signal generated by equipment, and factors such as power line transients affect manufacturing processes, from wafer handling to wire bonding to PCB assembly and test, causing millions of dollars in losses to the industry. Furthermore, conducted emission capable of causing electrical overstress (EOS) can damage sensitive semiconductor devices.  Intel consistently names EOS as the “number one source of damage to IC components.” (Intel® Manufacturing Enabling Guide 2001, 2010, 2016).

While EMC (Electromagnetic Compatibility) standards, such as the European EMC Directive and FCC Testing and Certification, etc. provide limits on allowed emission levels of equipment, once the equipment is installed along with other tools, the EMI levels in actual operating environments can be substantially different and therefore impact the equipment operation, performance, and reliability. For example, (i) Occasional transients induce “extra” pulses in rotary feedback of the servo motor which in time contributes to robotic arm’s erroneous position eventually damaging the wafer; (ii) Combination of high-frequency noise from servo motors and switched mode power supplies in the tool creates difference in voltage between the bonding wire/funnel and the device which causes high current and eventual electrical overstress to the devices; (iii) Wafer probe test provides inconsistent results due to high level of EMI on the wafer chuck caused by a combination of several servo motors in the wafer handler.  Field cases like these illustrate the gap between EMC test requirements and real-life EMI tolerance levels and its impact on semiconductor manufacturing and handling.

EMI on AC power lines

EMI on AC power lines

New standard, SEMI E176-1017, Guide to Assess and Minimize Electromagnetic Interference (EMI) in a Semiconductor Manufacturing Environment, developed by the NA Chapter of the Global Metrics Technical Committee bridges this gap. Targeted to IC manufacturers and anyone handling semiconductor devices, such as PCB assembly and integration of electronic devices, SEMI E176 is a practical guide as well as an educational document. SEMI E176 provides a concise summary of EMI origins, EMI propagation, measurement techniques and recommendations on mitigation of undesirable electromagnetic emission to enable equipment co-existence and proper operation as well as reduction of EOS in its intended usage environment. Specifically, E176 provides recommended levels for different types of EMI based on IC geometries.

“SEMI E176 is likely the only active Standard in the entire industry providing recommendations on both acceptable levels of EMI in manufacturing environments and the means of achieving and maintaining these numbers,” said Vladimir Kraz, co-Chair of the NA Metrics Technical Committee and president of OnFILTER, Inc. “E176 is also unique because it is not limited just to semiconductor manufacturing, but has application across other industries.  Back-end assembly and test, as well as PCB assembly are just as affected by EMI and can benefit from SEMI E176 implementation as there are strong similarities between handling of semiconductor devices in IC manufacturing and in PCB assemblies and prevention of defects is often shared between IC and PCBA manufacturers.”

The newly published SEMI E176 and recently updated SEMI E33-0217, Guide for Semiconductor Manufacturing Equipment Electromagnetic Compatibility (EMC),provide complete documentation for establishing and maintaining low EMI levels in the manufacturing environment.

Undesirable emission has operational, liability and regulatory consequences.  Taming it is a challenging task and requires a comprehensive approach that starts from proper system design practices and ends with developing EMI expertise in the field.  The new SEMI 176 provides practical guidance on reducing EMI to the levels necessary for effective high yield semiconductor manufacturing today and in the future.

SEMI Standards development activities take place throughout the year in all major manufacturing regions. To get involved, join the SEMI International Standards Program at: www.semi.org/standardsmembership.

 

BY ANDREW CHAMBERS, Senior Product Manager, Edwards Ltd.

With the prospects of large 450mm wafers going nowhere, IC manufacturers are increasing efforts to maximize fabrication plants using 300mm and 200mm diameter silicon substrates. The number of 300mm wafer production-class fabs in operation worldwide is expected to increase each year between now and 2021 to reach 123 compared to 98 in 2016, according to the forecast in IC Insights’ Global Wafer Capacity 2017-2021 report.

Significant opportunities to improve safety, reliability and yield still remain in our industry, many of them to be found in the sub-fab, where the critical systems that supply vacuum and treat exhaust gases are to be found—out of sight and, too often, out of mind. Properly handling and removing noxious components in the exhaust flow clearly impacts the safety of fab personnel and the quality of the local environment. As for reliability, when the sub-fab fails the process is down. And yield—the yield of many tools depends directly on steady, high-quality vacuum. “Smart” management of sub-fab systems can improve safety, reliability, yield, and energy efficiency, all of which contribute directly to the bottom line.

For example, consider high-flow CVD processes, which are finding increasing application in high-volume production of 3D-NAND, DRAM and other devices. The process precursors and their decomposition products can present a flammability risk and, unless properly controlled, can condense as hazardous materials in process exhausts. Such condensation can cause a variety of operational problems, including process shut-downs when pipes become blocked, exhaust pipe fires when fluorine reacts with residual silicon compounds, and HF vapour releases when pipes are exposed to atmosphere during cleaning.

Several approaches may be used to address these concerns, alone or in combination. The entire exhaust assembly may be heated to maintain a thermal profile that eliminates conden- sation, though eliminating all cold spots can pose practical difficulties and constant monitoring is required. Exhaust gases may be diluted to mitigate flammability risks, but the cost of the additional diluting gas (N2) becomes prohibitive at high flows. The total cost of ownership for high dilution flows must
also include increased capital investment, operating cost and sub-fab space require- ments for additional abatement capacity.

A smart dilution strategy would continuously adjust the flow of dilution gas based on information from the process tool. Is flammable gas flowing? Is oxidant gas present? If the process gas is non-flammable, can dilution be eliminated entirely? When only a flammable gas is flowing, how much can dilution be relaxed while still maintaining the mixture below the lower flammability limit; or can it be allowed to exceed the LFL, since there is no concurrently flowing oxidant? When flammable gases flow concurrently with oxidizing gases, what dilution is required to keep the concentration of flammable gas below its LFL, with a sufficient safety margin to allow for fault scenarios? What is the best dilution for cleaning gases to optimize the safety and efficiency in their abatement? Answers to these questions and more can be found by analyzing information from the process tool and can be used in a smart dilution strategy to ensure safety, and maximize reliability and yield while minimizing cost.

Information from the process tool can also be used to control the operation of the abatement system. When only flammable gas is flowing with low or moderate dilution, the abatement system can be operated in a “low fire” mode, minimizing consumption of fuel, city water and process cooling water. When flammable and oxidizing gases flow concurrently and high dilution flow is used, the abatement can be switched into a “high fire” mode to ensure full destruction of the process chemicals.

Coupled with smart operation, smart system design can further improve safety, reliability and cost. Consider the problem of gas leaks. Leaks from process exhaust pipes can lead to fires, equipment damage and harm to sub-fab personnel. Local gas leak detectors can protect personnel but risk process shut-down and product loss. Rigorous leak checking proce- dures can reduce the risk of leaks following maintenance, but cannot prevent progressive seal degradation or leaks that occur during normal operation. A smart design integrates pumps, abatement and all connecting piping in a single unit, engineered for performance and safety and thoroughly tested at all stages of manufacturing and installation. Integration also permits exhaust integrity checking, double-containment, accurate and consistent exhaust temperature control, and tool-connected “smart” operation and provides single-vendor responsibility for maintenance and performance.

Opportunities for improvements abound, but taking advantage of them requires a smart approach based on broad experience and thorough understanding of semiconductor manufacturing processes.