Category Archives: Semiconductors

Leti, a research institute of CEA Tech, has integrated hybrid III-V silicon lasers on 200mm wafers using standard CMOS process flow. This breakthrough shows the way to transitioning away from 100mm wafers and a process based on bulk III-V technology that requires contacts with noble metals and lift-off based patterning.

The project, carried out in the framework of the IRT Nanoelec program, which is headed by Leti, demonstrated that the hybrid device’s performance is comparable to the reference device fabricated with the current process on 100mm wafers. The fabrication flow is fully planar and compatible with large-scale integration on silicon-photonic circuits.

The results were reported Dec. 5 at IEDM 2017 in a paper titled “Hybrid III-V/Si DFB Laser Integration on a 200mm Fully CMOS-compatible Silicon Photonics Platform”.

CMOS compatibility with silicon photonics lowers fabrication costs, and provides access to mature and large-scale facilities, which enables packaging compatibility with CMOS driving circuits.

“Silicon-photonic technologies are becoming more mature, but the main limitation of these platforms is the lack of an integrated light source,” said Bertrand Szelag, a co-author of the paper. “This project showed that a laser can be integrated on a mature silicon-photonic platform with a modular approach that does not compromise baseline process performances. We demonstrated that the entire process can be done in a standard CMOS fabrication line with conventional process and materials, and that it is possible to integrate all the photonic building blocks at large scale.”

The integration required managing a thick silicon film, typically 500nm thick, for the hybrid laser, and a thinner one, typically 300nm, for the baseline silicon-photonic platform. This required locally thickening the silicon by adding 200nm of amorphous silicon via a damascene process, which presents the advantage of leaving a flat surface favorable for bonding III-V silicon. The laser can be integrated on a mature silicon photonic platform with a modular approach that does not compromise the baseline process performance.

The novelty of the approach also included using innovative laser electrical contacts that do not contain any noble metals, such as gold. The contacts also prohibit integration lift-off-based processes. Nickel-based metallization was used with an integration technique similar to a CMOS transistor technique, in which tungsten plugs connect the device to the routing metal lines.

Next steps include integrating the laser with active silicon-photonic devices, e.g. a modulator and photodiode with several interconnect metal levels in a planarized backend. Finally, III-V die bonding will replace III-V wafer bonding in order to process lasers on the entire silicon wafer.

Tilted scanning electron microscopy view of the III-V/Si DFB laser after the IIIV patterning steps.

Tilted scanning electron microscopy view of the III-V/Si DFB laser after the IIIV patterning steps.

Laser spectrum at 160 mA injection currents

Laser spectrum at 160 mA injection currents

A group of spintronics researchers at EPFL is using new materials to reveal more of the many capabilities of electrons. The field of spintronics seeks to tap the quantum properties of “spin,” the term often used to describe one of the fundamental properties of elementary particles – in this case, electrons. This is among the most cutting-edge areas of research in electronics today.

Researchers working in the Laboratory of Nanoscale Electronics and Structures (LANES), which is run by Professor Andras Kis, were able to quantify these quantum properties for a category of two-dimensional semiconductors called transition metal dichalcogenides, or TMDCs. Their research projects, which were published recently in ACS Nano and today in Nature Communications, confirm that materials like graphene (C), molybdenite (MoS2) and tungsten diselenide (WSe2) offer, either alone or by combining some of their characteristics, new perspectives for the field of electronics – perspectives that could ultimately lead to smaller chips that generate less heat.

“With the methods we’ve recently developed, we’ve shown that it is possible to access the spin in these TMDC materials, quantify it and use it to introduce new functionalities,” says Kis.

This all takes place at an extremely small scale. In order to access these quantum properties, the researchers must work with high quality materials. “If we want to examine certain characteristics of electrons, including their energy, we need to be able to watch them move over relatively long distances without there being too much dispersion or disruption,” explains Kis.

In the form of waves

The researchers’ method allows them to obtain samples of sufficient quality both to observe how electrons move around in the form of waves and to quantify their energy.

But the LANES team was also able to access another quantum property. Spins of electrons and holes in this type of a 2D semiconductor can be in one of two states, which are conventionally described as being oriented upward – spin up – or downward – spin down. Their energy will be slightly different in each of these two states. That’s called spin splitting, and the EPFL researchers have measured it for the first time for electrons in TMDC materials. In the second publication, the researchers wrote about how they used the spin splitting in a TMDC in order to introduce polarized spin currents in graphene without using a magnetic field.

These discoveries are a step forward for the emerging field of spintronics and make it increasingly likely that a different property of charge carriers – i.e. spin, in addition to the electrical charge – will play a role in tomorrow’s electronic devices.

A new technology enables dramatically lower thermal budget capability that is enabling to thermal processes like epitaxy, CVD and diffusion, without any semiconductor material consumption.

BY ROBERT PAGLIARO, RP Innovative Engineering Solutions, LLC, Mesa, AZ

As semiconductor based electronic devices have become smaller, faster, smarter, 3-dimensional, and multi-functional the methods and materials required to fabricate them demand novel approaches to be developed and implemented in the device manufacturing facilities. Amongst the most challenging requirements are the need to lower the thermal budgets of the front end thermal processes and to minimize the semiconductor material consumption that comes with the conventional oxidizing (hydrogen peroxide and ozone based chemistries) wet cleaning processes chemistries such as APM, HPM, SPM and SOM.

A novel wet surface preparation method that removes existing surface contamination and native oxide from semiconductor surfaces and then passivates them with a pristine and stable hydrogen passivated surface has been developed and commercialized by APET Co, Ltd. in a system called the TeraDox. This patented technology enables dramatically lower thermal budget capability that is enabling to thermal processes like epitaxy, CVD and diffusion, without any semiconductor material consumption.

The TeraDox system is an enhanced version of the APET FRD (HF etching, Rinse and Dry). The name TeraDox implies the ability to provide a process chemistry with < 1 ppb impurities, particularly dissolved oxygen, which allows for producing pristine and stable H-passivated semiconductor surfaces. Dilute HF and HCl (dHF and dHCl) are the etching chemistries used for removing the native and chemical oxides from Si, SiGe and Ge surfaces. The TeraDox system has a single vessel wet processor and a wafer transfer/drying hood that allows for a segue between the load, chemical fill, etch, insitu-rinse, dry and unload steps of the process sequence, while keeping the process chemistry and the wafers in a continuous ambient of ultra- pure N2. This equipment and process design eliminate the exposure of the wafers to air and minimizes gas perme- ation throughout the entire oxide removal and H-passiv- ation process sequence. These are all critical elements to achieving the best surface quality results. While there are a variety of important parameters towards achieving a pristine and stable H-passivated surface one of the most enabling ingredients to the APET TeraDox process and equipment IP is the PPT level degassing capability for the UPW and aqueous chemicals used in the H-passivation process. The unique UPW and chemical degassing apparatus require an optimized hardware configuration with membrane contactors and facilities used for the vacuum + UHP N2 sweep gas to achieve a DO degassing efficiency > 99.999%. This ultra-high degassing efficiency allows for a Dissolved Oxygen (DO) concen- tration capability of < 100 ppt.

It has been well proven and documented by multiple world-renowned surface scientists [1,2,3] since the late 1980s that the level of dissolved oxygen (DO), as well as other dissolved impurities (such as CO2, TOC, silica and N2), has a direct impact on the efficiency of H-passivation and the native oxide (initial and changing thickness vs. queue time) that follows the removal of native and chemical oxides from semicon- ductor surfaces. Queue time (Q-time) is the amount of time that the H-passivated wafer are exposed to air before being placed in an inert environment for the subsequent process step (epi, poly silicon, metal, ion implantation etc.). It can be seen in FIGURE 1 how native oxide regrowth occurs after HF treatment in air and UPW vs. exposure time [1].

Screen Shot 2017-12-06 at 12.26.01 PM

A similar DO vs. surface oxide and carbon relationship is also verified using encapsulated SIMS. This method uses dynamic SIMS to measure the amount of O, C that are trapped at the epi layer/silicon wafer interface. This has been a widely used characterization method to assess a pre-low temperature epi surface prepa- ration process’ hydrogen surface passivation quality since the early 90s. The typical epi cap is ~80-150nm and is deposited using a 650°C SiH4 source deposition process. The objective is to be able to minimize the thermal budget of the pre-deposition bake step which is required to remove any surface oxides and organics to allow perfect epitaxial deposition with no contami- nants or defects at the interface.

FIGURE 2 demonstrates how the encapsulated SIMS interface O (areal oxide density, AOD) using a 650°C SiH4 no bake Si deposition process is strongly dependent on the DO concentration. Three samples are depicted with different surface preparation conditions, a reference wafer with no surface preparation, a wafer dHF wet processedwith the UPW DO ~ 1ppb, and a wafer dHF wet processed with the DO ~0.1 ppb.

Screen Shot 2017-12-06 at 12.26.31 PM

It can be seen in FIGURE 3 how applying a 700C/80T/60s bake before a 650C Si deposition process with the UPW DO at 0.1ppb yields non-detectable O and C. This SIMS data info is relatively old (2010) but is still good for reference. The current APET TeraDox wet process capability can provide non-detectable O and C without a bake before the 650°C Si deposition process.

Screen Shot 2017-12-06 at 12.26.46 PM

As mentioned earlier, undesirable native oxide thickness increases with queue time on H-passivated Si, SiGe and Ge surfaces. So, it is important to minimize the Q-time between the H-passivation process and the subsequent process step, but the quality and stability of the H-passivation does need to accommodate practical queue times in a manufacturing environment. The H-passivation from the APET TeraDox process has proven to be stable enough for up to at least 8-hour Q-times for most low temperature process applications, which makes it suitable for most semiconductor device manufacturing facilities.

Aside from the low surface oxygen benefit from having ultra-low DO in this process there are other very important benefits to this as well. Having ultra-low DO prevents water marks, microroughness (faceting), bacterial contamination and material consumption. If there is no DO in the UPW or the etching chemistry then there is no competing mechanism to simultaneously oxidize and etch the semiconductor material during the oxide etch and insitu-rinse steps. If the surface is being oxidized/etched then orientation selective faceting will occur. Faceting leads to gener- ation a mix of mono-, di- and tri- hydride terminations on the different orientations of the semiconductor surface. An example is silicon (100), which if it is kept atomically smooth after the oxide is removed by HF, the surface will be dominated by di-hydride terminations. If the surface is faceted it will contain lower energy mono-hydride terminations. Higher energy hydride bonds lead to better surface stability while the lower energy hydride bonds make the surface less stable and will re-oxidize faster with Q-time.

So in general, the pristineness and the atomic smoothness of the semiconductor surface are what dictates the quality and stability of the H-passivating surface preparation process.

While the TeraDox process performance has continued to improve with the new innovations, the capabilities have surpassed the detection limits of conven- tional measurement methods like encapsulated SIMS characterization. Encapsulated SIMS also has a lot of drawbacks and limitations which make it an impractical process monitoring method in manufacturing facil- ities. The need to have a more sensitive measurement method that can measure “as processed” surfaces in a fast, real time and non-destructive manner had become an urgent requirement.

There are a variety of very good electrical and optical measurement methods that have been in use for many years, but most of them do not provide surface specific information directly. Surface parameters such as surface recombination velocity and lifetime (SRV and Ts) can be calculated relatively accurately using multiple step procedures by measurement methods such as uPCD, QSS-PC, PL and SPV. SRV (surface recombination velocity) and Ts (surface recombination lifetime) are extremely sensitive to surface contamination such as C, O metals and dopants as well as micro- roughness. This diverse sensitivity make it ideal for assessing surface preparation methods.

Until recently, only one measurement technique has been found that can measure the SRV and Teff (effective lifetime) of the surface directly and quickly on as processed H-passivated wafers. While doing a lot of research for the ideal measurement method to pair with the APET TeraDox H-passivation process, it was discovered that an enhanced version of the CADIPT department at the University of Toronto’s PCR-LIC technology, called Quantitative Lock-in Carrierog- raphy and Imaging (Q-LIC), could have the unique and enabling capabilities needed for this application. After completing an array of screening and optimization testing over the course of 8 months, the results have validated Q-LIC as an ideal measurement method for “as processed” H-passivated surfaces. In FIGURE 4, the plot demonstrates the SRV vs Q-time for four different wet cleans and an unprocessed control. The data shows strong evidence of the differentiation between different H-passivation methods (process and equipment), the level of DO in the wet process chemistry, and the dynamically changing surface state over time.

FIGURE 4. Q-LIC SRV measurements vs Q-time for four different HF last wet processes.

FIGURE 4. Q-LIC SRV measurements vs Q-time for four different HF last wet processes.

APET currently has five patents, related to this technology, integrated on the commercially available TeraDox wet process equipment, four of which include the use of vacuum/N2 sweep degassing with membrane contactors for both the UPW and chemical degassing.

The UPW degassing is done in a separate stand-alone module (called the APET Dox unit) that treats up to 60 lpm of UPW before going to the main unit. All Dox units are guaranteed to have DO < 1 ppb, but all of the units in use to date achieve < 200 ppt. The most recently installed Dox unit system has a base DO level of ~30-40 ppt. Aside from the importance of PPT level degassing of the UPW much attention has also been given towards the design and materials used in the entire TeraDox system to prevent gas permeation into the UPW supply and the process chemistry to achieve optimum H-passivation. The most recent TeraDox related patent that was issued to APET was for chemical degassing. The degassing of the HF and HCl are typically overlooked in this application. Typically, HF comes in ~48% and HCl in ~37% concentrations with the balance of these supplied mixtures is in DO saturated water. So even diluted etching chemistries of up to 400 (UPW) :1 (chemical) ratios will typically still produce a composite DO of > 3ppb in the process vessel, even if the UPW supply is degassed to 0 ppt. Having the unique chemical degassing capability to < 1ppb DO significant improves the overall performance of the H-passivation process. The chemical degassing apparatus is integrated into the HF and HCl chemical delivery lines inside the TeraDox system’s main unit.

In summary, APET has developed and commercialized a unique and enabling wet surface preparation technology, the TeraDox process and equipment, that can produce pristine and stable hydrogen passivated semiconductor surfaces. While there are several critical factors and innovations that enable the TeraDox’s unique process performance capabilities, the fully integrated “dry in/dry out” system design and the unique PPT level degassing of the process chemistries are the most facili- tating features on the TeraDox system.

Acknowledgement

A special thanks to Dr. Andreas Mandelis and his staff at the University of Toronto for their support in optimizing their Q-LIC system to provide data for this paper as well as demonstrating a suitable measurement method for the “as processed” H-passivation application.

References

1. M. Morita et al, J. Appl. Phys. 88 (3), 1 (1990)
2. A. Philipossian, J. Electrochem. Soc. 139 No. 10, 2956 (1992)
3. F. H. Li, M. K. Balazs, and S. Anderson, J. Electrochem. Soc. 152,
G669 (2005)

The Semiconductor Industry Association (SIA) today announced worldwide sales of semiconductors reached $37.1 billion for the month of October 2017, an increase of 21.9 percent from the October 2016 total of $30.4 billion and 3.2 percent more than last month’s total of $36.0 billion. October marked the global industry’s largest-ever monthly sales total. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average. Additionally, the latest WSTS industry forecast was revised upward and now projects annual global market growth of 20.6 percent in 2017 and 7.0 percent in 2018.

“The global semiconductor market continued to grow impressively in October, with sales surpassing the industry’s highest-ever monthly total and moving closer to topping $400 billion for 2017,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Market growth continues to be driven in part by high demand for memory products, but combined sales of all other semiconductor products were up substantially as well, showing the breadth of the market’s strength this year.”

Regionally, year-to-year sales increased in the Americas (40.9 percent), Europe (19.5 percent), China (19.1 percent), Asia Pacific/All Other (16.3 percent), and Japan (10.7 percent). Compared with last month, sales were up more modestly across all regions: the Americas (6.8 percent), China (2.6 percent), Europe (2.6 percent), Japan (1.8 percent), and Asia Pacific/All Other (1.5 percent).

Additionally, SIA today endorsed the WSTS Autumn 2017 global semiconductor sales forecast, which projects the industry’s worldwide sales will be $408.7 billion in 2017. This would mark the industry’s highest-ever annual sales, its first time topping $400 billion, and a 20.6 percent increase from the 2016 sales total. WSTS projects double-digit year-to-year increases across all regional markets for 2017: the Americas (31.9 percent), Asia Pacific (18.9 percent), Europe (16.3 percent), and Japan (12.6 percent). Beyond 2017, growth in the semiconductor market is expected to moderate across all regions. WSTS tabulates its semi-annual industry forecast by convening an extensive group of global semiconductor companies that provide accurate and timely indicators of semiconductor trends.

To find out how to purchase the WSTS Subscription Package, which includes comprehensive monthly semiconductor sales data and detailed WSTS Forecasts, please visit http://www.semiconductors.org/industry_statistics/wsts_subscription_package/. For detailed data on the global and U.S. semiconductor industry and market, consider purchasing the 2017 SIA Databook: https://www.semiconductors.org/forms/sia_databook/.

Oct 2017

Billions

Month-to-Month Sales                              

Market

Last Month

Current Month

% Change

Americas

7.99

8.54

6.8%

Europe

3.28

3.37

2.6%

Japan

3.14

3.20

1.8%

China

11.36

11.65

2.6%

Asia Pacific/All Other

10.18

10.33

1.5%

Total

35.95

37.09

3.2%

Year-to-Year Sales                         

Market

Last Year

Current Month

% Change

Americas

6.06

8.54

40.9%

Europe

2.82

3.37

19.5%

Japan

2.89

3.20

10.7%

China

9.78

11.65

19.1%

Asia Pacific/All Other

8.88

10.33

16.3%

Total

30.43

37.09

21.9%

Three-Month-Moving Average Sales

Market

May/Jun/Jul

Aug/Sep/Oct

% Change

Americas

6.94

8.54

23.0%

Europe

3.20

3.37

5.1%

Japan

3.04

3.20

5.2%

China

10.68

11.65

9.1%

Asia Pacific/All Other

9.77

10.33

5.8%

Total

33.63

37.09

10.3%

A new illumination technology compares favorably to conventional bright field illumination.

BY GURVINDER SINGH, Director, Product Management, Rudolph Technologies, Inc., Wilmington, MA

A new optical technique can reveal defects and contaminants that escape conventional inspection technologies in many advanced packaging applications. As wafer level packaging (WLP), and especially fan-out wafer and panel level packaging (FOWLP/FOPLP), gains broader accep- tance, certain classes of defects that are characteristic of these processes present significant challenges to standard optical inspection tools. A new optical technology demonstrates increased sensitivity to transparent defects, such as residual dielectric films and photoresist, which are only marginally visible with conventional tools. At the same time, it is less sensitive to nuisance defects, such as those caused by the varying contrast and texture of grains in metal films, that should correctly be ignored.

Challenges in advanced packaging applications

Advanced packaging processes often involve the use of front-end-like technologies in back-end applications. Fan-out packaging is no exception, and, not surpris- ingly, it is following a similar development path, with increasing circuit complexity accompanied by shrinking circuit geometries. Redistribution layer (RDL) line widths, which were around 20μm in early implementations, will soon reach 2μm and are unlikely to stop there. Just as front-end processes placed increasing emphasis on enhanced process monitoring and control, advanced packaging processes will be forced to include more and better inspection and metrology capability at critical steps to maintain control and improve yields.

Advanced packaging processes, such as fan-out, face unique challenges that, for inspection systems, result in overcounting nuisance defects and undercounting yield-robbing critical defects. These advanced packaging techniques make extensive use of metal and organic polymers. Layers of metal are used to define conductive paths and organic polymer dielectric materials are used to provide insulation between conductors and planar surfaces between the layers. Dark field and bright field inspection results often include tens of thousands of nuisance defects. These occur because the inspection algorithms are designed to find random aberrations in highly repeatable patterns and the variable grain patterns of metal conductors appear as defects when are not. If not excluded, their large numbers can quickly overwhelm the real defects. Metal grain features can be as large as 50μm, much larger than RDL lines, which are currently as small as 2μm, and likely to reach 1μm in the near future.

Another class of defects that has proven difficult for conventional optical inspection techniques is caused by the presence of organic residues left after etching and descumming operations. They are hard to find because these materials tend to be transparent at visible wavelengths, yielding little signal in bright field and dark field inspection. They can be especially troublesome when they occur on contacts such as bumps and pillars. The new illumination method effectively eliminates nuisance noise from metal surface textures and enhances signal strength from organic defects.

ClearfindTM technology

The results presented here were all acquired using a FireflyTM inspection system (Rudolph Technologies) that incorpo- rates the new Clearfind (CF) illumination technology1. The new method takes advantage of the fact that many organic polymers exhibit distinctive optical properties that are not present in metals, silicon or other common inorganic materials used in semiconductor manufacturing. These properties tend to be unique to organic molecules displaying a high degree of conjugation, such as polycyclic aromatic hydrocarbons, and in linear or branched chain organic polymers with multiple regularly interspersed pi-bonds. This phenomenon results in the generation of a readily detectable, high color-contrast signal when the feature is appropriately illuminated against a metallic or other inorganic surface. The emission tends to be anisotropic and therefore less sensitive to surface topography that could potentially direct most ordinary bright field or dark field reflected light away from the detector. This results in increased sensitivity to organic residues and reduced sensitivity to interference from surrounding features. The method has the additional advantage of being relatively insensitive to signal variations caused by metal grains. FIGURE 1 presents a simplified illustration comparing the new technology to traditional white light inspection.

Screen Shot 2017-12-05 at 1.12.48 PM Screen Shot 2017-12-05 at 1.12.56 PM

The light source for the new technology is laser based, rather than the broadband source typically used in white light inspection systems. Thus, the light output is more stable in terms of both spectral range and output power. Autofocusing of the samples is accomplished using a patented high speed, near infrared-based laser triangulation system that maintains a constant distance between the imaging optics and the area being scanned. Images are acquired at high speed with a high-resolution camera. The result images compared in this article using bright field, dark field and CF technology were all acquired on the same inspection platform using different illumination techniques.

Through Silicon Via (TSV)

The sample is a 300mm silicon wafer with revealed TSV pillars2. TSV nail diameter is about 8μm and the distance between TSVs is about 56μm. The TSVs are on the backside of the wafer and the front side of the wafer is attached to a carrier.

In FIGURE 2a, the top shows a bright field image of two TSVs. The TSV on the left, circled in red, is covered with unetched organic residue and the TSV on the right, circled in green, is completely exposed. In the bright field image both TSVs look good and the residue is not visible. The images at the bottom left of figure 2 were acquired with CF technology and show the same TSVs. The TSV on the left, circled in red, has a bright blob while the one on the right, circled in green, is completely dark. The organic residue remaining on the left TSV now emits a readily detectable signal.

FIGURE 2b shows the inspection result from the full TSV wafer. The dots on the wafer map represent defect locations. There is a heavy concentration of organic residue on TSVs on the right side of the wafer. Metal pads approximately 35μm in diameter will be placed on top of the TSVs. Any organic residue between the TSV and the pad can cause deplanarization, which may result in connectivity issues when the die is stacked together. In addition, organic residue can increase the resistance of the contact when the die is stacked. If the defects are found before the next process step the wafer can be reworked.

Screen Shot 2017-12-05 at 1.13.03 PM

Under Bump Metal (UBM)

The sample is a 300mm wafer with RDL and under bump metallization (UBM). The UBM pads are about 50μm wide. In FIGURE 3a, the bright field image of two UBM pads shows the left pad is completely exposed and the right pad is covered with unetched organic film. However, the film is transparent and both pads look good in this image. Note the random metal texture visible in the bright field image, which adds noise and makes sensitive inspection for small defects more difficult. The image at lower left, acquired with CF technology, shows the same pads. The left pad, with no residue, appears black. The right pad, covered by residue, is significantly brighter. Also note that the metal texture seen in the bright field image with absent in CF illumination, permitting sensitive inspection for defects down to the pixel level.

FIGURE 3b shows a map of the full wafer where there is a heavy concentration of defects on UBM pads near the edge of the wafer. As in the TSV example, residue remaining on the UBM pads can cause increased resistance or loss of connectivity to a bump deposited on the pad. Bumps deposited on the residue are higher than normal bumps, leading to loss of coplanarity and connectivity issues. If the problem is found before starting the bump process, the wafer can be reworked and the residues removed.

Screen Shot 2017-12-05 at 1.13.10 PM

Redistribution Layer (RDL)

The sample is a 300mm molding compound wafer for fan-out packaging. FIGURE 4a shows a bright field image that includes a UBM pad and several RDL lines. The middle image shows the same area viewed with the new illumination technology. In the bright field image, the metal of the UBM pad and the RDL lines is very similar to the underlying metal visible through an interposed transparent film. The texture and graininess of the metals add noise to the image, increasing the difficulty of detecting small defects. Inspection with bright field illumination resulted in high nuisance defect counts without finding real process issues on the wafer. In FIGURE 4b, the top surface metal features, RDL and UBM, stand out against the background of the transparent film, while the underlying metal features are barely visible. FIGURE 4c shows a full wafer map acquired using CF technology and reveals a rectangular pattern that corresponds to the reticle of the lithography tool. The rectangular pattern was not visible in the bright field wafer map.

Screen Shot 2017-12-05 at 1.13.19 PM

FIGURE 5 shows additional RDL inspection results on the same wafer. CF technology revealed thinner lines toward the lower left corner of the reticle pattern. Ultimately, it was determined that these thinner lines were caused by a defect in the condenser lens of the lithography tool. The improved contrast between the first layer metal features in the underlying organic film, and the reduced noise, permitted more accurate and sensitive measurements using the new illumination technology. A bright field inspection of 20 wafers containing the same defect did not detect any thinner lines.

Screen Shot 2017-12-05 at 1.13.25 PM

Photoresist

The sample is a 300mm patterned silicon wafer from a large memory manufacturer3. It contains die approximately 11.7mm x 7.6mm in size, and containing arrays of about 9,000 metal pillars, each pillar approximately 22μm in diameter. The customer was interested to know if the new illumination technology would find defects not found by bright field inspection. FIGURE 6a shows a wafer map overlaying bright field defects (blue triangles) and CF defects (green triangles). In both cases the defects appear to be randomly distributed and not clustered. As depicted by the bar chart in FIGURE 6b, bright field illumination found 2,279 defects compared to 289 defects found by CF technology. Most interestingly, only 32 of the defects found by CF technology were also found with bright field inspection. 257 defects would have been missed by bright field inspection. The bar chart (FIGURE 6c) shows the size distribution of defects discovered by both techniques. Bright field inspection found a very large number of small defects (less than 5μm) and more defects larger than 25μm. Defects found by the CF technology were between 5-25μm in size.

Screen Shot 2017-12-05 at 1.13.34 PM

FIGURE 7 compares CF technology results (top) and bright field results (bottom). Each vertical pair shows a defect missed by bright field inspection and detected by CF technology. The enhanced brightness and circular shape of the defects detected by the new method strongly imply that they are associated with polymer residues. The enhanced brightness of the defects against the very black background is a unique and valuable feature of CF technology. Overall, these results demonstrate the value of supplementing bright field inspection with CF technology. All of the defects found by CF technology were of sufficient size to impact yield.

Screen Shot 2017-12-05 at 1.13.44 PM

Conclusion

Results shown here demonstrate the benefits of imaging with the new CF illumination technology when compared to conventional bright field illumination. The new technology allows detection of transparent organic residues that are not visible with bright field illumination.

It was also shown to detect types and sizes of defects that were not detected by bright field inspection. Equally important, its ability to reduce noise caused by metal texture and graininess significantly improves its sensitivity to small defects on metal features and dramatically reduces the detection of nuisance defects.

References

1. Gurvinder Singh, et al, “Advanced packaging lithography and inspection solution for next generation FOWLP-FOPLP processing”, IEEE Xplore, October 2016.
2. Woo Young Han, et al, “Inspection challenges in wafer level packaging”, International Wafer Level Packaging Conference, October 2017
3. Jonathan Cohen, et al, “Photoresist residue detection in advanced packaging”, International Wafer Level Packaging Conference, October 2017

A research group in Japan announced that it has quantified for the first time the impacts of three electron-scattering mechanisms for determining the resistance of silicon carbide (SiC) power semiconductor devices in power semiconductor modules. The university-industry team consisting of researchers from the University of Tokyo and Mitsubishi Electric Corporation has found that resistance under the SiC interface can be reduced by two-thirds by suppressing electron scattering by the charges, a discovery that is expected to help reduce energy consumption in electric power equipment by lowering the resistance of SiC power semiconductors.

Electron scattering under the silicon carbide (SiC) interface is limited by three factors: roughness of the SiC interface, charges under the SiC interface and atomic vibration. Credit: 2017 Mitsubishi Electric Corporation.

Electron scattering under the silicon carbide (SiC) interface is limited by three factors: roughness of the SiC interface, charges under the SiC interface and atomic vibration. Credit: 2017 Mitsubishi Electric Corporation.

Electric power equipment used in home electronics, industrial machinery, trains and other apparatuses requires a combination of maximized efficiency and minimized size. Mitsubishi Electric, a leading Japanese electronics and electrical equipment manufacturer, is accelerating use of SiC devices for power semiconductor modules, which are key components in electric power equipment. SiC power devices offer lower resistance than conventional silicon power devices, so to further lower their resistance it is important to understand correctly the characteristics of the resistance under the SiC interface.

“Until now, however, it had been difficult to measure separately resistance-limiting factors that determine electron scattering,” says Satoshi Yamakawa, senior manager of the SiC Device Development Center at Mitsubishi Electric’s Advanced Technology R&D Center.

Electron scattering focusing on atomic vibration was measured using technology from the University of Tokyo. The impact that charges and atomic vibration have on electron scattering under the SiC interface was revealed to be dominant in Mitsubishi Electric’s analyses of fabricated devices. Although it has been recognized that electron scattering under the SiC interface is limited by three factors, namely, the roughness of the SiC interface, the charges under the SiC interface and the atomic vibration, the contribution of each factor had been unclear. A planar-type SiC metal-oxide-semiconductor field-effect transistor (SiC-MOSFET), in which electrons conduct away from the SiC interface to around several nanometers, was fabricated to confirm the impact of the charges.

“We were able to confirm at an unprecedented level that the roughness of the SiC interface has little effect while charges under the SiC interface and atomic vibration are dominant factors,” says Koji Kita, an associate professor at the University of Tokyo’s Graduate School of Engineering and one of scientists leading the research.

Using an earlier planar-type SiC-MOSFET device for comparison, resistance was reduced by two-thirds owing to suppression of electron scattering, which was achieved by making the electrons conduct away from the charges under the SiC interface. The previous planar-type device has the same interface structure as that of the SiC-MOSFET fabricated by the electronics maker.

For the test, Mitsubishi Electric handled the design, fabrication and analysis of the resistance-limiting factors and the University of Tokyo handled the measurement of electron-scattering factors.

“Going forward, we will continue refining the design and specifications of our SiC MOSFET to further lower the resistance of SiC power devices,” says Mitsubishi Electric’s Yamakawa.

This research achievement was announced at the 63rd International Electron Devices Meeting (IEDM) in San Francisco, California, on December 4, 2017.

SEMI, the global industry association representing the electronics manufacturing supply chain, today reported that worldwide semiconductor manufacturing equipment billings reached US$14.3 billion for the third quarter of 2017.

Quarterly billings of US$14.3 billion set an all-time record for quarterly billings, exceeding the record level set in the second quarter of this year. Billings for the most recent quarter are 2 percent higher than the second quarter of 2017 and 30 percent higher than the same quarter a year ago. Sequential regional growth was mixed for the most recent quarter with the strongest growth in Europe. Korea maintained the largest market for semiconductor equipment for the year, followed by Taiwan and China. The data are gathered jointly with the Semiconductor Equipment Association of Japan (SEAJ) from over 95 global equipment companies that provide data on a monthly basis.

Quarterly Billings Data by Region in Billions of U.S. Dollars
Quarter-Over-Quarter Growth and Year-Over-Year Rates by Region
3Q2017
2Q2017
3Q2016
3Q2017/2Q2017
3Q2017/3Q2016
Korea
4.99
4.79
2.09
4%
139%
Taiwan
2.37
2.76
3.46
-14%
-32%
China
1.93
2.51
1.43
-23%
35%
Japan
1.73
1.55
1.29
11%
34%
North America
1.50
1.23
1.05
22%
43%
Europe
1.06
0.66
0.53
61%
100%
Rest of World
0.74
0.62
1.13
20%
-34%
Total
14.33
14.11
10.98
2%
30%

Source: SEMI (www.semi.org) and SEAJ (http://www.seaj.or.jp)

The Equipment Market Data Subscription (EMDS) from SEMI provides comprehensive market data for the global semiconductor equipment market. A subscription includes three reports: the monthly SEMI Billings Report, which offers a perspective of the trends in the equipment market; the monthly Worldwide Semiconductor Equipment Market Statistics (WWSEMS), a detailed report of semiconductor equipment billings for seven regions and 24 market segments; and the SEMI Semiconductor Equipment Forecast, which provides an outlook for the semiconductor equipment market. More information is also available online: www.semi.org/en/MarketInfo/EquipmentMarket.

By Walt Custer, Custer Consulting

SEMICON Europa 2017 and productronica were co-located November 14 to 17 at Messe Munchen in Munich, Germany. Attendance was very good and the mood was upbeat.

The third quarter of this year has seen broad growth both globally and also for the European electronic supply chain.

Chart 1 shows 3Q’17/3Q’16 growth by electronic sector for the world. SEMI and PCB process equipment and semiconductors stand out but almost all key sectors expanded.

Custer-Chart-1-Global-Elec-

Chart 2 shows third quarter growth for Europe.  SEMI equipment leads but the third quarter Eurozone expansion was broad based.

Custer-Chart-2-EUropean-Ele

At productronica, Custer Consulting presented at the “Business Outlook for the Global Electronic Supply Chain” event (with emphasis on Europe).  For a copy of Walt’s charts, please email [email protected].

GLOBALFOUNDRIES and Ayar Labs, a startup bringing optical input/output (I/O) to silicon chips, today announced a strategic collaboration to co-develop and commercialize differentiated silicon photonic technology solutions. The companies will develop and manufacture Ayar’s novel CMOS optical I/O technology, using GF’s 45nm CMOS fabrication process, to deliver an alternative to copper I/O that offers up to 10x higher bandwidth and up to 5x lower power. This cost-effective solution is integrated in-package with customer ASICs as a multi-chip module, and improves data speed and energy efficiency in cloud servers, datacenters and supercomputers. As part of the agreement, GF has also invested an undisclosed amount in Ayar Labs.

Modern data centers and cloud applications require high-performance, power-hungry chips to process and analyze huge volumes of data in real time. Growth in chip I/O capabilities has not matched exponential increases in computing power, because of physical limitations in electrical data transmission. Optical I/O, which leverages optical components on the CMOS die to transmit data at rapid speeds, will be a key enabler to overcoming the limitations of today’s data center interconnects. In addition, Ayar’s technology reduces power consumption at both the network and processor level.

“GF has demonstrated true technology leadership in recognizing optical I/O as the inevitable next step as we move into a More than Moore world,” said Alex Wright-Gladstein, CEO at Ayar Labs. “This collaboration between Ayar and GF could improve chip communication bandwidth by more than an order of magnitude and at lower power, and is a validation of Ayar’s viability in the current semiconductor ecosystem. This collaboration will unlock a larger market opportunity, expanding both our and GF’s customer base. We look forward to working with GF to help solve the interconnect problems of today’s chips and create greater value for our customers than if both companies worked independently.”

“The Ayar Labs team has been designing cutting-edge silicon photonics components on GF’s technology for the past eight years and has achieved exceptional results,” said Mike Cadigan, senior vice president of global sales and business development at GF. “Our strategic collaboration builds on our relationship, leveraging GF’s silicon photonics IP portfolio and our world-class manufacturing expertise to enable faster and more energy-efficient computing systems for data centers.”

The collaboration brings together Ayar Labs’ patented IP in optical technology with GF’s best-in-class expertise in silicon photonics to co-develop optical solutions that will be fabricated using GF’s process technology. The availability of this technology, including certain Design IP cores, will enable internet service providers, system vendors and communication systems to push data capacity to 10 Tera bits per second (Tbps) and beyond, while maintaining the low energy and cost of optical-based interconnects.

Electronics manufacturing executives will attend Europe’s SEMI Industry Strategy Symposium (ISS Europe) in Dublin, Ireland on 4-6 March. Hosted by SEMI Europe, the ISS Europe 2018 is the three-day flagship business event that brings together leading analysts, researchers, economists, and technologists for critical insights on the forces shaping the electronics manufacturing supply chain.

While having core strengths of its own, Europe is part of a global innovation and supply chain and European organisations need to find new ways to maximise competitive advantage. “Organisations operating in Europe need to find the most effective way to innovate, manufacture and profit by finding their place in the global supply chain. During the symposium, best class discussions will address Europe’s strategic, economic and social needs“ said Laith Altimime, president, SEMI Europe.

A wide range of top European companies, research institutes and public institutions will debate the best ways to compete globally, along with discussions on successful manufacturing in Europe and mechanisms to support innovation:

Speaker Line-up:

  • David Bloss, VP, Technology Manufacturing Group, Intel
  • Holger Blume, Professor, University of Hanover
  • Jean-Frederic Clerc, Deputy CEO and CTO, CEA Tech
  • Kevin Cooney, Senior VP and Managing Director, Global CIO, Xilinx EMEA
  • Jean-Christophe Eloy, CEO, Yole Développement
  • Ann-Charlotte Johannesson, CEO, CEI-Europe AB
  • Cheryl Miller, Founder/Executive Director, Digital Leadership Institute
  • Mick A Morris, Director AMBER Research Centre, Professor, Trinity College Dublin
  • Alain Mutricy, Senior VP Product Management, GLOBALFOUNDRIES
  • James O’Riordan, CTO, S3
  • David Sneddo, Director of Large Customer Sales for Central Europe, Google
  • Florien van der Windt, Cluster Manager Smart Mobility, Dutch Ministry of Infrastructure & Environment
  • Hanns Windele, Vice President, Europe and India, Mentor, a Siemens Business

Highlight of this year, the Panel Discussion “Critical Strategies to Grow Europe in the Global Supply Chain”. SEMI will also offer great networking opportunities such as an opening networking reception and, a gala dinner during which SEMI will announce the 2017 European Award winner.

Join Europe’s strategic thinkers and business drivers at ISS Europe 2018 in Dublin, Ireland from March 4-6, 2018!

For further information about our programs, please visit www.semi.org/eu/iss-europe-2018 or contact Christina Fritsch, Senior Manager, Program and Events. To sponsor the event please contact: SEMI Europe, Denada Hodaj, Manager Sales Europe (email: [email protected]). Register before January 31 for a discount. Fee includes conference and presentations access, reception, lunches and dinner. To register online, please visit: https://iss2018.besl-eventservice.de/front/index.php