Category Archives: Semiconductors

Dialog Semiconductor plc (XETRA:DLG), a provider of highly integrated power management, AC/DC power conversion, charging, and low power connectivity technology, announced today that it has completed the acquisition of privately-held Silego Technology Inc. (“Silego”), a provider of Configurable Mixed-signal ICs (CMICs).

Headquartered in Santa Clara, California with approximately 235 employees worldwide, Silego is the pioneer and market leader in CMICs that integrate multiple analog, logic, and discrete component functionality into a single chip. Silego’s product portfolio will strengthen Dialog’s presence in markets including IoT, computing and automotive.

“The acquisition of Silego brings a highly complementary technology to Dialog. What Silego has developed is truly unique – a mixed-signal platform which customers can configure to their design requirements on the fly, drastically reducing the time to bring their products to market,” said Jalal Bagherli, CEO of Dialog. “With global scale and customer access, Dialog is the right platform to further accelerate industry wide CMIC adoption. Furthermore, we gain an exceptional group of talented people that will fit well with Dialog’s culture. Together, we will significantly increase the value we can bring to our customers by creating a better-positioned and more-diversified mixed signal offering.”

“We believe Dialog will be a great environment for the Silego team to grow as part of a much larger company serving global customers,” stated John Teegen, CEO of Silego Technology. “Our proprietary and configurable approach has allowed Silego to establish leadership while creating a new market. By leveraging Dialog’s technology and capabilities, I am confident we can further drive adoption of CMICs.”

Silego anticipates achieving over $80 million of revenue in 2017 and double-digit growth in 2018. The transaction is expected to be accretive to Dialog’s underlying EPS for full calendar year 2018 and accretive to Dialog’s gross margin.

This article first appeared on SemiMD.com.

With mask costs rising and the need for flexibility growing, companies are beginning to adopt embedded field programmable gate arrays in their SoC designs.

BY DAVE LAMMERS, Contributing Editor

It was back in 1985 that Ross Freeman invented the FPGA, gaining a fundamental patent (#4,870,302) that promised engineers the ability to use “open gates” that could be “programmed to add new functionality, adapt to changing standards or specifications, and make last-minute design changes.”

Freeman, a co-founder of Xilinx, died in 1989, too soon to see the emerging development of embedded field programmable logic arrays (eFPGAs). The IP cores offer system-on-chip (SoC) designers an ability to create hardware accelerators and to support changing algorithms. Proponents claim the approach provides advantages to artificial intelligence (AI) processors, automotive ICs, and the SoCs used in data centers, software-defined networks, 5G wireless, encryption, and other emerging applications.

With mask costs escalating rapidly, eFPGAs offer a way to customize SoCs without spinning new silicon. While eFPGAs cannot compete with custom silicon in terms of die area, the flexibility, speed, and power consumption are proving attractive.

Semico Research analyst Rich Wawrzyniak, who tracks the SoC market, said he considers eFPGAs to be “a very profound development in the industry, a capability that is going to get used in lots of places that we haven’t even imagined yet.”

While Altera, now owned by Intel, and Xilinx, have not ventured publicly into the embedded space, Wawrzyniak noted that a lively bunch of competitors are moving to offer eFPGA intellectual property (IP) cores.

Multiple competitors enter eFPGA field

Achronix Semiconductor (Santa Clara, Calif.) has branched out from its early base in stand-alone FPGAs, using Intel’s 22nm process, to an IP model. It is emphasizing its embeddable Speedcore eFPGAs that can be added to SoCs using TSMC’s 16FF foundry process. 7nm IP cores are under development.

Efinix Inc. (Santa Clara recently rolled out its Efinix Programmable Accelerator (EPA) technology.

Efinix (efinixinc.com) claims that its programmable arrays can either compete with established stand-alone FPGAs on performance, but at half the power, or can be added as IP cores to SoCs. The Efinix Programmable Accelerator technology can provide a look up table (LUT)-based logic cell or a routing switch, among other functions, the company said.

Efinix was founded by several managers with engineering experience at Altera Corp. at various times in their careers — Sammy Cheung, Tony Ngai, Jay Schleicher, and Kar Keng Chua — and has financial backing from two Malaysia-based investment funds.

Flex Logix Technologies, (Mountain View, Calif.) (www.flex-logix.com) an eFPGA startup founded in 2014, recently gained formal admittance to TSMC’s IP Alliance program. It supports a wide array of foundry processes, providing embedded FPGA IP and software tools for TSMC’s 16FFC/FF+, 28HPM/HPC, and 40ULP/LP.

QuickLogic adds SMIC to foundry roster

Menta  (http://www.menta-efpga.com/) is another competitor in the FPGA space. Based in Montpellier, France, Menta is a privately held company founded a decade ago that offers programmable logic IP targeted to both GLOBALFOUNDRIES (14LPP) and TSMC (28HPM and 28HPC+) processes.

Menta offers either pre-configured IP blocks, or custom IPs for SoCs or ASICs. The French company supports its IP with a tool set, called Origami, which generates a bitstream from RTL, including synthesis. Menta said it has fielded four generations of products that in use by customers now “for meeting the sometimes conflicting requirements of changing standards, security updates and shrinking time-to-market windows of mobile and consumer products, IoT devices, networking and automotive ICs.”

QuickLogic, a Silicon Valley stalwart founded in 1988, also is expanding its eFPGA capability. In mid-September, QuickLogic (Sunnyvale, Calif.) (quicklogic.com) announced that its eFPGA IP can now be used with the 40nm low-leakage process at Shanghai-based Semiconductor Manufacturing International Corp. (SMIC). QuickLogic also offers its eFPGA technology on several of the mature GLOBALFOUNDRIES processes, and is participating in the foundry’s 22FDX IP program.

Wawrzyniak, who tracks the SoC market for Semico Research, said an important market is artificial intelligence, using eFPGA gates to add a flexible convolutional neural network (CNN) capability. Indeed, Flex Logix said one of its earliest adopters is an AI research group at Harvard University that is developing a programmable AI processor.

A seminal capability

The U.S. government’s Defense Advanced Projects Agency (DARPA) also has supported Flex Logix by taking a license, endorsing an eFPGA capability for defense and aerospace ICs used by the U.S. military.

With security being such a concern for the Internet of Things edge devices market, Wawrzyniak said eFPGA gates could be used to secure IoT devices against hackers, a potentially large market.

“The major use is in apps and instances where people need some programmability. This is a seminal, basic capability. How many times have you heard someone say, ‘I wish I could put a little bit of programmability into my SoC.’ People are going to take this and run with it in ways we can’t imagine,” he said.

Bob Wheeler, networking analyst at The Linley Group, said the intellectual property (IP) model makes sense for startups. Achronix, during the dozen years it developed and then fielded its standalone FPGAs, “was on a very ambitious road, competing with Altera and Xilinx. Achronix went down the road of developing parts, and that is a tall order.”

While the cost of running an IP company is less than fielding stand-alone parts, Wheeler said “People don’t appreciate the cost of developing the software tools, to program the FPGA and configure the IP.” The compiler, in particular, is a key challenge facing any FPGA vendor.

Wheeler said Achronix https://www.achronix.com/ , has gained credibility for its tools, including its compiler, after fielding its high-performance discrete FPGAs in 2016, made on Intel’s 22nm process.

And Wheeler cautioned that IP companies face the business challenge of getting a fair return on their development efforts, especially for low-cost IoT solutions where companies maintain tight budgets for the IP that they license.

Achronix earlier this year announced that its 2017 revenues will exceed $100 million, based on a seven-times increase in sales of its Speedster 22i FPGA family, as well as licensing of its Speedcore embedded IP products, targeted to TSMC’s leading-edge 16 nm node, with 7nm process technology for design starts beginning in the second half of this year. Achronix revenues “began to significantly ramp in 2016 and the company reached profitability in Q1 2017,” said CEO Robert Blake.

Escalating mask costs

Geoff Tate, now the CEO of Flex Logix Technologies, earlier headed up Rambus for 15 years. Tate said Flex Logix (www.flex-logix.com uses a hierarchical interconnect, developed by co-founder Cheng Wang and others while he earned his doctorate at UCLA. The innovative interconnect approach garnered the Lewis Outstanding Paper award for Wang and three co-authors at the 2014 International Solid-State Circuits Conference (ISSCC), and attracted attention from venture capitalists at Lux Ventures and Eclipse Ventures.

Tate said one of those VCs came to him one day and asked for an evaluation of Wang & Co.’s technology. Tate met with Wang, a native of Shanghai, and found him to be anything but a prima donna with a great idea. “He seemed very motivated, not just an R&D guy.”

While most FPGAs use a mesh interconnect in an X-Y grid of wires, Wang had come up with a hierarchical interconnect that provided high density without sacrificing performance, and proved its potential with prototype chips at UCLA.

“Chips need to be more flexible and adaptable. FPGAs give you another level of programmability,” Tate noted.

Meanwhile, potential customers in networking, data centers, and other markets were looking for ways to make their designs more flexible. An embedded FPGA block could help customers adapt a design to new wireless and networking protocols. Since mask costs were escalating, to an estimated $5 million for 16nm designs and more than double that for 7nm SoCs, customers had another reason to risk working with a startup.

TSMC has supported Flex Logix, in mid-September awarding the company the TSMC Open Innovation Platform’s Partner of the Year Award for 2017 in the category of New IP.

“Our lead customer has a working chip, with embedded FPGA on it. They are in the process of debugging rest of their chip. Overall, we are still in the early stages of market development,” Tate said, explaining that semiconductor companies are understandably risk-averse when it comes to their IP choices.

Asked about the status of its 16nm test chip, Tate said “the silicon is out of the fab. The next step is packaging, then evaluation board assembly.  We should be doing validation testing starting in late September.”

Potential customers are in the process of sending engineers to Flex Logix to look at metrics of the largest 16nm arrays, such as IR drop, vest vectors, switching simulations, and the like. “They making sure we are testing in a thorough fashion. If we screw them over, they’ll tell everybody, so we have got to get it right the first time,” Tate said.

The Semiconductor Industry Association (SIA) today announced worldwide sales of semiconductors reached $107.9 billion for the third quarter of 2017, marking the industry’s highest-ever quarterly sales and an increase of 10.2 percent compared to the previous quarter. Sales for the month of September 2017 were $36.0 billion, an increase of 22.2 percent over the September 2016 total of $29.4 billion and 2.8 percent more than the previous month’s total of $35.0 billion. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

highest ever sales

“Global semiconductor sales increased sharply year-to-year in September, and year-to-date sales through September are more than 20 percent higher than at the same point last year,” said John Neuffer, SIA president and CEO. “The industry posted its highest-ever quarterly sales in Q3, and the global market is poised to reach its highest-ever annual revenue in 2017.”

Regionally, year-to-year and month-to-month sales increased in September across all markets: the Americas (40.7 percent year-to-year/5.9 percent month-to-month), China (19.9 percent/2.5 percent), Europe (19.0 percent/1.8 percent), Asia Pacific/All Other (16.8 percent/1.9 percent), and Japan (11.9 percent/0.5 percent).

“The Americas market continued to stand out, notching its largest year-to-year sales increase in more than seven years,” Neuffer said. “Standouts among semiconductor product categories included memory products like DRAM and NAND flash, both of which posted major year-to-year growth in September, as well as Logic products, which enjoyed double-digit growth year-to-year.”

Scientists at the U.S. Department of Energy’s National Renewable Energy Laboratory (NREL) reported significant advances in the thermoelectric performance of organic semiconductors based on carbon nanotube thin films that could be integrated into fabrics to convert waste heat into electricity or serve as a small power source.

The research demonstrates significant potential for semiconducting single-walled carbon nanotubes (SWCNTs) as the primary material for efficient thermoelectric generators, rather than being used as a component in a “composite” thermoelectric material containing, for example, carbon nanotubes and a polymer. The discovery is outlined in the new Energy & Environmental Science paper, Large n- and p-type thermoelectric power factors from doped semiconducting single-walled carbon nanotube thin films.

“There are some inherent advantages to doing things this way,” said Jeffrey Blackburn, a senior scientist in NREL’s Chemical and Materials Science and Technology center and co-lead author of the paper with Andrew Ferguson. These advantages include the promise of solution-processed semiconductors that are lightweight and flexible and inexpensive to manufacture. Other NREL authors are Bradley MacLeod, Rachelle Ihly, Zbyslaw Owczarczyk, and Katherine Hurst. The NREL authors also teamed with collaborators from the University of Denver and partners at International Thermodyne, Inc., based in Charlotte, N.C.

Ferguson, also a senior scientist in the Chemical and Materials Science and Technology center, said the introduction of SWCNT into fabrics could serve an important function for “wearable” personal electronics. By capturing body heat and converting it into electricity, the semiconductor could power portable electronics or sensors embedded in clothing.

Blackburn and Ferguson published two papers last year on SWCNTs, and the new research builds on their earlier work. The first paper, in Nature Energy, showed the potential that SWCNTs have for thermoelectric applications, but the films prepared in this study retained a large amount of insulating polymer. The second paper, in ACS Energy Letters, demonstrated that removing this “sorting” polymer from an exemplary SWNCT thin film improved thermoelectric properties.

The newest paper revealed that removing polymers from all SWCNT starting materials served to boost the thermoelectric performance and lead to improvements in how charge carriers move through the semiconductor. The paper also demonstrated that the same SWCNT thin film achieved identical performance when doped with either positive or negative charge carriers. These two types of material–called the p-type and the n-type legs, respectively–are needed to generate sufficient power in a thermoelectric device. Semiconducting polymers, another heavily studied organic thermoelectric material, typically produce n-type materials that perform much worse than their p-type counterparts. The fact that SWCNT thin films can make p-type and n-type legs out of the same material with identical performance means that the electrical current in each leg is inherently balanced, which should simplify the fabrication of a device. The highest performing materials had performance metrics that exceed current state-of-the-art solution-processed semiconducting polymer organic thermoelectrics materials.

“We could actually fabricate the device from a single material,” Ferguson said. “In traditional thermoelectric materials you have to take one piece that’s p-type and one piece that’s n-type and then assemble those into a device.”

For the first time, researchers have used a single-step, laser-based method to produce small, precise hybrid microstructures of silver and flexible silicone. This innovative laser processing technology could one day enable smart factories that use one production line to mass-produce customized devices combining soft materials such as engineered tissue with hard materials that add functions such as glucose sensing.

Using a one-step laser fabrication process, researchers created flexible hybrid microwires that conduct electricity. (a) An optical microscope image of the silver (black) and silicone (clear) microwires. (b) Scanning electron microscopy image of the same fabricated structure. Both scale bars are equal to 25 microns. Credit: Mitsuhiro Terakawa, Keio University

Using a one-step laser fabrication process, researchers created flexible hybrid microwires that conduct electricity. (a) An optical microscope image of the silver (black) and silicone (clear) microwires. (b) Scanning electron microscopy image of the same fabricated structure. Both scale bars are equal to 25 microns. Credit: Mitsuhiro Terakawa, Keio University

The metal component of the microstructures renders them electrically conductive while the elastic silicone contributes flexibility. This unique combination of properties makes the structures sensitive to mechanical force and could be useful for making new types of optical and electrical devices.

“These types of microstructures could possibly be used to measure very small movements or changes, such as a slight movement from an insect’s body or the subtle expression produced by a human facial muscle,” said research team leader Mitsuhiro Terakawa from Keio University, Japan. “This information could be used to create perfect computer-generated versions of these movements.”

As detailed in the journal Optical Materials Express, from The Optical Society (OSA), the researchers produced wire-like structures of silver surrounded by a type of silicone known as polydimethylsiloxane (PDMS). The researchers used PDMS because it is flexible and biocompatible, meaning that it is safer to use on or in the body.

They fabricated the structures, which measure as little as 25 microns wide, by irradiating a mixture of PDMS and silver ions with extremely short laser pulses that last just femtoseconds. In one femtosecond, light travels only 300 nanometers, which is just slightly larger than the smallest bacteria.

“We believe we are the first group to use femtosecond laser pulses to create a hybrid material containing PDMS, which is very useful because of its elasticity,” said Terakawa. “The work represents a step towards using a single, precision laser processing technology to fabricate biocompatible devices that combine hard and soft materials.”

Turning two laser processes into one

The one-step fabrication method used to make the hybrid microstructures combines the light-based chemical reactions known as photopolymerization and photoreduction, both of which were induced using femtosecond laser pulses. Photopolymerization uses light to harden a polymer, and photoreduction uses light to form microstructures and nanostructures from metal ions.

The fabrication technique resulted from a collaboration between Terakawa’s research group, which been studying two-photon photoreduction using soft materials, and a group at the German research organization Laser Zentrum Hannover, that has been advancing single-photon photopolymerization of PDMS.

To create the wire microstructures, the researchers irradiated the PDMS-silver mixture with light from femtosecond laser emitting at 522-nm, a wavelength that interacts efficiently with the material mixture. They also carefully selected silver ions that would combine well with PDMS.

The researchers found that just one laser scan formed wires that exhibit both the electrical conductivity of metal and the elasticity of a polymer. Additional scans could be used to produce thicker and more uniform structures. They also showed that the wire structures responded to mechanical force by blowing air over the structures to create a pressure of 3 kilopascal.

The researchers say that, in addition to making wires structures, the approach could be used to make tiny 3D metal-silicone structures. As a next step, they plan to study whether the fabricated wires maintain their structure and properties over time.

“Our work demonstrates that simultaneously inducing photoreduction and photopolymerization is a promising method for fabricating elastic and electrically conductive microstructures,” said Terakawa. “This is one step toward our long-term goal of developing a smart factory for fabricating many human-compatible devices in one production line, whether the materials are soft or hard.”

The ConFab 2018 update


November 1, 2017

BY PETE SINGER, Editor-in-Chief

A new wave of growth is sweeping through the semiconductor industry, propelled by a vast array of new applications, including artificial intelligence, virtual and augmented reality, automotive, 5G, the IoT, cloud computing, healthcare and many others. The big question facing today’s semiconductor manufacturers and their suppliers is how can they best position themselves to take advantage of this tremendous growth.

Finding answers to that question is the goal of The ConFab 2018, to be held May 20-23 at The Cosmopolitan of Las Vegas. Now in its 14th year, The ConFab is a conference and networking event designed to inform and connect leading semiconductor executives from all parts of the supply chain. It is produced by Solid State Technology magazine, the semiconductor industry’s oldest and most respected business publication.

Kicking things off will be IBM’s Rama Divakaruni, who will speak on “How AI is Driving the New Semiconductor Era.” This is hugely important to how semiconductors will be designed and manufactured in the future, because AI — now in its infancy — will demand dramatic enhancement in computa- tional performance and efficiency. Fundamental changes will be required in algorithms, systems and chip design. Devices and materials will also need to change.

Rama is well position to address these changes: As an IBM Distin- guished Engineer, he is responsible for IBM Advanced Process Technology Research (which includes EUV technologies and advanced unit process and Enablement technologies) as well as the main interface between IBM Semiconductor Research and IBM’s Systems Leadership. He is one of IBMs top inventors with over 225+ issued US patents.

We’re also pleased to announce several other speakers at this point. Joining us will be George Gomba, VP of technology research at GlobalFoundries. George has overall responsibility for GlobalFoundries’ semiconductor technology research programs, including global consortia and strategic supplier management (and, like Rama, has a long history at IBM). The focus of George’s talk will be on EUV lithography.

Dan Armbrust, Founder and Director of Silicon Catalyst, the world’s first incubator focused exclusively on semiconductor solutions startups will also be on the dais. A frequent speaker at The ConFab, Dan has a great background, including President and Chief Executive Officer of SEMATECH, IBM VP, 300mm Semiconductor Operations, and Strategic Client Exec for IBM’s Systems and Technology Group.

Another great speaker is Tom Sonderman, President of SkyWater Technology Foundry. Tom also has a great background including GlobalFoundries’ VP of manufacturing technology, and two decases at AMD, where he had global responsibility for devel- opment, integration, support and scalability of automation and manufacturing systems in the company’s wafer fabrication and assembly operations. Prior to joining SkyWater, Prior to joining SkyWater, Tom was the group vice president and general manager for Rudolph Technologies’ Integrated Solutions Group. In this position, he created a Smart Manufacturing ecosystem based on big data platforms, predictive analytics and IoT.

We’re so excited about the other speakers we tentatively have lined up, our plans for several thought-provoking panels and much more, so stay tuned. You register and keep up-to-date by visiting www.theconfab.com. For sponsorship inquiries, contact Kerry Hoffman at [email protected]. For those interested in attending as a guest or qualifying as a VIP, contact Sally Bixby at [email protected].

Microsemi Corporation (Nasdaq: MSCC), a provider of semiconductor solutions differentiated by power, security, reliability and performance, and Knowles Corporation (NYSE: KN), jointly announced today that Microsemi has entered into a definitive agreement to acquire the high performance timing business of Vectron International, a Knowles company, for $130 million.

Vectron is a world leader in the design, manufacture and marketing of frequency control, sensor and hybrid solutions using the very latest techniques in both bulk acoustic wave (BAW) and surface acoustic wave (SAW)-based designs from DC to microwave frequencies. Products include crystals and crystal oscillators; frequency translators; clock and data recovery products; SAW filters; SAW oscillators; crystal filters; SAW and BAW based sensors and components used in telecommunications, data communications, frequency synthesizers, timing, navigation, military, aerospace, medical and instrumentation systems.

“Microsemi is focused on building the industry’s most comprehensive portfolio of high value timing solutions,” said James J. Peterson, Microsemi’s chairman and CEO. “Vectron’s highly complementary technology suite expands our product offering with differentiated technology and allows Microsemi to sell more to its tier one customers in the aerospace and defense, communications and industrial markets while improving upon the operating performance of the combined model as we execute on significant synergy opportunities.”

Microsemi expects the acquisition to be immediately accretive once closed.  The transaction is subject to customary closing conditions and is currently expected to close in Microsemi’s fiscal first quarter ending December 2017.

As of this date, Microsemi remains comfortable with its July 28, 2017 non-GAAP guidance for its fourth fiscal quarter of 2017 ended Oct. 1, 2017. Microsemi currently intends to announce its fourth fiscal quarter results on Nov. 9, 2017.

Research by scientists at Swansea University has shown that improvements in nanowire structures will allow for the manufacture of more stable and durable nanotechnology for use in semiconductor devices in the future.

Dr. Alex Lord and Professor Steve Wilks from the Centre for NanoHealth led the collaborative research published in Nano Letters. The research team defined the limits of electrical contact technology to nanowires at atomic scales with world-leading instrumentation and global collaborations that can be used to develop enhanced devices based on the nanomaterials. Well-defined, stable and predictable electrical contacts are essential for any electrical circuit and electronic device because they control the flow of electricity that is fundamental to the operational capability.

Their experiments found for the first time, that atomic changes to the metal catalyst particle edge can entirely alter electrical conduction and most importantly reveal physical evidence of the effects of a long standing problem for electrical contacts known as barrier inhomogeneity. The study revealed the electrical and physical limits of the materials that will allow nanoengineers to select the properties of manufacturable nanowire devices.

One-of-a-kind multi-probe LT Nanoprobe at Swansea University used to obtain the electrical measurements of nanowires that were correlated to atomic resolution imaging. Credit: Swansea University

One-of-a-kind multi-probe LT Nanoprobe at Swansea University used to obtain the electrical measurements of nanowires that were correlated to atomic resolution imaging. Credit: Swansea University

Dr Lord, recently appointed as a Senior Sêr Cymru II Fellow part-funded by the European Regional Development Fund through the Welsh Government, said: “The experiments had a simple premise but were challenging to optimise and allow atomic-scale imaging of the interfaces. However, it was essential to this study and will allow many more materials to be investigated in a similar way.

“This research now gives us an understanding of these new effects and will allow engineers in the future to reliably produce electrical contacts to these nanomaterials which is essential for the materials to be used in the technologies of tomorrow.

“The new concepts shown here provide interesting possibilities for bridged nanowire devices such as transient electronics and reactive circuit breakers that respond to changes in electrical signals or environmental factors and provide instantaneous reactions to electrical overload.”

The Swansea research team used specialist experimental equipment at the Centre for NanoHealth and collaborated with Professor Quentin Ramasse of the SuperSTEM Laboratory, Science and Facilities Technology Council1-3 and Dr Frances Ross of the IBM Thomas J. Watson Research Center, USA.3 The scientists were able to physically interact with the nanostructures and measure how atomic changes in the materials affected the electrical performance.

Dr. Frances Ross, IBM, USA, added: “”This research shows the importance of global collaboration, particularly in allowing unique instrumentation to be used to obtain fundamental results that allow nanoscience to deliver the next generation of technologies.”

Nanotechnology is the scaling down of everyday materials by scientists to the size of nanometres (one million times smaller than a millimetre on a standard ruler) and is seen as the future of electronic devices. Progressions in scientific and engineering advances are resulting in new technologies such as computer components for smart devices and sensors to monitor our health and the surrounding environment.

Nanotechnology is having a major influence on the Internet of Things which connects everything from our homes to our cars into a web of communication. All of these new technologies require similar advances in electrical circuits and especially electrical contacts that allow the devices to work correctly with electricity.

Silicon has provided enormous benefits to the power electronics industry. But performance of silicon-based power electronics is nearing maximum capacity.

Enter wide bandgap (WBG) semiconductors. Seen as significantly more energy-efficient, they have emerged as leading contenders in developing field-effect transistors (FETs) for next-generation power electronics. Such FET technology would benefit everything from power-grid distribution of renewable-energy sources to car and train engines.

Diamond is largely recognized as the most ideal material in WBG development, owing to its superior physical properties, which allow devices to operate at much higher temperatures, voltages and frequencies, with reduced semiconductor losses.

A main challenge, however, in realizing the full potential of diamond in an important type of FET — namely, metal-oxide-semiconductor field-effect transistors (MOSFETs) — is the ability to increase the hole channel carrier mobility. This mobility, related to the ease with which current flows, is essential for the on-state current of MOSFETs.

Researchers from France, the United Kingdom and Japan incorporate a new approach to solve this problem by using the deep-depletion regime of bulk-boron-doped diamond MOSFETs. The new proof of concept enables the production of simple diamond MOSFET structures from single boron-doped epilayer stacks. This new method, specific to WBG semiconductors, increases the mobility by an order of magnitude. The results are published this week in Applied Physics Letters, from AIP Publishing.

Left: Optical microscope image of the MOSCAPs and diamond deep depletion MOSFETs (D2MOSFETs) of this work. Top right: Scanning electron microscope image of a diamond D2MOSFET under electrical investigation. S: Source, G: Gate, D: Drain. Bottom right: D2MOSFET concept. The on-state of the transistor is ensured thanks to the accumulation or flat band regime. The high mobility channel is the boron-doped diamond epilayer. The off-state is achieved thanks to the deep depletion regime, which is stable only for wide bandgap semiconductors. For a gate voltage larger than a given threshold, the channel is closed because of the deeply and fully depleted layer under the gate. Credit: Institut NÉEL

Left: Optical microscope image of the MOSCAPs and diamond deep depletion MOSFETs (D2MOSFETs) of this work. Top right: Scanning electron microscope image of a diamond D2MOSFET under electrical investigation. S: Source, G: Gate, D: Drain. Bottom right: D2MOSFET concept. The on-state of the transistor is ensured thanks to the accumulation or flat band regime. The high mobility channel is the boron-doped diamond epilayer. The off-state is achieved thanks to the deep depletion regime, which is stable only for wide bandgap semiconductors. For a gate voltage larger than a given threshold, the channel is closed because of the deeply and fully depleted layer under the gate. Credit: Institut NÉEL

In a typical MOSFET structure, an oxide layer and then a metal gate are formed on top of a semiconductor, which in this case is diamond. By applying a voltage to the metal gate, the carrier density, and hence the conductivity, of the diamond region just under the gate, the channel, can be changed dramatically. The ability to use this electric “field-effect” to control the channel conductivity and switch MOSFETS from conducting (on-state) to highly insulating (off-state) drives their use in power control applications. Many of the diamond MOSFETs demonstrated to date rely on a hydrogen-terminated diamond surface to transfer positively charged carriers, known as holes, into the channel. More recently, operation of oxygen terminated diamond MOS structures in an inversion regime, similar to the common mode of operation of silicon MOSFETS, has been demonstrated. The on-state current of a MOSFET is strongly dependent on the channel mobility and in many of these MOSFET designs, the mobility is sensitive to roughness and defect states at the oxide diamond interface where unwanted carrier scattering occurs.

To address this issue, the researchers explored a different mode of operation, the deep-depletion concept. To build their MOSFET, the researchers deposited a layer of aluminum oxide (Al2O3) at 380 degrees Celsius over an oxygen-terminated thick diamond epitaxial layer. They created holes in the diamond layer by incorporating boron atoms into the layer. Boron has one less valence electron than carbon, so including it leaves a missing electron which acts like the addition of a positive charge, or hole. The bulk epilayer functioned as a thick conducting hole channel. The transistor was switched from the on-state to the off-state by application of a voltage which repelled and depleted the holes — the deep depletion region. In silicon-based transistors, this voltage would have also resulted in formation of an inversion layer and the transistor would not have turned off. The authors were able to demonstrate that the unique properties of diamond, and in particular the large band gap, suppressed formation of the inversion layer allowing operation in the deep depletion regime.

“We fabricated a transistor in which the on-state is ensured by the bulk channel conduction through the boron-doped diamond epilayer,” said Julien Pernot, a researcher at the NEEL Institute in France and an author of the paper. “The off-state is ensured by the thick insulating layer induced by the deep-depletion regime. Our proof of concept paves the way in fully exploiting the potential of diamond for MOSFET applications.” The researchers plan to produce these structures through their new startup called DiamFab.

Pernot observed that similar principles of this work could apply to other WBG semiconductors. “Boron is the doping solution for diamond,” Pernot said, “but other dopant impurities would likely be suitable to enable other wide bandgap semiconductors to reach a stable deep-depletion regime.”

Last year at Arm TechCon, SoftBank Chairman and President Masayoshi Son laid out an ambitious vision of a trillion connected devices. It’s a vision ARM is aggressively pursuing by working with their ecosystem to invisibly enable those trillion devices to connect securely.

Connecting a trillion devices is no easy task of course but doing it securely is key. Especially when the tools and techniques used by attackers are rapidly evolving to go after every piece of system hardware from foundational SoCs to peripheral components. All are seen as an opportunity to access privileged data. With daily occurrences of cyber-attacks, it’s clear security across the entire device needs to be considered at the design stage, not as an afterthought.

At the SoC level, there are many classes of threats including those where attackers try to take advantage of the physical characteristics of the silicon implementation manifested during algorithmic execution. Today, ARM is announcing the availability of highly-efficient on-die threat mitigation technology designed to protect against threats including:

  • Simple and Differential Power Analysis (SPA/DPA), where an attacker is trying to compromise confidential information (e.g. a secret cryptographic key) through various analysis methods of the power consumed by an integrated circuit (IC) during operation
  • Simple and Differential Electromagnetic Analysis (SEMA/DEMA), where an attacker is trying to compromise confidential information (e.g. a secret cryptographic key) through various analysis methods of the electromagnetic field created during IC operation

The power and electromagnetic analysis mitigation technology relieves designers of the need to worry about this category of non-invasive attacks, while providing a solution that is easily scalable to cover changes in the protected logic. The resulting system benefit is addressing the leakage source directly and preventing sensitive data leakage through the IC power consumption and electromagnetic emission. From an implementation perspective, the mitigation technology is applicable across the full spectrum of silicon processes used in the semiconductor industry.

Trust between connected devices and their users is a critical factor in the continued growth of the IoT, particularly in applications making use of highly sensitive data, such as autonomous vehicles, mobile payment systems and connected health. Adding this technology to our security IP portfolio will enable the deployment of more secure devices as we drive toward our vision of a truly connected world.

To learn more about ARM security solutions, attend the security track at Arm TechCon, (Oct. 24-26 in Santa Clara, CA.)