Category Archives: Wafer Level Packaging

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that GLOBALFOUNDRIES (GF) has chosen Cadence as the primary EDA tool vendor for use in Avera Semi, a GF subsidiary, for advanced node chip design projects. The Avera Semi engineering team has come to rely on the features, capacity, speed and scalability of the Cadence® digital and signoff, system and verification, custom IC and PCB design and analysis tools and flows. Establishing Cadence as their primary vendor has enabled them to improve engineering productivity.

Avera Semi has successfully completed several large, complex 12nm and 14nm tapeouts and delivered production designs using Cadence flagship solutions such as the Innovus Implementation System, the GenusSynthesis Solution, the Tempus Timing Signoff Solution and XceliumParallel Logic Simulation as well as the Virtuoso® custom IC design platform, Spectre® circuit simulation platform and Allegro® and Sigritytools, which are part of following product categories:

  • Digital and Signoff: The parallelized, integrated Cadence digital and signoff solutions provided Avera Semi with a trusted design flow to achieve industry-leading power, performance and area (PPA) results with integrated signoff accuracy for designs with more than 500M instances, complex clocking requirements and chip sizes at the mask reticle limit.
  • System and Verification: The Cadence Verification Suite helped the Avera Semi verification team find bugs more efficiently, quickly implement and bring up complex testbenches for faster project completion and fuel testbench automation, analysis and reuse for increased productivity.
  • Custom IC/Analog Design: The comprehensive analog and mixed-signal simulation capabilities in the Cadence custom IC design platform enabled Avera Semi to consistently, accurately and quickly design and verify complex IP such as the Avera Semi 112G Serial Link. Additionally, the tight integration of Cadence physical verification and design-for-manufacturing (DFM) tools within the Cadence Virtuoso IC design platform accelerated design and implementation.
  • PCB Design and Analysis: Cadence’s PCB design and analysis tools helped Avera Semi achieve a smooth and efficient interface between the chip and packaging teams, helping to manage and track engineering change requests. The tools’ customizability enabled Avera Semi to automate the numerous properties associated with a package, reducing manual errors and design cycle time.

“Today’s announcement is another solid step in our collaborative journey to achieve a higher level of productivity through Cadence’s design flow,” said Kevin O’Buckley, GM at Avera Semi. “We have already deployed the Cadence flows to complete a number of successful production designs for our customers using the GF 12nm and 14nm FinFET process technologies and will extend our collaboration with Cadence on advanced nodes. Standardizing on Cadence’s custom, digital and IC package flows and verification solutions will help us master new challenges encountered at advanced nodes and expand our leadership in designs for data centers, wired communications, and machine learning and artificial intelligence applications.”

“Avera Semi uses Cadence as its primary supplier due to many years of successful collaborations on large, complex designs that met evolving market demands,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “We are always working to optimize design flow speed, throughput and provide differentiated tool features to deliver best-in-class PPA to customers. As we expand upon our longstanding relationship with Avera Semi, their customers can also benefit from our continued innovation and dedication to advancing ASIC design.”

Intel names Robert Swan CEO

January 31, 2019

Intel Corporation (NASDAQ: INTC) today announced that its board of directors has named Robert (Bob) Swan as chief executive officer. Swan, 58, who has been serving as Intel’s interim CEO for seven months and as chief financial officer since 2016, is the seventh CEO in Intel’s 50-year history. Swan has also been elected to Intel’s board of directors.

Intel Corporation has named Robert Swan as its chief executive officer. His promotion was announced Jan. 31, 2019. Swan, who previously served as the company’s chief financial officer and interim CEO, is the seventh CEO to lead the company based in Santa Clara, Calif. (Credit: Intel Corporation)

Todd Underwood, vice president of Finance and director of Intel’s Corporate Planning and Reporting, will assume the role of interim chief financial officer as the company undertakes an internal and external search for a permanent CFO.

“As Intel continues to transform its business to capture more of a large and expanding opportunity that includes the data center, artificial intelligence and autonomous driving, while continuing to get value from the PC business, the board concluded after a thorough search that Bob is the right leader to drive Intel into its next era of growth,” said Chairman Andy Bryant. “The search committee conducted a comprehensive evaluation of a wide range of internal and external candidates to identify the right leader at this critical juncture in Intel’s evolution. We considered many outstanding executives and we concluded the best choice is Bob. Important in the board’s decision was the outstanding job Bob did as interim CEO for the past seven months, as reflected in Intel’s outstanding results in 2018. Bob’s performance, his knowledge of the business, his command of our growth strategy, and the respect he has earned from our customers, our owners, and his colleagues confirmed he is the right executive to lead Intel.”

“In my role as interim CEO, I’ve developed an even deeper understanding of Intel’s opportunities and challenges, our people and our customers,” Swan said. “When I was first named interim CEO, I was immediately focused on running the company and working with our customers. When the board approached me to take on the role permanently, I jumped at the chance to lead this special company. This is an exciting time for Intel: 2018 was an outstanding year and we are in the midst of transforming the company to pursue our biggest market opportunity ever. I’m honored to have the chance to continue working alongside our board, our leadership team, and our more than 107,000 superb employees as we take the company forward.”

Swan is a proven leader with a strong track record of success both within and outside Intel. As interim CEO, Swan has managed the company’s operations in close collaboration with Intel’s senior leadership team. Swan has been Intel’s CFO since October 2016. In this role, he led the global finance, mergers and acquisitions, investor relations, IT and corporate strategy organizations. Prior to joining Intel, Swan served as an operating partner at General Atlantic LLC and served on Applied Materials’ board of directors. He previously spent nine years as CFO of eBay Inc., where he is currently a director. Earlier in his career, he was CFO of Electronic Data Systems Corp. and TRW Inc. He also served as CFO, COO and CEO of Webvan Group Inc., and began his career at General Electric, serving for 15 years in several senior finance roles.

ZEISS today unveiled a new suite of high-resolution 3D X-ray imaging solutions for failure analysis (FA) of advanced semiconductor packages, including 2.5/3D and fan-out wafer-level packages. The new ZEISS systems include the Xradia 600-series Versa and Xradia 800 Ultra X-ray microscopes (XRM) for submicron and nanoscale package FA, respectively, as well as the new Xradia Context microCT. With the addition of these new systems to its existing family of products, ZEISS now provides the broadest portfolio of 3D X-ray imaging technologies serving the semiconductor industry.

“Throughout its 170-year history, ZEISS has pushed the frontiers of scientific research and advanced the start-of-the-art in imaging technologies to enable new industrial applications and technological innovations,” stated Dr. Raj Jammy, president, ZEISS Process Control Solutions (PCS) and Carl Zeiss SMT, Inc. “Now more than ever in the semiconductor industry, where package as well as device features are shrinking in all three dimensions, new imaging solutions are needed to quickly isolate failures in order to enable higher package yields. We are extremely pleased to announce this trio of new 3D X-ray imaging solutions for advanced semiconductor packaging, which provides our customers with a powerful high-resolution toolset to improve their failure analysis success rates.”

Advanced Packaging Requires New Defect Detection and Failure Analysis Methods
As the semiconductor industry approaches the limits of CMOS scaling, semiconductor packaging needs to help bridge the performance gap. To continue producing ever-smaller and faster devices with lower power requirements, the semiconductor industry is turning to package innovation through 3D stacking of chips and other novel packaging formats. This drives increasingly complex package architectures and new manufacturing challenges, along with increased risk of package failures. Furthermore, since the physical location of failures is often buried within these complex 3D structures, conventional methods for visualizing failure locations are becoming less effective. New techniques are required to efficiently isolate and determine the root cause of failures in these advanced packages.

To address these needs, ZEISS has developed a new suite of 3D X-ray imaging solutions that provides submicron and nanoscale 3D images of features and defects buried within intact structures in advanced package 3D architectures. This is enabled by rotating a sample and capturing a series of 2D X-ray images from different perspectives, followed by reconstruction of 3D volumes using sophisticated mathematical models and algorithms. An unlimited number of virtual cross-sections of the 3D volume may be viewed from any angle – providing valuable insight of failure locations prior to physical failure analysis (PFA). The combination of submicron and nanoscale XRM solutions from ZEISS provides a unique FA workflow that can significantly enhance FA success rates. ZEISS’s new Xradia Context microCT offers high contrast and resolution in a large field of view, using projection-based geometric magnification, and is fully upgradable to Xradia Versa.

New Imaging Solutions in Detail
Xradia 600-series Versa is the next generation of 3D XRM for non-destructive imaging of localized defects within intact advanced semiconductor packages. It excels in structural and FA applications for process development, yield improvement and construction analysis. Based on the award-winning Versa platform with Resolution at a Distance (RaaD) capability, Xradia 600-series Versa offers unsurpassed performance for high-resolution imaging of larger samples at long working distances to determine root causes of defects and failures in packages, circuit boards and 300 mm wafers. It can easily visualize defects associated with package-level failures, such as cracks in bumps or microbumps, solder wetting problems or through silicon via (TSV) voids. The 3D visualization of defects prior to PFA reduces artifacts and guides cross-section orientations, leading to improved FA success rates. Features include:

  • 0.5 micron spatial resolution, 40 nm min voxel size
  • Up to 2x higher throughput than Xradia 500-series Versa, achieved while maintaining high resolution with excellent source spot-size stability and thermal management control across the full kV and power range
  • Improved ease of use, including fast-activation source control
  • Ability to observe submicron structural changes within a package successively imaged at multiple reliability test read points

Xradia 800 Ultra brings 3D XRM to the nanoscale realm, producing images of buried features with nanoscale spatial resolution while preserving the volume integrity of the region of interest. Applications include process analysis, construction analysis and defect analysis of ultra-fine-pitch flip chip and bump connections – enabling process improvement for ultra-fine-pitch package and back-end-of-line (BEOL) interconnects. Xradia 800 Ultra enables visualization of the texture and volume of solder consumed by intermetallic compounds in fine-pitch copper pillar microbumps. Defect sites are preserved during imaging, enabling targeted follow-up analysis by a variety of techniques. The construction quality of blind assemblies, such as wafer-to-wafer bonded interconnect and direct hybrid bonding, can be characterized in 3D. Features include:

  • 150 nm and 50 nm spatial resolution (sample preparation is required)
  • Optional pico-second laser sample prep tool, enabling extraction of an intact volume sample (typically 100 microns in diameter) in under one hour
  • Compatibility with a wide range of options for follow-on analysis, including transmission electronic microscopy (TEM), energy dispersive X-ray spectroscopy (EDS), atomic force microscopy (AFM), secondary ion mass spectroscopy (SIMS) and nanoprobing

IC Insights is in the process of completing its forecast and analysis of the IC industry and will present its new findings in The McClean Report 2019, which will be published later this month.  Among the semiconductor industry data included in the new 400+ page report is an analysis of semiconductor merger and acquisition agreements.

The historic flood of merger and acquisition agreements that swept through the semiconductor industry in 2015 and 2016 slowed significantly in 2017 and then eased back further in 2018, but the total value of M&A deals reached in the last year was still nearly more than twice the annual average during the first half of this decade.  Acquisition agreements reached in 2018 for semiconductor companies, business units, product lines, and related assets had a combined value of $23.2 billion compared to $28.1 billion in 2017, based on data compiled by IC Insights.  The values of M&A deals struck in these years were significantly less than the record-high $107.3 billion set in 2015 (Figure 1).

Figure 1

The original 2016 M&A total of $100.4 billion was lowered by $41.1 billion to $59.3 billion because several major acquisition agreements were not completed, including the largest proposed deal ever in semiconductor history—Qualcomm’s planned purchase of NXP Semiconductor for $39 billion, which was raised to $44 billion before being canceled in July 2018.  Prior to the explosion of semiconductor acquisitions that erupted four years ago, M&A agreements in the chip industry had a total annual average value of $12.6 billion in the 2010-2014 timeperiod.

The two largest acquisition agreements in 2018 accounted for about 65% of the M&A total in the year.  In March 2018, fabless mixed-signal IC and power discrete semiconductor supplier Microsemi agreed to be acquired by Microchip Technology for $8.35 billion in cash.  Microchip said the purchase of Microsemi would boost its position in computing, communications, and wireless systems applications.  The transaction was completed in May 2018.  Fabless mixed-signal IC supplier Integrated Device Technology (IDT) agreed in September 2018 to be purchased by Renesas Electronics for $6.7 billion in cash.  Renesas believes the IDT acquisition will strengthen its position in automotive ICs for advanced driver-assistance systems and autonomous vehicles.  The IDT purchase is expected to be completed by June 2019.

Just two other semiconductor acquisition announcements in 2018 had values of more than $1 billion.  In October 2018, memory maker Micron Technology said it would exercise an option to acquire full ownership of its IM Flash Technology joint venture from Intel for about $1.5 billion in cash. Micron has started the process of buying Intel’s non-controlling interest in the non-volatile memory manufacturing and development joint venture, located in Lehi, Utah.  The transaction is expected to be completed in 2H19.  In September 2018, China’s largest contract manufacturer of smartphones, Wingtech Technology, began acquiring shares of Nexperia, a Dutch-based supplier of standard logic and discrete semiconductors that was spun out of NXP in 2017 with the financial backing of Chinese investors.   Wingtech launched two rounds of share purchases from the Chinese owners of Nexperia with a combined value of nearly $3.8 billion.  The company hopes to take majority ownership of Nexperia (about 76% of the shares) in 2019.

Panel FO-WLP is in production at Powertech Technology, Inc. (PTI) for MediaTek’s power management integrated circuit (PMIC) for smartphone applications. The Samsung Galaxy watch uses the fan-out panel level process (FOPLP) developed by Samsung Electro-Mechanics (SEMCO) to package the application processor and PMIC. Future applications under consideration for panel production include application processors, memory and RF modules. TechSearch International, Inc. details these applications and analyzes monthly panel requirements and planned capacity. Supplier plans are discussed and consortia activities are highlighted.

One of the major market trends in wearable electronics is the shift to smartwatches, which have surpassed shipment numbers for wristbands. Package trends for wearable electronic products are analyzed, including Apple’s new smartwatch using TSMC’s InFO and Samsung’s Galaxy using FOPLP. The latest trends in augmented reality (AR) and virtual reality (VR) headsets are discussed. A detailed analysis of the change in packages from the previous generation HTC Vive VR system is presented.

A detailed analysis of the OSAT financials is provided with regional growth documented. Board and substrate material requirements for 5G applications are presented.

The latest Advanced Packaging Update is a 45-page report with full references and an accompanying set of 46 PowerPoint slides.

TechSearch International, Inc., founded in 1987, is a market research leader specializing in technology trends in microelectronics packaging and assembly. Multi- and single-client services encompass technology licensing, strategic planning, and market and technology analysis. TechSearch International professionals have an extensive network of more than 18,000 contacts in North America, Asia, and Europe. For more information, contact TechSearch at tel: 512-372-8887 or see Follow us on twitter @Jan_TechSearch

The semiconductor manufacturing industry is fighting to attract, educate, and retain the necessary talent for its continued growth. A significant workforce gap of up to 10,000 global positions stretches the industry’s ability to meet the world’s already demanding technology needs. To solve this challenge, SEMI, the global electronics manufacturing association, is launching an audacious and innovative campaign to raise industry awareness and attract students and recent graduates that don’t yet know about the immense opportunities available to them in semiconductor manufacturing.

Semiconductors are the brains and memory of all modern electronics. Their incredible processing power has made breakthroughs possible in communication, transportation, and medicine, powering everything from smartphones to space travel. Whether you’re driving a car, surfing the internet or using a computer, semiconductors drive technological innovation. Global semiconductor revenue has grown by over $100 billion in the last four years and is projected to surpass $0.5 trillion by 2019.

The campaign, You’re Welcome, speaks to how fundamental, yet underappreciated, this technology is. It includes a suspenseful, action-filled movie trailer that shows what happens when scientists, engineers, and mathematicians make semiconductors to save the world from the brink of disaster. The video also takes viewers behind-the-scenes of a semiconductor facility, or fab, which brings together cutting-edge STEM fields to develop the world’s most advanced technology. The campaign’s website provides information about the value and production of semiconductors, as well as a career guide that showcases the wide variety of opportunities available with companies such as Intel, Samsung, Applied Materials, Tokyo Electron, and the more than 2,000 SEMI member companies.

The campaign is just one piece in SEMI’s comprehensive workforce development plan. The plan engages students as early-on as 4th grade, inspires and motivates them through high school and college, and provides pathways to professional careers, building a pipeline to fill the short-term and long-term needs of the industry. Through the You’re Welcome campaign, SEMI is addressing the increasingly urgent workforce need by taking a completely new, never-before-seen approach to talent recruitment by leveraging high-interest areas of entertainment, media and storytelling to excite students about the industry’s role in society.

Sanjay Mehrotra, President and CEO, Micron Technology, 2019 SIA Chair

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced the SIA Board of Directors has elected Sanjay Mehrotra, President and CEO of Micron Technology, Inc. (NASDAQ: MU), as its 2019 Chair and Keith Jackson, President, CEO, and Director of ON Semiconductor (NASDAQ: ON), as its 2019 Vice Chair.

“It is a great pleasure to welcome Sanjay Mehrotra as SIA’s 2019 Chair and Keith Jackson as SIA’s Vice Chair,” said John Neuffer, SIA President and CEO. “A design engineer by trade, Sanjay is a highly accomplished industry veteran and a leading voice on semiconductor technology. With more than 30 years of experience, Keith is a mainstay in our industry and a devoted champion for semiconductor priorities. Their combined skills and experience will be a tremendous asset to SIA as we pursue our industry’s interests in Washington and around the world.”

A 39-year veteran of the semiconductor industry, Mehrotra joined Micron in May 2017 after a long and distinguished career at SanDisk Corporation, where he led the company from a start-up in 1988 until its eventual sale in 2016. In addition to being a SanDisk co-founder, Mehrotra served as its President and CEO from 2011 to 2016, overseeing its growth to an industry-leading Fortune 500 company.

Prior to SanDisk, Mehrotra held design engineering positions at Integrated Device Technology, Inc., SEEQ Technology, and Intel Corporation. Mehrotra earned both bachelor’s and master’s degrees in electrical engineering and computer science from the University of California, Berkeley. He holds more than 70 patents and has published articles in the areas of non-volatile memory design and flash memory systems.

“The semiconductor industry is leading the greatest period of technological advancement in human history, making the seemingly impossible possible and opening up tremendous opportunities for economic growth,” said Mehrotra. “Driving innovation requires our industry to speak with one voice and promote policies that support our industry vision, and I look forward to helping lead that effort as 2019 SIA Chair.”

Jackson began serving as President, CEO, and Director of ON Semiconductor in November 2002. Before joining ON Semiconductor, he was with Fairchild, serving as Executive Vice President and General Manager, Analog, Mixed Signal, and Configurable Products Groups, and was head of its Integrated Circuits Group.

Previously, Jackson served as President and a Member of the Board of Directors of Tritech Microelectronics in Singapore and worked for National Semiconductor Corporation, most recently as Vice President and General Manager of the Analog and Mixed Signal division. He also held various positions at Texas Instruments Incorporated, including engineering and management positions, from 1973 to 1986. Mr. Jackson earned his bachelor’s and master’s degrees from Southern Methodist University.

“It is an honor to serve as 2019 SIA Vice Chair,” Jackson said. “Many issues of great importance to the semiconductor industry are being debated in Washington and around the world. We look forward to promoting policies that advance semiconductor technology and move our industry forward.”


Mentor, a Siemens business, today announced that DECA Technologies has become the latest member of Mentor’s (outsourced assembly and test) OSAT Alliance – a program to help drive faster adoption of new, high-density advanced packaging (HDAP) technologies like 2.5D IC, 3D IC and fan-out wafer-level packaging (FOWLP) for customer integrated circuit (IC) designs. The Alliance enables mutual customers to better leverage Mentor’s proven HDAP flow to quickly bring to market innovations for internet of things (IoT), automotive, high-speed communications, computing and artificial intelligence (AI). DECA is supporting this objective by making available to Mentor and DECA’s mutual customers a new assembly design kit (ADK) for DECA’s M-Series advanced fan-out wafer-level package (FOWLP) process to be used with Mentor software.

Through the alliance, the two companies are offering a comprehensive tool flow that gives mutual customers the ability to create and evaluate multiple complex IC package assemblies and interconnect scenarios in an easy-to-use, data robust graphical environment prior to and during physical design implementation.

The Mentor flow from DECA Technologies features industry-leading tools:

  • Xpedition® Substrate Integrator – for engineers to evaluate M-Series package and configuration before committing to design; and for DECA configuration of customer designs into selected M-Series package.
  • Xpedition® Package Designer – for engineers to design/layout a single or multi-die M-Series package.
  • Calibre® 3DSTACK – for signoff leveraging the M Series ADK – ensures die or multiple dice and package design conform to M-Series manufacturing rules.

The DECA ADK provides mutual customers with a verified sign-off fabrication rule deck for Calibre 3DSTACK that will enable companies to converge on sign-off faster and with less verification cycles.

“Being part of the Mentor OSAT Alliance has allowed DECA to fast-track the creation of a Mentor-based ADK for our breakthrough M-Seriesä FO-WLP technology,” said Chris Scanlan, senior vice president at DECA Technologies. “Since the Mentor flow includes Calibre, the golden signoff solution for the fabless ecosystem, our customers are able to quickly close any physical verification issues for their entire solution, resulting in faster time to market.”

Mentor continues to spearhead the EDA industry by enabling the entire ecosystem to adopt new technologies via its OpenDoor program and the various alliances that fall under the program. The OSAT Alliance program helps promote the adoption, implementation and growth of HDAP throughout the semiconductor eco-system and design chain, enabling system and fabless semiconductor companies to have a friction-free path to emerging packaging technologies.

“We are pleased that HDAP technology pioneer DECA Technologies has joined the Mentor OSAT Alliance,” said AJ Incorvaia, vice president and general manager of Mentor’s Electronic Board Systems Division. “In doing so, and by providing a fully validated ADK for DECA’s M-Series FOWLP process for Mentor’s proven HDAP tool flow, we have enabled customers to more easily transition from classic chip design to 2.5 and 3D solutions.”

By Paul Semenza

Automobiles have become an even more important segment for MEMS and sensors as carmakers integrate more chips for propulsion, navigation, and control into their designs. However, these advanced functions and their crisp rate of adoption have fragmented the sourcing of automotive chips. IHS Markit’s Jérémie Bouchaud provided a closer look at and outlook for this key market at the MEMS and Sensors Executive Congress in late October in Napa. Following are key takeaways from his presentation.

Autonomous and Electric/Hybrid Vehicles to Drive MEMS Market Growth

The automotive market, approaching 100 million vehicles produced annually, is approaching $6 billion, dominated by MEMS and silicon magnetic sensors for chassis and safety, and powertrain applications. Going forward, the market growth will be in autonomous vehicles and electric/hybrid vehicles. Because the penetration of electric and hybrid vehicles is much higher than that of autonomous vehicles, it has a larger available market, particularly for sensors. Each of these markets has its own dynamics.

For example, the electric and hybrid market has historically relied on a significant number of traditional, or non-semiconductor sensors, but new sensor technologies are vying to address multiple sensing needs. The most important limitation on demand of autonomous vehicles is the overall market penetration: IHS Markit expects autonomous vehicle production to reach 10 million at most by 2030.

Production of Electric and Hybrid Automobiles Now Growing at Fast Clip

Production of electric and hybrid vehicles is in a rapid growth phase, and IHS Markit expects penetration of such vehicles to reach 50% of the automotive market by 2030, up from 3% in 2016. The core functions of charging and power inversion require, among other capabilities, current, temperature and position sensing. Historically, many of these functions have been handled by non-semiconductor devices, for example negative temperature coefficient (NTC) thermistors for temperature sensing, devices that appear to be strongly positioned. In other areas, semiconductor sensors are competing with traditional devices.

For example, silicon magnetoresistive devices are going head-to-head with inductive devices for position and Hall effect sensing. Sensing requirements are also likely to evolve over time, particularly as battery systems become more reliable and robust. While some automakers are looking to sensors to monitor pressure or gas leaks from batteries, battery makers are more focused on maturing the systems and reducing the need for monitoring.

Autonomous Vehicles Drive New Source of Demand for MEMS and Sensors

The movement towards automated driving has created a new source of demand for MEMS and sensors, with advanced driver assistance systems driving faster growth than the historical powertrain applications. Currently available vehicles are at Level 2 (partial automation), with multiple cameras and radars. Level 3 vehicles (conditional automation) are likely to enter the market next year, adding driver monitoring cameras, LIDAR systems and, potentially, microbolometers or other night-vision systems. Level 4 and 5 (high and full automation, respectively) will add vehicle-to-vehicle communications and other systems, but are not likely to be widely available for several years.

The autonomous vehicle market, while smaller overall compared to electric/hybrid vehicles, provides a more attractive opportunity for MEMS devices, particularly in LIDAR systems. LIDAR and other sensing/surveying systems are at the heart of autonomous vehicles, and MEMS devices are in demand for the critical beam-steering function. However, demand for image and other sensors will accelerate as the higher levels of autonomy are rolled out.

Automotive Drives Extremely Diverse Set of Applications for MEMS and Sensor Makers

The automotive market presents an extremely diverse set of applications for MEMS and sensor makers. Some companies have developed broad product portfolios and compete in multiple applications. For example, TDK offers NTC thermistors as well as MEMS and silicon-based sensors. Semiconductor companies such as Infineon are competing in MEMS and with silicon-based sensors such as magnetoresitive and Hall effect.

The growth in demand for image and radar sensors used in ADAS, as well as magnetoresistive and Hall sensors in EVs, means that the center of gravity in automotive markets is likely to shift from MEMS over the next several years – a fundamental change, Bouchaud cautioned, that will put automotive sensor suppliers focusing solely on MEMS at risk.

Paul Semenza is a consultant in SEMI Industry Research and Statistics. 

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that IHP – Innovations for High Performance Microelectronics (IHP), a German research institute for silicon-based systems, highest-frequency integrated circuits, and technologies for wireless and broadband communication, has purchased an EVG® ComBond® automated high-vacuum wafer bonding system for use in developing next-generation wireless and broadband communication devices.

The EVG ComBond features micron-level wafer-to-wafer alignment accuracy and room-temperature covalent bonding, which enables a wide variety of substrate and interconnect combinations for producing advanced engineered substrates, next-generation MEMS and power devices, stacked solar cells, and high-performance logic and “beyond CMOS” devices. The ability to conduct oxide-free aluminum-to-aluminum (Al-Al) direct bonding at low temperature is a unique capability of the EVG ComBond platform, and is among the new bonding applications that IHP will explore with the system.

The EVG ComBond® features micron-level wafer-to-wafer alignment accuracy and room-temperature covalent bonding, which enables a wide variety of substrate and interconnect combinations.

Covalent bonding enables wafer-level packaging and heterogeneous integration

Heterogeneous integration through wafer-level-packaging (WLP) — where multiple semiconductor components with different design nodes, sizes or materials are combined into a single package at the wafer level — is key to extending the semiconductor technology roadmap. Metal and hybrid wafer bonding are key process technologies for WLP and heterogeneous integration due to their ability to enable ultra-fine pitch interconnections between the stacked devices or components. The continuous drive to higher performance and functionality of these integrated systems requires constant reductions in the dimensions and pitch of the interconnects — which in turn drives the need for tighter wafer bond alignment accuracy.

In addition, for certain WLP applications, Al-Al direct bonding is a promising new method of metal-based bonding due to aluminum’s low cost coupled with its high thermal and electrical conductivities. However, conventional Al-Al thermo-compression bonding requires high temperatures and bond forces to provide reliable bonding interfaces — making it incompatible with heterogeneous integration efforts.

According to Paul Lindner, executive technology director at EV Group, “Combining different materials and device components into a single package has taken on greater importance in adding performance and value to electronic devices. The EVG ComBond facilitates the bonding of nearly ‘anything on anything’ in wafer form. This provides our customers with a powerful solution for researching new material combinations for future semiconductor devices. Its micron-level alignment capability also makes the EVG ComBond uniquely suited for use in high-volume manufacturing of emerging heterogeneous integration device designs.”

EVG’s breakthrough ComBond wafer activation technology and high-vacuum handling and processing allow the formation of covalent bonds at room or low temperature for fabricating engineered substrates and device structures. The EVG ComBond facilitates the bonding of heterogeneous materials with different lattice constants and coefficients of thermal expansion (CTE) as well as the formation of electrically conductive bond interfaces through a unique oxide-removal process. The EVG ComBond maintains a high-vacuum and oxide-free environment throughout the entire bonding process, enabling low-temperature bonding of metals, such as aluminum, that re-oxidize quickly in ambient environments. Void-free and particle-free bond interfaces and excellent bond strength can be achieved for all material combinations.