Category Archives: Wafer Level Packaging

Crosstalk and noise can become a major source of reliability problems of CNT based VLSI interconnects in the near future. Downscaling of component size in integrated circuits (ICs) to nanometer scale coupled with high density integration makes it challenging for researchers to maintain signal integrity in ICs. There are high chances of occurrence of crosstalk between adjacent wires. This crosstalk in turn, will increase the peak noise in the transient signals that pass through the interconnects. As multiple occurrences of crosstalk happen, the noise propagates through multiple stages of wires and the problem worsens to logic failure.

But thanks to semiconducting CNTs, which till now have found applications in the fabrication of futuristic field effect transistors, when placed around an interconnect, can reduce crosstalk to a large extent. Basically, semiconducting CNTs are non-conducting, have small dielectric constant, medium to large band gaps and hence can act as insulating shields to electric fields.

As semiconducting CNTs are one dimensional nanowires, they have very high anisotropic properties along their axis as well as their radius. The dielectric polarizability, which is the measure of number of polarizable bonds in a material, is found to be very smaller along the CNT radius compared to its axis. So, semiconducting CNTs are less polarizable along their radius which further suggests that they have small dielectric constants. The famous Clausius-Mossotti relation can be used to derive the dielectric constant from the dielectric polarizability. Further, this relation also tells that the dielectric constant of a CNT increases with its radius. So, obviously small diameter semiconducting CNTs are the ideal candidates as the low-k dielectric medium between two CNT interconnects.

The contact geometry is modified in such a way that more metal atoms are present at the centre where metallic CNTs are present. The contact has lesser number of metal atoms at the periphery where semiconducting CNTs are present. This helps in building a Schottky barrier at the contact semiconducting CNT interface and hence, inhibits any carrier movement.

Finally, experimental results show that the radial dielectric constant can be as low as 2.82 if (2,2) CNTs are used as shields. The coupling capacitance between adjacent wires is dependent on the interconnect thickness as well as the semiconducting CNT shield thickness. Crosstalk between CNT wires can be reduced by 28% if semiconducting CNTs are used. The crosstalk induced peak noise was also found to be 25% lesser for semiconducting CNT shielded interconnects at different input voltages of 0.8V, 0.5V and 0.3V.

SkyWater Technology Foundry announces that it has been assigned the Specialty Foundry customer relationships from Cypress Semiconductor Corporation. The customer relationships were already being serviced within SkyWater’s 200mm semiconductor wafer manufacturing facility when purchased from Cypress earlier this year. Through the transaction, SkyWater assumes ownership of Cypress’ current embedded Specialty Foundry customer engagements and adds associated business management personnel.

“This transaction builds upon the concept of a Technology Foundry, which enables customers to design, build, and scale their products by simplifying the realization of complex technologies through access to semiconductor technology, experienced personnel and volume manufacturing capabilities,” said SkyWater Chairman of the Board Gary Obermiller. “The addition of the Specialty Foundry customers is synergistic with our pure-play Technology Foundry model; customers come to us with their ideas and we transform them into practice through the application of our differentiated semiconductor technology and operational expertise.”

The Technology Foundry Business model enables customers to design and optimize their product concepts. In tandem with SkyWater’s advanced wafer manufacturing facility, customers are able to prototype and rapidly scale to production volumes, all inside of a high-yield production fab.

“The Specialty Foundry Business was created in 2008 with the vision of providing advanced development access to a high-volume production-scale fab, building on the site’s proven track record of success in bringing new technologies to production,” said Michael Moore, executive vice president of Sales and Marketing at SkyWater. “It’s in our DNA. We’ve been doing development work at this site for decades, right alongside production.  This move is a natural next step for the company and our customers.  We have successfully diversified the customer base this way, by serving new and unique markets that are poised for rapid growth.”

As part of the assignment, which closed October 2, SkyWater will now have direct responsibility for all Specialty Foundry Business customers, eliminating the prior Cypress interface. Because of the existing working relationship between all parties, there will be a seamless transition for all current projects; the same team will continue working with all existing customers, the only difference being that they are now SkyWater employees.

Within SkyWater’s manufacturing facility there are a wide variety of unique technologies currently being developed and manufactured – from superconducting quantum computers to advanced technology Readout IC’s (ROIC), MEMS-based infrared imagers, DNA sequencing and fabrication platforms, and photonic integrated circuit (PIC) devices.

According to SkyWater’s Senior Director of Sales Brad Ferguson, “These types of Technology engagements just start with a simple conversation about our capabilities, and once Customers see the potential of our Technology Foundry solution, they realize this is the right place to transform their concepts into a manufactured product.”

SkyWater is a U.S.-based technology foundry specializing in the development and manufacturing of a wide variety of semiconductor based solutions.

IC Insights has revised its outlook for semiconductor industry capital spending and will present its new findings in the November Update to The McClean Report 2017, which will be released at the end of this month.  IC Insights’ latest forecast now shows semiconductor industry capital spending climbing 35% this year to $90.8 billion.

After spending $11.3 billion in semiconductor capex last year, Samsung announced that its 2017 outlays for the semiconductor group are expected to more than double to $26 billion.  Bill McClean, president of IC Insights stated, “In my 37 years of tracking the semiconductor industry, I have never seen such an aggressive ramp of semiconductor capital expenditures.  The sheer magnitude of Samsung’s spending this year is unprecedented in the history of the semiconductor industry!”

Figure 1 shows Samsung’s capital spending outlays for its semiconductor group since 2010, the first year the company spent more than $10 billion in capex for the semiconductor segment.  After spending $11.3 billion in 2016, the jump in capex expected for this year is simply amazing.

To illustrate how forceful its spending plans are, IC Insights anticipates that Samsung’s semiconductor capex of $8.6 billion in 4Q17 will represent 33% of the $26.2 billion in total semiconductor industry capital spending for this quarter.  Meanwhile, the company is expected to account for about 16% of worldwide semiconductor sales in 4Q17.

IC Insights estimates that Samsung’s $26 billion in semiconductor outlays this year will be segmented as follows:

3D NAND flash: $14 billion (including an enormous ramp in capacity at its Pyeongtaek fab)

DRAM: $7 billion (for process migration and additional capacity to make up for capacity loss due to migration)

Foundry/Other: $5 billion (for ramping up 10nm process capacity)

annual samsung capex

IC Insights believes that Samsung’s massive spending outlays this year will have repercussions far into the future. One of the effects likely to occur is a period of overcapacity in the 3D NAND flash market. This overcapacity situation will not only be due to Samsung’s huge spending for 3D NAND flash, but also to its competitors in this market segment (e.g., SK Hynix, Micron, Toshiba, Intel, etc.) responding to the company’s spending surge.  At some point, Samsung’s competitors will need to ramp up their capacity or loose market share.

Samsung’s current spending spree is also expected to just about kill any hopes that Chinese companies may have of becoming significant players in the 3D NAND flash or DRAM markets.  As our clients have been aware of for some time, IC Insights has been extremely skeptical about the ability of new Chinese startups to compete with Samsung, SK Hynix, and Micron with regards to 3D NAND and DRAM technology.  This year’s level of spending by Samsung just about guarantees that without some type of joint venture with a large existing memory suppler, new Chinese memory startups stand little chance of competing on the same level as today’s leading suppliers.

SEMICON Europa 2017 will take place in Munich from 14 to 17 November, co-located with productronica. Consistent with SEMI’s theme “Connect, Collaborate, and Innovate,” co-locating SEMICON Europa with productronica gathers the full span of electronics manufacturing and end-products, creating the largest European electronics platform ever. More than 400 exhibitors will present their products and innovations at SEMICON Europa 2017. Over 40,000 attendees are expected at the co-located events.

After a period of slow growth, Europe’s semiconductor manufacturers are investing in new construction of 300mm fabs in Germany, Italy and France. Four semiconductor and MEMS manufacturers have announced investments in Europe totaling more than $10 billion. Bosch will build a new fab in Dresden; ST Microelectronics is planning two new 300mm fabs in Agrate and Crolles; and GLOBALFOUNDRIES and Infineon plan to expand their production capacity.

“The global industry will invest more than US$100 billion in equipment and materials this year. Forecasts for 2017 also predict that semiconductor manufacturers worldwide will exceed $400 billion in revenue ─ a new record,” says Ajit Manocha, president and CEO of SEMI.  “An unprecedented number of new inflections and applications will broadly expand the digital economy and drive increasing silicon content — in areas including IoT, assisted driving in automotive, Artificial Intelligence (AI), Big Data, and 5G. Assuming an average 7 percent CAGR, global chip sales could approach $1 trillion by 2030, and equipment and materials spending could similarly grow to nearly a quarter of a trillion dollars.”

The market segments in which European companies hold strong market positions also shape the conference program of SEMICON Europa 2017. More than 250 presentations, 50 conferences and high-caliber discussions provide an overview of current trends. Key issues this year include: materials, semiconductor manufacturing, advanced packaging, MEMS/sensors, power electronics, flexible and printed electronics. The focus is also on important applications such as the Internet of Things (IoT) and artificial intelligence (AI), smart manufacturing (“Industry 4.0”), automotive electronics and medical technology.

The Opening Ceremony will include a welcome speech by Ajit Manocha, president and CEO of SEMI,followed by Laith Altimime, president, SEMI Europe, plus four keynotes:

  • Bosch Sensortec: Stefan Finkbeiner, CEO, on how environmental sensing can contribute to a better quality of life in the context of the IoT
  • Rinspeed Inc.: Frank M. Rinderknecht, founder and CEO, on how to create innovative technologies, materials and mobility means of tomorrow
  • SOITEC: Carlos Mazure, CTO, executive VP, on contributions and benefits of engineered substrates solutions and thin-layer transfer technologies, focusing on applications in the smart space
  • TSMC Europe: Maria Marced, president, on opportunities for new business models to apply in the Smart City

On the exhibition show floor, the TechARENA free sessions are a highlight with the SEMI China Innovation and Investment Forum and the INNOVATION VILLAGE.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, and Leti, an institute of CEA Tech, today announced the world’s first successful 300-mm wafer-to-wafer direct hybrid bonding with pitch dimension connections as small as 1µm (micron). This breakthrough also achieved copper pads as small as 500nm.

The copper/oxide hybrid bonding process, a key enabler for 3D high-density IC applications, was demonstrated in Leti’s cleanrooms using EVG’s fully automated GEMINI FB XT fusion wafer bonding system. This result was obtained in the framework of the program IRT Nanoelec headed by Leti. EVG joined the institute’s 3D Integration Consortium in February 2016.

Wafer bonding an enabling process for 3D device stacking

Vertical stacking of semiconductor devices has become an increasingly viable approach to enabling continuous improvements in device density and performance. Wafer-to-wafer bonding is an essential process step to enable 3D stacked devices. However, tight alignment and overlay accuracy between the wafers is required to achieve good electrical contact between the interconnected device on the bonded wafers, as well as to minimize the interconnect area at the bond interface so that more space can be made available on the wafer for producing devices. The constant reduction in pitches that are needed to support component roadmaps is fueling tighter wafer-to-wafer bonding specifications with each new product generation.

Demonstration results

In the Leti demonstration, the top and bottom 300mm wafers were directly bonded in the GEMINI FB XT automated production fusion bonding system, which incorporates EVG’s proprietary SmartView NT face-to-face aligner and an alignment verification module to enable in-situ post-bond IR alignment measurement. The system achieved overlay alignment accuracy to within 195nm (3-sigma) overall, with mean alignment results well centered below 15nm. Post-bake acoustic microscopy scans of the full 300mm bonded wafer stack as well as specific dies confirmed a defect-free bonding interface for pitches ranging from 1µm to 4µm with optimum copper density.

Focused Ion Beam Scanning Electron Microscope (FIB-SEM) cross-section of 1-µm pitch copper pads on a pair of 300-mm wafers bonded with the GEMINI®FB XT automated production fusion bonding system from EV Group. Photo courtesy of Leti.

Focused Ion Beam Scanning Electron Microscope (FIB-SEM) cross-section of 1-µm pitch copper pads on a pair of 300-mm wafers bonded with the GEMINI®FB XT automated production fusion bonding system from EV Group. Photo courtesy of Leti.

“To our knowledge, this is the first reported demonstration of sub-1.5µm pitch copper hybrid bonding feasibility,” said Frank Fournel, head of bonding process engineering at Leti. “This latest demonstration represents a real breakthrough and important step forward in enabling the achievement and eventual commercialization of high-density 3D chip stacking.”

This demonstration is summarized in a paper co-authored by Leti, titled “1 µm Pitch Direct Hybrid Bonding with with <300nm Wafer-to-wafer Overlay Accuracy,” which was presented at the 2017 IEEE S3S Conference.

“3D integration holds the promise for increased device density and bandwidth as well as lower power consumption for a variety of applications, from next-generation CMOS image sensors and MEMS to high-performance computing,” stated Markus Wimplinger, corporate technology development and IP director at EV Group. “As a leader in 3D integration research and development, Leti has been at the forefront in moving this critical technology toward industry adoption and commercialization. EVG shares that vision, and we are pleased to have played a role in supporting Leti’s latest achievement in 3D integration.”

Leveraging EVG’s high-throughput XT Frame platform and an equipment front-end module (EFEM), the GEMINI FB XT automated production fusion bonding system is optimized for ultra-high throughput and productivity. The SmartView NT aligner integrated into the system provides industry-leading wafer-to-wafer overlay alignment accuracy (sub-200nm, 3-sigma). In addition, the GEMINI FB XT can accommodate up to six pre- and post-processing modules for surface preparation, conditioning and metrology steps such as wafer cleaning, plasma activation alignment verification, debonding (allowing pre-bonded wafers to be separated automatically and re-processed if necessary) and thermo-compression bonding.

EVG will showcase the GEMINI FB XT at the SEMICON Europa exhibition being held November 14-17 at the Messe München in Munich, Germany. Attendees interested in learning more about the product, as well as EVG’s full suite of wafer bonding and lithography solutions, are invited to visit the company’s booth #B1-1424.

A*STAR’s Institute of Microelectronics (IME) has established a development line to accelerate the development of fan-out wafer level packaging (FOWLP) capabilities for next-generation Internet of Things (IoT) technologies. The FOWLP development line, which is built upon existing infrastructure at IME’s facilities at Singapore Science Park II, and its new facilities at Fusionopolis Two, will allow IME and its partners (see Annex A for list of partners) to develop technologies that serve a wide range of markets such as that of consumer electronics, healthcare and automotive.

The IoT is set to become the next growth driver for the semiconductor industry, as demand for internet-connected devices continues to soar. FOWLP is an emerging breakthrough chip packaging technology platform aimed at meeting the technology requirements of next-generation electronic devices that require ultra- low power consumption rates, smaller package profiles, higher performance; and all made at a lower cost.

IME’s FOWLP development line is equipped with fully automated tools that can perform the “mold-first” and “Re-Distribution Layer (RDL)-first” method in multi- chip fabrication. The “RDL-first” method is expected to achieve a higher reliability rate compared to the conventional “mold-first” method traditionally used by the semiconductor industry. IME and its partners will jointly develop tools and processes for next-generation FOWLP technologies such as high speed Copper (Cu) pillar plating, Physical Vapor Deposition (PVD) process to control the wafer warpage, moldable underfilling for Chip-to-Wafer, as well as over molding on wafer with vertical Cu pillar/Cu wire interconnections using wafer level compression molding, plasma descum of small vias and warpage adjustment, etc.

To unlock the potential of FOWLP and accelerate the development and adoption of these innovative process technologies by the industry, IME has also formed a consortium comprising leading OSATs, Materials, Equipment, EDA, Fabless partners (see Annex A for list of consortium members).

The FOWLP development line consortium will allow members across the value chain to co-share resources on an open innovation platform, and draw upon IME’s rich portfolio of advanced packaging capabilities to address the complexities in system scaling and heterogeneous system integration. The FOWLP development line will be a test-bedding platform through which consortium members could gain new insights on requirements of FOWLP by testing and developing new processes, paving the way for high-volume manufacturing.

The FOWLP development line utilises tools already in use in major OSATs, and will allow processes, materials and integration flows developed at IME to be smoothly transferred. Through this development line, fabless companies could also make quicker decisions on package structure, integration flows, processes, materials and equipment for their new products; so materials and equipment suppliers could expedite the development of their products and increase their adoption.

“The launch of IME’s FOWLP development line and consortium will enable us to advance pre-competitive R&D that positions the semiconductor industry for growth opportunities in the thriving IoT market. Through an open and collaborative approach, the consortium will drive the development and the transfer of innovative technologies from pilot-scale to commercial production more easily and quickly,” said Dr. Tan Yong Tsong, Executive Director, IME.

“We are extremely proud to be a part of IME’s FOWLP consortium and play an active role in this great initiative. This broad industry cooperation will help solve one of the largest challenges faced by the semiconductor industry in the area of achieving higher density in advanced packaging. ERS is committed to developing new thermo-management solutions to enable next generation of FOWLP technologies,” said Mr. Klemens Reitinger, Chief Executive Officer, ERS Electronic GmbH.

“We are pleased to be collaborating with IME in this FOWLP development line consortium (DLC). We have benefitted from the experience in the previous consortium on High Density FOWLP, and are confident that with our combined experience and knowledge, the consortium will accelerate the development of FOWLP and establish an innovative cost-effective manufacturing process to further the mass adoption of FOWLP,” said Mr. Tong Liang Cheam, Vice President of Corporate Strategy, Kulicke & Soffa.

“It’s exciting to participate in this new FOWLP development line at IME to advance chip packaging. Nordson has a successful history of working on innovations in the semiconductor packaging industry, and this consortium is positioned well to produce excellent solutions,” said Mr. Joseph Stockunas, Vice President, Advanced Technology – Electronics Systems, Nordson Corporation.

“It is through collaborative efforts, such as that of the FOWLP development line and consortium that the semiconductor ecosystem can advance. Our engagement with the consortium will not only benefit our customers, but the industry as a whole in driving the adoption of this technology for emerging High Bandwidth Memory (HBM) and diverse IoT applications,” said Mr. Asim Salim, Vice President of Manufacturing Operations, Open-Silicon. “Through Open- Silicon’s extensive experience in 2.5D ASIC design, and the expertise of the consortium, issues like cost will be mitigated, thus enabling OEMs of all sizes to adopt FOWLP technology.”

“We are delighted to be a part of IME’s FOWLP development line consortium and continue to play an active role in this open innovation initiative. Industry-wide cooperation is key in overcoming the many challenges faced today by the electronics packaging industry. Orbotech is committed to developing new cost- efficient solutions to enable the next generation of advanced packaging technologies, which in turn will impact the industry’s next inflection point,” said Dr. Abraham Gross, Chief Technology Officer and Head of Innovation, Orbotech.

“As demand for high speed, high bandwidth data connectivity in consumer electronics continues to grow, the performance and cost challenges limiting the implementation of high frequency millimeter wave applications have the potential to be addressed with FOWLP solutions. We look forward to working with the FOWLP development line consortium to realise the benefits of FOWLP technology for mmWave antennae devices in emerging markets such as automotive and the Internet of Things (IoT),” said Mr. Shim Il Kwon, Chief Technology Officer, STATS ChipPAC.

The Institute of Microelectronics (IME) is a research institute of the Science and Engineering Research Council of the Agency for Science, Technology and Research (A*STAR).

DARPA’s new initiative


November 8, 2017

BY DR. PHIL GARROU, Contributing Editor

Earlier this year, DARPA’s Microsystems Technology Office (MTO) announced a new Electronics Resurgence Initiative (ERI) “to open pathways for far-reaching improvements in electronics performance well beyond the limits of traditional scaling.” Key to the ERI will hopefully be new collab- orations among the commercial electronics community, defense industrial base, university researchers, and the DoD. The DoD proposed FY 2018 budget reportedly includes a $75 million allocation for DARPA in support of this, initiative. It is reported that in total we are looking at a $200,000MM program.

The program will focus on the development of new materials for devices, new architectures for integrating those devices into circuits, and software and hardware designs for using these circuits. The program seeks to achieve continued improvements in electronics performance without the benefit of traditional scaling. Bill Chappell, director of DARPA’s Microsystems Technology Office (MTO), which will lead the program, announced

“For nearly seventy years, the United States has enjoyed the economic and security advantages that have come from national leadership in electronics innovation…..If we want to remain out front, we need to foment an electronics revolution that does not depend on traditional methods of achieving progress. That’s the point of this new initiative – to embrace progress through circuit specialization and to wrangle the complexity of the next phase of advances, which will have broad implications on both commercial and national defense interests.” He continued: “We need to break away from tradition and embrace the kinds of innovations that the new initiative is all about…”

The chip research effort will complement the recently created Joint University Microelectronics Program (JUMP), an electronics research effort co-funded by DARPA and SRC (Semiconductor Research Corporation). Among the chip makers contributing to JUMP are IBM, Intel Corp., Micron Technology and Taiwan Semiconductor Manufacturing Co. SRC members and DARPA are expected to kick in more than $150 million for the five-year project. Focus areas include high-frequency sensor networks, distributed and cognitive computing along with intelligent memory and storage.

The materials portion of the ERI initiative will explore the use of unconventional materials to increase circuit performance without requiring smaller transistors. Although silicon is used for most of the circuits manufactured today, other materials like GaAs, GaN and SiC have made significant inroads into high performance circuits. It is hoped that the initiative will uncover other elements from the Periodic Table that can provide candidate materials for next-generation logic and memory components. One research focus will be to integrate different semiconductor materials on individual chips, and vertical (3D) rather than planar integration of microsystem components.

The architecture portion of the initiative will examine circuit structures such as Graphics processing units (GPUs), which underlie much of the ongoing progress in machine learning, have already demonstrated the performance improvement derived from specialized hardware architectures. The initiative will explore other opportunities, such as “reconfigurable physical structures that adjust to the needs of the software they support.”

The design portion of the initiative will focus on devel- oping tools for rapidly designing specialized circuits. Although DARPA has consistently invested in these appli- cation-specific integrated circuits (ASICs) for military use, ASICs can be costly and time-consuming to develop. New design tools and an open-source design paradigm could be transformative, enabling innovators to rapidly and cheaply create specialized circuits for a range of commercial applications.

As part of this overall Electronics Resurgence Initiative, DARPA had their kickoff meeting for the CHIPS program (Common Heterogeneous Integration and Intellectual Property (IP) Reuse). The CHIPS vision is an ecosystem of discrete modular, IP blocks, which can be assembled into a system using existing and emerging integration technologies. Modularity and reusability of such IP blocks will require electrical and physical interface standards to be widely adopted by the community supporting the CHIPS ecosystem. The CHIPS program hopes to develop the design tools and integration standards required for modular integrated circuit (IC) designs.

Program contractors include Intel, Micron, Cadence, Lockheed Martin, Northrop Grumman, Boeing, Synopsys, Intrinsix Corp., and Jariet Technologies, U. Michigan, Georgia Tech, and North Carolina State.

Enabling the A.I. era


November 8, 2017

BY PETE SINGER, Editor-in-Chief

There’s a strongly held belief now that the way in which semiconductors will be designed and manufactured in the future will be largely determined by a variety of rapidly growing applications, including artificial intelligence/deep learning, virtual and augmented reality, 5G, automotive, the IoT and many other uses, such as bioelectronics and drones.

The key question for most semiconductor manufacturers is how can they benefit from these trends? One of the goals of a recent panel assembled by Applied Materials for an investor day in New York was to answer that question.

The panel, focused on “enabling the A.I. era,” was moderated by Sundeep Bajikar (former Sellside Analyst, ASIC Design Engineer). The panelists were: Christos Georgiopoulos (former Intel VP, professor), Matt Johnson (SVP in Automotive at NXP), Jay Kerley (CIO of Applied Materials), Mukesh Khare (VP of IBM Research) and Praful Krishna (CEO of Coseer). The panel discussion included three debates: the first one was “Data: Use or Discard”; the second was “Cloud versus Edge”; and the third was “Logic versus Memory.”

“There’s a consensus view that there will be an explosion of data generation across multiple new categories of devices,” said Bajikar, noting that the most important one is the self-driving car. NXP’s Johnson responded that “when it comes to data generation, automotive is seeing amazing growth.” He noted the megatrends in this space: the autonomy, connectivity, the driver experience, and electrification of the vehicle. “These are changing automotive in huge ways. But if you look underneath that, AI is tied to all of these,” he said.

He said that estimates of data generation by the hour are somewhere from 25 gigabytes per hour on the low end, up to 250 gigabytes or more per hour on the high end. or even more in some estimates.

“It’s going to be, by the second, the largest data generator that we’ve seen ever, and it’s really going to have a huge impact on all of us.”

Intel’s Georgiopoulos agrees that there’s an enormous amount of infrastructure that’s getting built right now. “That infrastructure is consisting of both the ability to generate the data, but also the ability to process the data both on the edge as well as on the cloud,” he said. The good news is that sorting that data may be getting a little easier. “One of the more important things over the last four or five years has been the quality of the data that’s getting generated, which diminishes the need for extreme algorithmic development,” he said. “The better data we get, the more reasonable the AI neural networks can be and the simpler the AI networks can be for us to extract information that we need and turn the data information into dollars.” Check out our website at www.solid-state.com for a full report on the panel.

By Ajit Manocha, president and CEO, SEMI

Artificial intelligence (AI) may be a hot topic today, but SEMI has helped to incubate Big Data and AI since its founding. Early in SEMI’s history, SEMI’s always intelligent members worked together to introduce International Standards that enabled different pieces of equipment to collect and later pass data.  At first, it was for basic interoperability and equipment state analysis.  Later, SEMI data protocol Standards allowed process and metrology data to be used locally and across the fab to approach the goals of Smart Manufacturing and AI – for the equipment itself to make adjustments based on incoming wafer data.

Ajit--photo 1--sample.e.XL3A5483 (from pdg)As a part of this evolution, SEMI members developed the latest sensors and computational hardware that could ever better sense, analyze and act on the environment. Often first to use its own newly developed hardware, progress in this area was critical toward improving the likelihood of success for one of the world’s most complicated production processes – and coping with the breakneck speed of Moore’s Law – by accelerating capabilities that would later be regarded as the basis for machine learning and “thinking” systems.

Since then, process steps have increased from about 175 to as many as 1,000 for the leading technology nodes. By the time 300mm wafers were introduced, manufacturing intelligence and automation sharply increased productivity while reducing fab labor by more than 25 percent. Employing adaptive models, modern leading-edge factories are fully automated and operate at nearly 60 percent autonomous control.

Today, AI is akin to where IoT was yesterday in the hype cycle – popping up everywhere as a major consideration for the future. Neither IoT nor AI is hype, though – they’re the future.  There is ever more at stake for SEMI members with AI.  AI appears to be the next wave helping to maintain double-digit growth for the foreseeable future.

As part of its appeal for the global supply chain, AI can be a key silicon driver for three inflections that should benefit society. First, there is a massive increase in the amount of compute needed. Half of all the compute architectures shipping in 2021 will be supporting and processing AI.

Second, the Cloud will flourish and the Edge will bloom. By 2021, 50 percent of enterprise infrastructure will employ cognitive and artificial intelligence.

Third, new species of chips will emerge, such as the devices fueling IC content and electronics for the rapid growth of disruptive capabilities in vehicles and autonomous cars (as well as medical and agricultural applications, for example). There are also many more advantages created with and for AI as SEMI members enable new materials and advanced packaging.

What results can be measured from these changes for the global electronics manufacturing supply chain? More apps, more electronics, more silicon and more manufacturing.

On the other hand, the technologies alone create relatively little business value if the problems in our factories and markets are not well understood. There’s a great need to anticipate and guide AI. This requires a new kind of collaboration.

To address this need, SEMI’s vertical application platforms have been created for Smart Data (which is all about AI), and also for Smart MedTech, Smart Transportation, Smart Manufacturing and IoT. This higher degree of facilitated collaboration serves to cultivate multiple “smart communities” that accelerate progress for AI, better directing how connected networks and data mining can step up the pace for advancement of global prosperity. This process also provides members with access to untapped business opportunities and new players.​​

Ajit--photo 2 (panel)_D512959

We at SEMI are learning right along with our members. If you attended SEMICON West in July, several lessons about AI were presented by the Executive Panel (“Meeting the Challenges of the 4th Industrial Revolutions along the Microelectronics Supply Chain”) with Mary Puma (Axcelis), Shaheen Dayal (Intel), Lori Ciano (Brooks Automation) and Regenia Sanders (Ernst & Young). This very timely and excellent panel discussed how and where predictive analytics can have the biggest impact and the implications of sharing (and not sharing) data for problem solving and process optimization.

Ensuring that the SEMI staff gleans everything possible from the experts, we hosted an “encore” of the Executive Panel in October in our headquarters for an even more in-depth discussion about how to enhance collaboration across the supply chain in support of AI.

Going forward, these SEMI vertical platform communities will help to simplify and accelerate supply chain engagement for member value. Collaboration will play an ever greater role for using AI to master the making of advanced node semiconductor devices and enabling limitless cognitive computing. As a result, AI as we know it today, has a big head start over the previous pace of evolution for one of our great trendsetters, Moore’s Law.

Join the conversation.  Find out how you can work with SEMI to advance the AI – and especially AI in semiconductor manufacturing.  Frank Shemansky Jr., Ph.D., is heading up SEMI’s formation of SEMI’s Smart Data vertical application platform.  Let Frank know ([email protected]) you’re interested and he’ll give you more information on what’s to come.  As always, please let me know your thoughts.

 

The technologies to watch identified by TechInsights analysts at the beginning of the year have not been disappointing.

BY STACY WEGNER, Ottawa, Canada, and JEONGDONG CHOE, Ottawa, Canada

TechInsights analysts have been keeping an intent watch on where technology has progressed, how it’s changing, and what new developments are emerging. At the end of the first quarter, our analysts shared their insights and thoughts about what to keep an eye on as the year unfolds. In this article, they provide an update on what 2017 has delivered so far.

Intelligent, connected devices

As we wrote earlier this year, in 2016, wearables were extremely interesting mainly because there was so much uncertainty around whether or not the market would be viable. Some, no, many, say the wearables market will cool off and possibly just expire. At TechInsights, we do will not speculate about whether this market is going to survive. We will report what we find and analyze what is currently being sold. Apple, Samsung, and Huawei have all released smartwatches for what would parallel a “flagship” in the mobile market (FIGURE 1). Fitness bands are becoming even ”smarter” and combining sensors where possible. Perhaps one of the most notable developments is Nokia’s acquisition and complete integration of Withings into its existing brands.

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We are witnessing the “rise of the machines,” in products from scales and hair brushes to rice cookers. Primarily these devices offer consumers convenience. For example, with a connected scale, instead of recording your weight manually, the smart scales do the job for you, syncing with various health apps so you can track your weight over time. The connected hair brush provides insights into your hair’s manageability, frizziness, dryness, split ends and breakage to provide a hair quality score. Brushing patterns, pressure applied and brush stroke counts are analyzed to measure effectiveness of brushing habits and a personal diagnosis is provided with tips and real-time product recommendations. The most common connected devices include refrigerators, lights, washing machines, thermostats, and televisions.

One dominant example is the ever-popular Amazon Echo, which has taken on a life of its own and is generating spin-off markets and competition. In July, it was reported that Amazon’s Alexa voice platform passed 15,000 skills — the voice-powered apps that run on devices like the Echo speaker, Echo Dot, newer Echo Show and others. The figure is up from the 10,000 skills Amazon officially announced in February. Amazon’s Alexa is building out an entire voice app ecosystem putting it much further ahead than its nearest competitor. The success seen with Echo has motivated other companies like Google, Lenovo, LG, Samsung and Apple to release compet- itive speakers, however it is estimated that Amazon is expected to control 70 percent of the market this year. In addition, Amazon and Microsoft recently announced a partnership to better integrate their digital assistants. This cross-platform integration provides users with access to Cortana features that Alexa is missing, and vice versa. Finally, the high- performance far-field microphones found in Amazon Echo products may soon find their way to other hardware companies as Amazon announced that the technology is available to those who want to integrate into the Alexa Experience. With its new reference solution, it’s never been easier for device makers to integrate Alexa and offer their customers the same voice experiences.

In the mobile market overall, we are seeing a strong emergence of devices targeted for the very hot market of India. The mobile devices for this market range from supporting 15 or more cellular bands to as few as five cellular bands, and that is for smart- phones. At TechInsights, we will be analyzing OEMs in India like Micromax, Intex, and Lava to see how they approach dealing with strong competitors like Samsung and Xiaomi.

Memory devices

In early 2017, 32L and 48L 3D NAND products were common and all the NAND players were eager to develop next generation 3D NAND products such as 64L and 128L. 3D NAND has been jumping into 64L (FIGURE 2). Samsung, Western Digital, Toshiba, Intel, and Micron already revealed CS or mass-products on the market. SK Hynix also showed their 72L NAND die as a CS product. In the second half of this year, we will see 64L and 72L NAND products on the commercial market. For n+1 generation with 96L or 128L, we expect that two-stacked cell array architecture for 3D NAND would be adopted in 2018. Micron/Intel will keep their own FG based 3D NAND cell structure for the next generation.

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Referring to DRAM, all the major players already used their advanced process technology for cell array integration such as an advanced ALD for high-k dielectrics, low damage plasma etching and honeycomb capacitor structure. Buried WL, landing pad and plug for a capacitor node, and MESH structure are still main stream. Samsung 18nm DRAM products for DDR4 and LPDDR4X are on the market. SK Hynix and Micron will reveal the same tech node DRAM products in this year. n+1 gener- ation with 15nm or 16nm node will be next in 2018. Once 6F2 15nm DRAM cell technology is successful, 4F2 DRAM products such as a capacitorless DRAM might be delayed. In 2018, 18nm and 15nm DRAM technology will be used for GDDR6 and LPDDR5.

When it comes to emerging memory, 3D XPoint memory technology is a hot potato (FIGURE 3). The XPoint products from Intel are on the market as an Optane SSD with 16GB and 32GB. Performance including retention, reliability and speed are not matched as expected, but they used a double stacked memory cell between M4 and M5 on the memory array. It’s a PCM with GST based material. An OTS with Se-As-Ge-Si is added between the PCM and the electrode (WL or BL). We expect to see multiple (triple or quadruple) stacked XPoint memory architecture within a couple years. For other emerging memory such as STT-MRAM, PCRAM and ReRAM, we’re waiting on some commercial products from Adesto (CBRAM 45nm, RM33 series) and Everspin (STT-MRAM pMTJ 256Mb, AUP-AXL-M128).

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Conclusion

The technologies to watch identified by TechInsights analysts at the beginning of the year have not been disappointing. As our analysts continue to examine and reveal the innovations others can’t inside advanced technology, we will continue to share our findings on these and new technologies as they emerge, including how they are used, how they impact the market, and how they will be changed by the next discovery or invention.