Category Archives: Wafer Level Packaging

Monthly semiconductor sales reach $35B globally for first time in August

October 4, 2017

The Semiconductor Industry Association (SIA) today announced worldwide sales of semiconductors reached $35.0 billion for the month of August 2017, an increase of 23.9 percent compared to the August 2016 total of $28.2 billion and 4.0 percent more than the July 2017 total of $33.6 billion. All major regional markets posted both year-to-year and month-to-month increases in August, and the Americas market led the way with growth of 39.0 percent year-to-year and 8.8 percent month-to-month. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Global semiconductor sales were up significantly in August, increasing year-to-year for the thirteenth consecutive month and reaching $35 billion for the first time,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Sales in August increased across the board, with every major regional market and semiconductor product category posting gains on a month-to-month and year-to-year basis. Memory products continue be a major driver of overall market growth, but sales were up even without memory in August.”

Year-to-year sales increased in the Americas (39.0 percent), China (23.3 percent), Asia Pacific/All Other (19.5 percent), Europe (18.8 percent), and Japan (14.3 percent). Month-to-month sales increased in the Americas (8.8 percent), China (3.7 percent), Japan (2.8 percent), Asia Pacific/All Other (2.2 percent), and Europe (0.6 percent).

“With about half of global market share, the U.S. semiconductor industry is the worldwide leader, but U.S. companies face intense global competition,” said Neuffer. “To allow our industry to continue to grow and innovate here at home, policymakers in Washington should enact corporate tax reform that makes the U.S. tax system more competitive with other countries. The corporate tax reform framework released last week by leaders in Congress and the Trump Administration is an important step forward. We look forward to working with policymakers to enact corporate tax reform that strengthens our industry and the U.S. economy.”

Aug 2017
Billions
Month-to-Month Sales
Market	Last Month	Current Month	% Change
Americas	6.94	7.55	8.8%
Europe	3.20	3.22	0.6%
Japan	3.04	3.13	2.8%
China	10.68	11.08	3.7%
Asia Pacific/All Other	9.77	9.98	2.2%
Total	33.63	34.96	4.0%

Year-to-Year Sales
Market	Last Year	Current Month	% Change
Americas	5.43	7.55	39.0%
Europe	2.71	3.22	18.8%
Japan	2.73	3.13	14.3%
China	8.99	11.08	23.3%
Asia Pacific/All Other	8.35	9.98	19.5%
Total	28.22	34.96	23.9%

Three-Month-Moving Average Sales
Market	Mar/Apr/May	Jun/Jul/Aug	% Change
Americas	6.27	7.55	20.5%
Europe	3.11	3.22	3.8%
Japan	2.95	3.13	6.0%
China	10.25	11.08	8.1%
Asia Pacific/All Other	9.43	9.98	5.9%
Total	31.99	34.96	9.3%

Robotics and chip industries in Japan

October 2, 2017

By Yoichiro Ando, SEMI Japan

Shinzo Abe, the prime minister of Japan, plans to stage a Robot Olympics in 2020 alongside the summer Olympic Games to be hosted in Tokyo. Abe said he wants to showcase the latest global robotics technology, an industry in which Japan has long been a pioneer. Japan’s Robot Strategy developed by the Robot Revolution Initiative Council plans to increase Japanese industrial robot sales to 1.2 trillion JPY by 2020. This article discusses how the robotics industry is not just a key pillar of Japan’s growing strategy but also a key application segment that may lead Japan’s semiconductor industry growth.

Japan leads robotics industry

According to International Federation of Robotics (IFR), the 2015 industrial robot sales increased by 15 percent to 253,748 units compared to the 2014 sales. Among the 2015 record sales, Japanese companies shipped 138,274 units that represent 54 percent of the total sales according to Japan Robot Association (JARA). The robotics companies in Japan include Yaskawa Electric, Fanuc, Kawasaki Heavy Industries, Fujikoshi and Epson.

Source: International Federation of Robotics (global sales) and Japan Robot Association (Japan shipment)

The automotive industry was the most important customer of industrial robots in 2015 that purchased 97,500 units or 38 percent of the total units sold worldwide. The second largest customer was the electrical/electronics industry (including computers and equipment, radio, TV and communication devices, medical equipment, precision and optical instruments) that showed significant growth of 41 percent to 64,600 units.

Semiconductors devices used in robotics industry

Robotics needs semiconductor devices to improve both performance and functionality. As the number of chips used in a robot increases and more advanced chips are required, the growing robotics market is expected to generate significant semiconductor chip demands.

Semiconductor devices in robots are used for collecting information; information processing and controlling motors and actuators; and networking with other systems.

Sensing Devices: Sensors are used to collect information including external information such as image sensors, sound sensors, ultrasonic sensors, infrared ray sensors, temperature sensors, moisture sensors and pressure sensors; and movement and posture of the robot itself such as acceleration sensors and gyro sensors.
Enhancing these sensors’ sensitivity would improve the robot performance. However, for robot applications, smaller form factors, lighter weight, lower power consumption, and real-time sensing are also important. Defining all those sensor requirements for a specific robot application is necessary to find an optimal and cost-effective sensor solution.

In addition, noise immunity is getting more important in selecting sensors as robot applications expand in various environments that include noises. Another new trend is active sensing technology that enhances sensors’ performance by actively changing the position and posture of the sensors in various environments.
Data Processing and Motor Control Devices: The information collected by the sensors is then processed by microprocessors (MPUs) or digital signal processors (DSPs) to generate control signals to the motors and actuators in the robot. Those processors must be capable of operating real-time to quickly control the robot movement based on processed and analyzed information. To further improve robot performance, new processors that incorporate artificial intelligence (AI) and ability to interact with the big data cloud database are needed.

As robotics is adapted to various industry areas as well as other services and consumer areas, the robotics industry will need to respond to multiple demands. It is expected that more field programmable gate arrays (FPGAs) will be used in the industry to manufacture robots to those demands.
In the control of motors and actuators, power devices play important roles. For precise and lower-power operation of the robot, high performance power devices using high band gap materials such as Silicon Carbide and Gallium Nitride will likely used in the industrial applications.
Networking Devices: Multiple industrial robots used in a production line are connected with a network. Each robot has its internal network to connect its components. Thus every robot is equipped with networking capability as a dedicated IC, FPGA or a function incorporated in microcontrollers.

Smart Manufacturing or Industry 4.0 requires all equipment in a factory to be connected to a network that enables the machine-to-machine (M2M) communication as well as connection to the external information (such as ordering information and logistics) to maximize factory productivity. To be a part of such Smart Factories, industrial robots must be equipped with high-performance and high-reliability network capability.

Opportunities for semiconductor industry in Japan

Japanese semiconductor companies are well-positioned in the key semiconductor product segments for robotics such as sensors, microcontrollers and power devices. These products do not require the latest process technology to manufacture and can be fabricated on 200mm or smaller wafers at a reasonable cost. Japan is the region that holds the largest 200mm and smaller wafer fab capacity in the world and the lines are quite versatile in these product categories.

The robotics market will likely be a large-variety and small-volume market. Japanese semiconductor companies will have an advantage over companies in other regions because they can collaborate with leading robotics companies in Japan from early stages of development. Also, Japan may lead the robotics International Standards development which would be another advantage to Japanese semiconductor companies.

For more information about the robotics and semiconductor, attend SEMICON Japan on December 13 to 15 in Tokyo. Event and program information will be available at www.semiconjapan.org soon.

New 3D packaging & integration committee

October 2, 2017

By James Amano, International Standards, SEMI

The SEMI International Standards Committee, at their SEMICON West 2017 meeting, approved the transformation of the existing 3D Stacked IC Committee and Assembly & Packaging Committee into a single, unified 3D Packaging and Integration Committee. Emerging technologies will be accommodated into the scope of the new committee, as North American TC Chapter Co-Chair Sesh Ramaswami (Applied Materials) explains: “Multi-die integration, horizontally and vertically, leveraging substrate, fan-out, interposer and TSV technology is our future. Hence, the new charter and scope will enable the committee to be of more value to the industry.”

Charter:

To explore, evaluate, discuss, and create consensus-based specifications, guidelines, test methods, and practices that, through voluntary compliance, will:

include the materials, piece parts, and interconnection schemes, and unique packaging assemblies that provide for the communication link between the semiconductor chip and the next level of integration, either single- or multi-chip configurations. It relates to the technologies for heterogeneous and other multi-chip packaging such as Fan-out/Fan-in Wafer Level Packaging, Panel Level Packaging, Three-Dimensional Stacking IC, device embedded packaging, flexible electronics technology
promote mutual understanding and improved communication between users and suppliers, equipment, automation systems, devices, and services
enhance the manufacturing efficiency, capability and shorten time-to-market and reduce manufacturing cost

Scope:

To develop standards for semiconductor devices, including processed wafers, chips, or multi-chip configurations to the next level of integration, either in single- or multi-chip configurations.

materials needed for 3D applications, including prime silicon and glass wafers, temporary and permanent bonding material, specifications needed for processed wafers and/or chips to enter an integration step, etc.
the materials related to the elements of, interconnection schemes, and unique packaging assemblies that provide for the communication link between device and packaging.
the technologies for heterogeneous and other multi-chip packaging such as Fan-out/Fan-in Wafer Level Packaging, Panel Level Packaging, Three-Dimensional Stacking IC, device embedded packaging, and flexible electronics technology
metrologies to support these 3D integration and packaging technologies

Masahiro Tsuriya (iNEMI), Japan Co-Chair, further emphasizes “The new 3D Packaging & Integration Committee will be able to contribute to the advance of new, innovative semiconductor packaging technologies.”

The global committee currently has chapters active in Japan, North America, and Taiwan, which all meet throughout the year. To get involved, please join the SEMI International Standards Program at: www.semi.org/standardsmembership.

Itâs gonna be a bright, bright sun-shiny day

September 26, 2017

BY ARABINDA DAS and JUN LU, TechInsights, Ottawa, ON

Last year was a great year for photovoltaic (PV) technology. According to Renewable Energy World magazine, since April 2016, 21 MW of solar PV mini-grids were announced in emerging markets [1]. The exact numbers of installed solar grids for 2016 has not been published yet but looking at the data for 2015, the PV industry is growing, helped by the $/watt for solar panels continuing to drop. The $/watt is obtained by taking the ratio of total cost of manufacturing and the number of watts generated. According to the Photovoltaic Magazine, the PV market continued to grow worldwide in 2015. The magazine also makes reference to the newly published report by the International Energy Agency Photovoltaic Power System (IEA PVPS) programme’s “Snapshot of Global Photovoltaic Markets 2015,” which also states that the total capacity around the globe has crossed the 200 GW benchmark and is continuing to grow [2]. This milestone of 200 GW in installed systems is a remarkable achievement and makes us think of the amazing journey of PV technology. The technology was born in Bell Labs, around 1954, with a solar cell efficiency of just 4% [3]. By the end of the 20th century, the overall solar cell efficiency was close to 11% and the worldwide installed capacity of PV was only 1 GW [3]. Today, seventeen years later, it has soared to 200 GW, with single junction cells having efficiencies around 20% [2].

Si-based solar cells

To celebrate this important milestone, we put TechInsights’ analysis and technical databases to work to investigate the structure of solar cells of two leading manufacturers and compare them to earlier technologies. We chose to analyze Si-based solar cells only, as they represent over 85% of the global market. According to the 2016 IHS Markit report, the top three PV module suppliers in the world are Trina Solar, SunPower, and First Solar [4]. We procured panels from Trina Solar, a Chinese based company, and SunPower, an American company, and carried out a structural analysis of these panels. These analyses helped us take a snapshot of current PV technology. We compared these two types of panels with an older panel from our database. This panel is about eight years old and was made by Kaneka (Japan). We will provide an overview of each panel and their underlying structure.

Table 1 consolidates some of the important param- eters of the three panels. The SunPower panel is based on monocrystalline silicon and the Trina solar panels are based on polycrystalline silicon. The older Kaneka panel is based on amorphous Si thin film technology. The panel from Kaneka is an earlier product; their recent products are made using hybrid technology, a combination of amorphous films and polycrystalline substrates, The Kaneka panel complements very well the other two products which are based on Si crystalline wafers. The technology to fabricate the solar cells (thin film, multi-crystalline or mono-crystalline) has a direct impact on the efficiency of the cells and on their electrical parameters like the open circuit voltage (Voc) and the short circuit current (Isc), as can be seen in Table 1. This table also shows that the Kaneka thin-film based panel has the lowest nominal power among the three. The ratio of nominal power to the light power that is received by the PV panel is indicative of its efficiency. It can be seen also that Kaneka’s thin film panel has the highest open circuit voltage which is the maximum voltage available from the solar cell without any load connected to it.

Table 1 indicates that SunPower is the only one among the three that uses an n-type substrate and has the highest solar efficiency. SunPower has the lowest weight per meter-square of all the panels assessed (9.3kg).

Unlike SunPower panels, most installed Si solar panels employ a p-type substrate, even though the first silicon-based solar cells developed at Bell Labs were based on n-type Si substrates [3]. Researchers J. Libal and R. Kopecek posit that the industry transitioned to p-type substrates because the initial usage of solar cells was in space applications and p-type wafers demonstrated less degradation in the presence of cosmic rays. They suggest that for terrestrial applications there is growing evidence that n-type based solar panels are preferred over p-type based panels [5]. The reasons for choosing n-type Si substrates rather than p-type substrates are because the former are less sensitive to metallic impurities and thus are less expensive to fabricate. In general, the minority carrier diffusion lengths in n-type substrates are higher than p-type Si substrates. Also, n-type Si substrates can withstand higher processing temperatures than p-type substrates, which are prone to boron diffusion. According to the International Technology Roadmap for Photovoltaic (ITRPV), n-type based substrates will increase in prevalence and may eventually replace the p-type monocrystalline Si cells [6].

Thin film based solar panels are very different from monocrystalline Si cells. Thin film cells have the lowest efficiency and yet they too have a role to play in the PV industry. They are the most versatile; they can be coated on different substrates such as glass, plastic or even flexible substrates. The other big advantage of amorphous solar films is that they can be manufac- tured in a range of shapes, even non-polygonal shapes, thus they can be used in various applications. Also, thin film solar panels are not affected by high temper- atures, unlike crystalline solar panels. Thin film based panels made from amorphous Si are more effective for wavelengths between 400 nm to 700 nm, which is also the sensitive spectrum of the human eye; thus they can be used as light sensors [7]. Usually, thin film panels are almost half the price of monocrystalline panels. Amorphous silicon solar cells only require 1% of the silicon used in crystalline silicon solar cells [7].

Multi-crystalline (MC) solar panels are also cheaper than monocrystalline solar panels. MC panels are made by melting raw silicon and confining them into square molds, where they are cooled. This MC-Si process does not require the expensive Czochralski process. In the early days, the cost of fabrication of MC-Si panels was higher than thin film based panels. Now, due to the major advances in fabrication technologies, these panels often have the best $/ watt, which represent the ratio of cost to manufacture to energy output [8]. It is difficult to compare $/watt directly from different manufacturers and different types of solar panels as the technology is manufacturing is changing rapidly and often the most recent products of a manufacturer are not compared. A more sensible factor of comparison would be the ratio of total kilowatt-hours the system generates in its lifetime divided by the cost per square unit of the panel. To make a detailed estimation even the installation cost and tolerance to shade, overall reliability must be included in the calculations, which is beyond the scope of this article.

Solar panel overview

FIGURE 1 shows the panel from Kaneka. It indicates that the Kaneka solar panel cells are long strips that run across the whole length of the panel. The color of the panels is a shade of purple. The Kaneka Solar which is amorphous Si-based, has a very uniform color. The inherent structure of amorphous Si-films has many structural defects because they are not crystalline and thus are tolerant to other defects like impurities during manufacturing, unlike crystalline based panels [7]. The color of the thin film panels is strongly thickness dependent because thickness affects the light absorption. A solar cell’s outward appearance can range from blue to black and is dependent on the absorption and reflectivity of their surface. Ideally, if the cell absorbs all the light impinging on the surface it should be black. FIGURE 2 shows the panels from Trina solar and Sunpower. The Trina Solar panel has a blueish color and each cell is perfectly square. The SunPower SPR-X20- 250-BLK solar cell has a uniform blackish color. The spacing between the cells, the interconnect resis- tance, the top contacts and the materials used for the connections affect the overall performance of the panel. All three manufacturers connect their cells within a PV module and PV modules within an array in a series configuration.

Table 2 summarizes the cell dimensions for the three manufacturers. Kaneka panels have the narrowest space (0.55mm) between the cells. The Trina solar panel has a 3 mm wide gap and a 5 mm gap, between two adjacent solar cells, in the horizontal and vertical direction respectively. These gaps are used for bus electrodes. In the SunPower solar panel, the metal grid is placed on the back surface eliminating metal finger width as a layout constraint. This design significantly reduces the finger resistance and improves the series resistance.

For all panels, interconnects are made between the cells. The metallization and interconnects between the cells is a field of technology on its own. There are various techniques like lithography, laser grooving and printed contacts and these details are discussed more in detail elsewhere [9, 10, 11].

Solar panel cross-sections

In this section, we look into the layers deposited on the substrates. Cross-sectioning these big panels is not a trivial feat. These panels are covered with tempered glass and shatter during sawing and cross-sectioning. To extract a small rectangular piece requires patience and involves sawing and grinding processes. In most cases, the glass was removed before doing the cross-section. FIGURE 3 illustrates two SEM cross-sectional images and one schematic drawing. The SEM cross-sectional images show the top and bottom part of the Kaneka solar cell. In figure 3(a), the active layers comprise indium- tin- oxide, an amorphous silicon layer capped with zinc oxide, silver and a very thin layer of Ni-Al. On top of the Ni-Al film, solder is deposited. Ni-Al provides better adhesion to solder. Two electrical contacts are made between the cells, one to the indium-tin-oxide for the back contact and the other to the Ni-Al layer. Figure 3(b) exposes the layers under the glass substrate. The rear surface of the glass substrate is covered by a soft material such as EVA (ethyl-vinyl-acetate), which in turn is covered by a rear Polyvinyl Fluoride (PVF) layer called the backsheet (Tedlar or similar). EVA is also used on the top surface (figure 3(a)). The usage of these layers is standard practice in the PV industry. The main function of these layers is that they are impervious to moisture and are stable under prolonged exposure to sunlight. On the front side, EVA also helps to reduce reflection and provides good adhesion between the top glass and the solar panels. Figure 3(c) shows the complete stack in the Kaneka solar cell.

FIGURE 4 presents the stack of materials on the multi- crystalline substrate of the Trina Solar panel. The substrate is p-type and has a very thin phosphorous doped region near the top surface. This n-doped region forms the PN junction. A silicon nitride anti-reflective coating layer is deposited on top of the substrate and in designated areas the passivation is opened and silver is deposited to make electrical contact to the n-doped regions. At the bottom of the multi-crystalline substrate, there is also a thin region of high p-doping concentration and this forms the back surface field layer. This solar cell module is fabricated using passivated emitter and full metal back-surface-field (BSF) technology. BSF technology is implemented to mitigate rear surface recombination and this is done by doping heavily at the rear surface of the substrate. This high doping concentration keeps minority carriers (electrons) away from the rear contact because the interface between the high and low doped areas of same conductivity acts like a diode and restricts the flow of the minority carriers to the rear surface. Passivated emitters in the front side and BSF layer on the rear side improve the efficiency of the cells. Figure 3(b) is the schematic repre- sentation of the cell without the EVA and PVF layers.

FIGURE 5 shows an optical cross-section of the SunPower cell. Figure 5(a) shows that SunPower employs a backside junction technology with interdigitated backside p-emitter and n-base metal. This means that both the contact’s n and p-electrodes are at the bottom of the substrate and are placed in in an alternating manner. Having all the metal contacts on the rear side has two big advantages:

1. Metallic contacts are reflective and occupy space that can be used to collect more sunlight; transferring these contacts to the rear side improves the cell efficiency and also leaves the front surface with a uniformly black color, which is more aesthetic for the home users.

2. It reduces bulk recombination. The mono-crystalline substrate is only 120 μm thick. It is designed so that the carrier is generated close to the junction. The substrate is n-type and p-electrodes are formed by localized doping on the bottom part of the substrate.

Figure 5(b) illustrates the general structure of the cell.

FIGURE 6 depicts a SEM cross-section of the metal fingers that connect to the interdigitated electrodes. The pitch between the metal fingers is 920 um and repeats over the entire back surface of the panel.

All three manufacturers employ some sort of surface texturing along with anti-reflective coatings to reduce reflection but SunPower uses the most advanced technology for surface texturing. FIGURE 7 illustrates a SEM topographical image of the front surface texture of the monocrystalline substrate having pyramids, which are etched into the silicon surface. These faceted surfaces increase the probability of reflected light entering back to the surface of the substrate. A similar concept is also applied to the back surface.

The future is sunny and bright

Of the three panels we analyzed, SunPower solar panels employ the most advanced technologies and they illustrate how the solar cell has evolved over the ages. It started from a simple PN junction, then passivated emitters were intro- duced along with local back-surface-field (BSF) technology, which came to be known as Passivated-Emitter with Rear Locally (PERL) diffused technology. In contrast, today the most advanced technology is interdigitated back contacts along with passivated contacts.

In addition to these advances, there is great progress in tandem cells and multi-junctions to capture the different wavelength regions of the sun’s rays. A recent article in IEEE spectrum magazine presented the state of art of record-breaking PV cells made with different techniques such as thin film, crystalline Si, single junction, multi-junction cells. PV cells especially the multi-junction cells, have now crossed the 50% efficiency barrier [12]. Similarly, a publication from the alterenergy.org has collected all the major advances made in PV technology and discusses concepts like colloidal quantum dots and GaAs for cell technology, along with new applications [13]. Today, we regularly read about new materials (like perovskites) and come across new techniques that improve solar panel efficiencies, including new manufacturing methods to reduce the overall cost of fabrication. Moreover, PV cells are used in an innovative manner. The installation of PV panels is no more restricted to isolated rooftops or solar farm. An article in the Guardian made a reference to a solar panel road in Normandy, France [14]. At TechInsights, we will continue to keep an eye on emerging solar cell technologies.

The efforts emerging from various organizations all over the world are very encouraging. There are indeed many challenges for renewable energy to overcome before fiscal parity with fossil fuels is achieved; particularly for PV energy. Nevertheless, there is an increased focus on climate change issues. This has resulted in a significant amount of resources being allotted to PV technology in many countries, especially in developing countries such as China, India, and Brazil [1, 2]. This optimistic scenario reminds us of the song “I Can See Clearly Now” by the 1970s American singer Johnny Nash, where the refrain runs optimistically, “It’s gonna be a bright, bright sun-shiny day.”

References

1. http://www.renewableenergyworld.com/articles/2017/01/21-mw- of-solar-pv-for-emerging-market-community-mini-grids-announced- since-april.html;
2. http://www.pv-magazine.com/news/details/beitrag/iea-pvps— installed-pv-capacity-at-227-gw-worldwide_100024068/#ixzz4MB1 a44hq
3. The history of solar: https://www1.eere.energy.gov/solar/pdfs/solar_ timeline.pdf
4. http://news.ihsmarkit.com/press-release/technology/ihs-markit- names-trina-solar-sunpower-first-solar-hanwha-q-cells-and-jinko-
5. www.pv-tech.org/guest…/n_type_silicon_solar_cell_technology_ ready_for_take_off
6. http://www.itrpv.net/; http://www.itrpv.net/Reports/Downloads/2016/ 7. http://www.solar-facts-and-advice.com/amorphous-silicon.html
8. http://energyinformative.org/solar-cell-comparison-chart-mono-
polycrystalline-thin-film/
9. RP_0706-14839-O-4CS-11Kaneka
10. RP_0616-41931-O-5SA-100_Trina
11. RP_0716-42662-O-5SA-100_SunPower
12. http://spectrum.ieee.org/green-tech/solar/what-makes-a-good-pv-
technology
13. http://www.altenergy.org/renewables/solar/latest-solar-technology.
html
14. https://www.theguardian.com/environment/2016/dec/22/solar-panel-
road-tourouvre-au-perche-normandy

North American semiconductor equipment industry posts August 2017 billingsÂ

September 22, 2017

North America-based manufacturers of semiconductor equipment posted $2.18 billion in billings worldwide in August 2017 (three-month average basis), according to the August Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI.

SEMI reports that the three-month average of worldwide billings of North American equipment manufacturers in August 2017 was $2.18 billion.The billings figure is 3.9 percent lower than the final July 2017 level of $2.27 billion, and is 27.7 percent higher than the August 2016 billings level of $1.71 billion.

“Equipment billings in August declined relative to July, signaling a pause in this year’s extraordinary growth,” said Ajit Manocha, president and CEO of SEMI. “Nonetheless monthly billings remain well above last year’s monthly levels.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.

	Billings (3-mo. avg)	Year-Over-Year
March 2017	$2,079.7	73.7%
April 2017	$2,136.4	46.3%
May 2017	$2,270.5	41.8%
June 2017	$2,300.3	34.1%
July 2017 (final)	$2,269.7	32.9%
August 2017 (prelim)	$2,181.8	27.7%

Source: SEMI (www.semi.org), September 2017

Leading-edge paves the way for pure-play foundry growth

September 20, 2017

IC Insights has just released its September Update to The McClean Report. This 32-page Update includes a detailed look at the pure-play foundry market and an analysis of the historical DRAM price-per-bit trends. Shown below is an excerpt from the Update that examines the IC technology trends in the pure-play foundry market.

In 2017, the 7% increase in the total pure-play foundry market is forecast to be almost entirely due to an 18% jump in <40nm feature size device sales (Figure 1).

Figure 1

Although expected to represent 60% of total pure-play foundry sales in 2017, the ≥40nm pure-play IC foundry market is forecast to be up only $0.2 billion this year. In contrast, the 2017 leading-edge <40nm pure-play foundry market is expected to surge by a hefty $3.3 billion. Moreover, not only is almost all of the pure-play foundry growth forecast to come from leading-edge production in 2017, most of the profits that are expected to be realized in the foundry market also forecast to come from the finer feature sizes as well.

TSMC is by far the technology leader among the major pure-play foundries. In 2017, 58% of TSMC’s revenue is expected to come from <40nm processing, more than double percentage at GlobalFoundries and more than triple the share at UMC. In total, TSMC is forecast to hold an 86% share of the total <40nm pure-play foundry market this year.

Illustrating how dominant TSMC is in the leading-edge pure-play foundry market, the company is expected to have almost 7x the dollar volume sales at <40nm as compared to GlobalFoundries, UMC, and SMIC combined this year ($18.5 billion for TSMC and $2.7 billion for combined total of GlobalFoundries, UMC, and SMIC). In fact, 10% of TSMC’s total sales this year are forecast to be for its 10nm process technology.

In contrast to TSMC, SMIC only entered initial production of its 28nm technology in 4Q15, more than three years after TSMC first put its 28nm process into production. In fact, only 7% of SMIC’s 2017 sales are expected to be from devices having 28nm feature sizes (the company does not offer a finer feature size at this time), which is the primary reason its revenue per wafer is so much less compared to TSMC.

Scientists demonstrated 1.3 Î¼m submilliamp threshold quantum dot micro-lasers on Si

September 18, 2017

Decades ago, the Moore’s law predicted that the number of transistors in a dense integrated circuit doubles approximately every two years. This prediction was proved to be right in the past few decades, and the quest for ever smaller and more efficient semiconductor devices have been a driving force in breakthroughs in the technology.

With an enduring and increasing need for miniaturization and large-scale integration of photonic components on the silicon platform for data communication and emerging applications in mind, a group of researchers from the Hong Kong University of Science and Technology and University of California, Santa Barbara, successfully demonstrated record-small electrically pumped micro-lasers epitaxially grown on industry standard (001) silicon substrates in a recent study. A submilliamp threshold of 0.6 mA, emitting at the near-infrared (1.3?m) was achieved for a micro-laser with a radius of 5 μm. The thresholds and footprints are orders of magnitude smaller than those previously reported lasers epitaxially grown on Si.

Their findings were published in the prestigious journal Optica on August 4, 2017 (doi: 10.1364/OPTICA.4.000940).

“We demonstrated the smallest current injection QD lasers directly grown on industry-standard (001) silicon with low power consumption and high temperature stability,” said Kei May Lau, Fang Professor of Engineering and Chair Professor of the Department of Electronic & Computer Engineering at HKUST.

“The realization of high-performance micron-sized lasers directly grown on Si represents a major step toward utilization of direct III-V/Si epitaxy as an alternate option to wafer-bonding techniques as on-chip silicon light sources with dense integration and low power consumption.”

The two groups have been collaborating and has previously developed continuous-wave (CW) optically-pumped micro-lasers operating at room temperature that were epitaxially grown on silicon with no germanium buffer layer or substrate miscut. This time, they demonstrated record-small electrically pumped QD lasers epitaxially grown on silicon. “Electrical injection of micro-lasers is a much more challenging and daunting task: first, electrode metallization is limited by the micro size cavity, which may increase the device resistance and thermal impedance; second, the whispering gallery mode (WGM) is sensitive to any process imperfection, which may increase the optical loss,” said Yating Wan, a HKUST PhD graduate and now postdoctoral fellow at the Optoelectronics Research Group of UCSB.

“As a promising integration platform, silicon photonics need on-chip laser sources that dramatically improve capability, while trimming size and power dissipation in a cost-effective way for volume manufacturability. The realization of high-performance micron-sized lasers directly grown on Si represents a major step toward utilization of direct III-V/Si epitaxy as an alternate option to wafer-bonding techniques,” said John Bowers, Deputy Chief Executive Officer of AIM Photonics.

IMAPS 2017 to showcase advances in microelectronics technology

September 15, 2017

The International Microelectronics And Packaging Society (IMAPS) will celebrate the 50^th anniversary of its flagship technical conference – the IMAPS Symposium – from October 9 – 12, 2017, as microelectronics engineers and scientists gather at the Raleigh Convention Center near Research Triangle Park, North Carolina, USA to take part in the electronics industry’s largest technical conference dedicated to advanced microelectronics packaging technology. Researchers and exhibitors will showcase their work during a comprehensive conference program of technical papers, panels, special sessions, short courses/tutorials, and an exhibition that will spotlight premier work in the fields of microelectronics, semiconductor packaging and circuit design.

The 50^th International Symposium on Microelectronics is an international technology forum for the presentation of applied research on microelectronics, consisting of more than 180 papers presented by researchers from corporations, universities and government labs worldwide, with five technical tracks: Chip Packaging Interactions; High Performance, Reliability, & Security; Advanced Packaging & Enabling Technologies; Advanced Packaging & System Integration; and Advanced Materials & Processes.

Keynote Presentations Lead Off the IMAPS Technical Program on Tuesday, October 10
Four keynote addresses from leading industry experts include:

“Packaging Challenges for the Next Generation of Mobile Devices,” by Ahmer Syed, Senior director of package engineering, Qualcomm Technologies

“Packaging without the Package – A More Holistic Moore’s Law,” by Subramanian (Subu) S. Iyer, distinguished chancellor’s professor in the Charles P. Reames Endowed Chair of the Electrical Engineering Department at the University of California at Los Angeles (UCLA) and Director of the Center for Heterogeneous Integration and Performance Scaling (CHIPS)

“Electronics Outside the Box: Building a Manufacturing Ecosystem for Flexible Hybrid Electronics,” by Benjamin Leever, senior materials engineer, Air Force Research Laboratory (AFRL) Soft Matter Materials Branch

“Transforming Electronic Interconnect,” by Tim Olson, founder & CTO, Deca Technologies

International Panel Session & Wine Reception on Wednesday, October 11
A panel session on “Global Perspectives on Packaging Requirements & Trends Towards 2025” will be moderated by Jan Vardaman, TechSearch International and Gabriel Pares, CEA-Leti. Panelist will include representatives from Asia (Yasumitsu Orii, NAGASE Group and Ton Schless, SIBCO), Europe (Steffen Kroehnert, Nanium and Eric Bridot, SAFRAN), and North America (David Jandzinski, Qorvo). The 90-minute panel session includes a wine reception.

Diversity Roundtable & Networking Discussions on Monday, October 9
Following the opening reception, IMAPS leaders will conduct a series of roundtable discussions designed to inspire conversations about overcoming diversity barriers, the strengths inherent in a diverse workforce, identifying and collaborating with a mentor, and more.

Posters & Pizza Session on Thursday, October 12
One of the fastest-growing segments of the IMAPS conference is the popular “Posters & Pizza” session held outside the exhibit hall, giving attendees the opportunity to interact one-on-one with presenters in a more informal setting.

Professional Development Courses (Short Courses & Tutorials) on Monday, October 9
Preceding the IMAPS Symposium technical program is a full day of professional development opportunities, presented as a series of 2-hour sessions in four tracks: Intro to Microelectronics Packaging; Next Generation Packaging Challenges; Baseline & Emerging Technologies; and Reliability. These short courses represent a unique opportunity, only available through IMAPS, for participants to personally interact with the instructors, and with each other in small groups from 10 – 30 people, led by industry experts in the field with ample time for questions and networking.

Student Opportunities at IMAPS
As part of its ongoing mission IMAPS invites students to participate in an informal networking event on Tuesday, October 10 with IMAPS industry leaders over lunch in the exhibit hall, giving them an chance to learn about career opportunities, navigating the hiring process, and other topics. In addition, the IMAPS Microelectronics Foundation sponsors a student paper competitionin conjunction with the Symposium that awards more than $3,500 in scholarships for outstanding student papers.

Social Events & an Introduction to the RTP/Raleigh Area’s Technology Community
In addition to the technical program, a variety of social events are planned around the IMAPS Symposia, including the Annual David C. Virissimo Memorial Fall Golf Classic, a charity golf outing scheduled for Monday, October 9 at NCSU’s Lonnie Poole Golf Course. Proceeds from the event benefit the IMAPS Microelectronics Foundation.

Monday evening’s welcome reception will feature NC-themed entertainment from a local bluegrass band, and participants will also be able to view historical photos and other memorabilia spanning 50 years of IMAPS history.

There is also a scheduled tour of the nearby Micross Advanced Interconnect Technology (AIT) facility, one of the premier wafer bumping and wafer level packaging facilities in the U.S., with more than 20 years experience providing leading edge interconnect and 3D integration technologies (TSV, Si interposers, 3D IC) to worldwide customers.

New to the Symposium this year is a unique opportunity for IMAPS attendees to experience the vibrant technology community in the greater RTP/Raleigh area. IMAPS has invited local non-profit organizations that comprise the area’s rapidly-growing technology ecosystem to participate in a special area adjacent to the exhibit hall during the day of October 10, providing an opportunity for IMAPS Symposium attendees to network and interact.

To register for the IMAPS 50^th International Symposium on Microelectronics, please visit the online registration site for more information, or contact Brianne Lamm, IMAPS Marketing & Events Manager, at [email protected] or 980-299-9873.

Cadence appoints John Wall as next Chief Financial Officer

September 15, 2017

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that John Wall, corporate vice president of finance and corporate controller of Cadence, has been appointed senior vice president and chief financial officer of Cadence, effective October 1, 2017. Geoff Ribar, current CFO of Cadence, will remain with the company as a senior advisor until his previously announced retirement at the end of March 2018.

Mr. Wall, a 20-year Cadence executive, has been corporate controller for the past year-and-a-half, during which he has worked closely with Mr. Ribar to set and execute the company’s financial goals. He previously served as vice president of finance, where he was responsible for worldwide revenue accounting and sales finance, and was instrumental in development of the ratable revenue model and sales models that Cadence uses. At the beginning of his tenure with Cadence, Mr. Wall established the Cadence office in Dublin, Ireland, was European controller and implemented the company’s international tax structure.

“The Board of Directors and I are excited to appoint John Wall as the next CFO of Cadence,” said Lip-Bu Tan, president and chief executive officer of Cadence. “We are confident that John’s deep financial experience and knowledge about our business will serve us well as we build upon the important progress we have made with our System Design Enablement strategy, further expand Cadence’s position with customers and improve our financial position.”

Mr. Tan continued, “On behalf of the Board and the entire Cadence team, I want to express our deepest gratitude to Geoff Ribar for his significant contributions to Cadence’s excellent financial management over the last seven years as CFO. Geoff played a key role in building the financial foundation through which we steadily increased our operating margin and improved our performance. We look forward to continuing to benefit from his exceptional skill and leadership during the transition and wish him all the best for the future.”

Cadence has also appointed Michelle Quejado as corporate controller, reporting to Mr. Wall. Ms. Quejado was most recently interim CFO at Zynga Inc., where she also served as corporate controller and chief accounting officer. Prior to Zynga, she served in multiple financial executive positions at Lam Research Corporation, including assistant corporate controller.

Semiconductor industry records best second quarter in three years

September 14, 2017

Despite a slightly down first quarter, the semiconductor industry achieved near record growth in the second quarter of 2017, posting a 6.1 percent growth from the previous quarter, according to IHS Markit (Nasdaq: INFO). Global revenue came in at $101.4 billion, up from $95.6 billion in the first quarter of 2017. This is the highest growth the industry has seen in the second quarter since 2014.

The memory chip market set records in the second quarter, growing 10.7 percent to a new high of $30.2 billion with DRAM and NOR flash memory leading the charge, growing 14 percent and 12.3 percent quarter-on-quarter, respectively.

“The DRAM market had another quarter of record revenues on the strength of higher prices and growth in shipments,” said Mike Howard, director for DRAM memory and storage at IHS Markit. “Anxiety about product availability in the previous third and fourth quarters weighed on the industry. This led many DRAM buyers to build inventory — putting additional pressure on the already tight market. This year is shaping up to smash all DRAM revenue records and will easily pass the $60 billion mark.”

“For NOR, the supply-demand balance has tightened raising average selling prices and revenue,” said Clifford Leimbach, senior analyst for memory and storage at IHS Markit. “This mature memory technology has been in a steady decline for many years, but some market suppliers are reducing supply or leaving the market, which has tightened supply recently, resulting in the increase of revenue.”

In terms of application, consumer electronics and data processing saw the most growth, increasing in revenue by 7.9 percent and 6.8 percent, respectively, quarter-on-quarter. A lot of this growth can be attributed to the continual growth in memory pricing, as supply still remains tight.

Industrial semiconductors showed the third highest growth rate at 6.4 percent during the same period. This growth can be attributable to multiple segments, such as commercial and military avionics, digital signage, network video surveillance, HVAC, smart meters, traction, PV inverters, LED lighting and medical electronics including cardiac equipment, hearing aids and imaging systems.

Another trend in the industrial market is increasing factory automation, which alone is driving growth for discrete power transistors, thyristors, rectifiers and power diodes. The market for these devices is expected to reach $8 billion in 2021, up from $5.7 billion in 2015.

Intel remains the number one semiconductor supplier in the world, followed by Samsung Electronics by a slight margin. IHS Markit does not include foundry operations and other non-semiconductor revenue in the semiconductor market rankings.

Among the top 20 semiconductor suppliers, Advanced Micro Devices (AMD) and nVidia achieved the highest revenue growth quarter over quarter by 24.7 percent and 14.6 percent, respectively. There was no market share movement in the top 10 semiconductor suppliers. However, seven of the 10 companies in the 11 to 20 market share slots did change market share.