Category Archives: Wafer Level Packaging

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced new capabilities that complete its holistic, integrated design flow for TSMC’s advanced wafer-level Integrated Fan-Out (InFO) packaging technology. Additionally, Cadence has unveiled enhancements for TSMC’s chip-on-wafer-on-substrate (CoWoS) advanced packaging technology. The complete InFO flow and enhanced CoWoS design methodologies enable design teams to efficiently complete the development process, from planning to analysis across multiple dies.

Completed InFO Design Flow

The Cadence® tools that have been enhanced to complete the TSMC InFO flow include the Quantus™ QRC Extraction Solution, Physical Verification System (PVS), and the Voltus™ Sigrity™ Package Analysis solution. Additional tools in the flow include OrbitIO™ Interconnect Designer, System-in-Package (SiP) Layout, Sigrity XtractIM™ technology, Tempus™Timing Signoff Solution, Sigrity PowerDC™ technology and Sigrity PowerSI® 3D-EM Extraction Option. With the completion of the flow, system-on-chip (SoC) designers can now:

  • Create virtual interface blocks and automate parasitic extraction, enabling package-level cross-die timing analysis: Cadence provides the first available platform that offers cross-die coupling extraction via the Quantus QRC Extraction Solution and PVS, enabling InFO designers to efficiently complete timing analysis with the Tempus Timing Signoff Solution at the package level.
  • Perform power DC and root mean square (RMS) electromigration (EM) and signal EM analysis: The Voltus Sigrity Package Analysis solution provides an integrated platform for power analysis across multiple dies and InFO designs.

CoWoS Reference Flow Enhancements

Cadence has also developed enhancements to the TSMC CoWoS reference flow. The new capabilities within the CoWoS refence flow enable designers to perform:

  • Integrated electromagnetic interference (EMI) analysis that enables analysis of the CoWoS system: Cadence is now offering an updated Sigrity EMI flow with automatic design merging, enabling integrated EMI analysis, as well as broadband-frequency-dependent S-parameter simulation, allowing for E/H-field analysis of the CoWoS system.
  • Static/dynamic IR analysis from a single environment: Voltus IC Power Integrity Solution now allows designers to do static/dynamic IR analysis across die and silicon interposers concurrently, while also analyzing power EM (dynamic/static) and signal EM (peak/RMS/average) for both dies and interposers within a single tool environment.
  • Correct cross-die interface alignment among dies and interposers: The PVS design rule checking (DRC) and layout versus schematic (LVS) capabilities provide cross-die DRC and power/signal connectivity checks, ensuring the cross-die interface has the correct alignment among the dies and interposers.
  • Thermal analysis across the CoWoS package, allowing accurate thermal runway predictions and reduced EM pessimism: The Voltus IC Power Integrity Solution and Sigrity PowerDC technology enable designers to do layer-based thermal analysis across the CoWoS package, which includes automated power map generation for all die within the solution and layer-based temperature map generation.
  • Parasitic extraction for silicon interposers, enabling timing and electrical analysis: The Quantus QRC Extraction Solution offers performance RC extraction, generating Standard Parasitic Exchange Format (SPEF) data for cross-die timing analysis. Additionally, Cadence Sigrity XcitePI™ technology provides RCLK extraction for frequency domain, signal integrity and power integrity simulation.

“We see a strong demand from both mobile and high-performance computing customers wanting to quickly deploy systems based on TSMC’s advanced packaging technologies,” said Tom Beckley, senior vice president and general manager of the Custom IC & PCB Group at Cadence. “Through our close working relationship with TSMC, we have completed TSMC InFO design flow and enhanced TSMC CoWoS reference flow, enabling our mutual customers to further shorten design and verification cycle times so they can get to market faster.”

“The Cadence solution for InFO technology enables our customers to deliver designs with increased bandwidth within small form factors,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “With these enhancements, the integrated full-flow addresses the market need for faster design and verification cycles. Additionally, the new capabilities added to the Cadence solution for CoWoS supports our customers who want to utilize this holistic reference flow for advanced packaging projects.”

The latest update to the World Fab Forecast report, published on September 5, 2017 by SEMI, again reveals record spending for fab equipment. Out of the 296 Front End facilities and lines tracked by SEMI, the report shows 30 facilities and lines with over $500 million in fab equipment spending.  2017 fab equipment spending (new and refurbished) is expected to increase by 37 percent, reaching a new annual spending record of about US$55 billion. The SEMI World Fab Forecast also forecasts that in 2018, fab equipment spending will increase even more, another 5 percent, for another record high of about $58 billion. The last record spending was in 2011 with about $40 billion. The spending in 2017 is now expected to top that by about $15 billion.

fab equipment spending

Figure 1: Fab equipment spending (new and refurbished) for Front End facilities

Examining 2017 spending by region, SEMI reports that the largest equipment spending region is Korea, which increases to about $19.5 billion in spending for 2017 from the $8.5 billion reported in 2016. This represents 130 percent growth year-over-year. In 2018, the World Fab Forecast report predicts that Korea will remain the largest spending region, while China will move up to second place with $12.5 billion (66 percent growth YoY) in equipment spending. Double-digit growth is also projected for Americas, Japan, and Europe/Mideast, while other regions growth is projected to remain below 10 percent.

The World Fab Forecast report estimates that Samsung is expected to more than double its fab equipment spending in 2017, to $16-$17 billion for Front End equipment, with another $15 billion in spending for 2018. Other memory companies are also forecast to make major spending increases, accounting for a total of $30 billion in memory-related spending for the year. Other market segments, such as Foundry ($17.8 billion), MPU ($3 billion), Logic ($1.8 billion), and Discrete with Power and LED ($1.8 billion), will also invest huge amounts on equipment. These same product segments also dominate spending into 2018.

In both 2017 and 2018, Samsung will drive the largest level in fab spending the industry has ever seen. While a single company can dominate spending trends, SEMI’s World Fab Forecast report also shows that a single region, China, can surge ahead and significantly impact spending. Worldwide, the World Fab Forecast tracks 62 active construction projects in 2017 and 42 projects for 2018, with many of these in China.

For insight into semiconductor manufacturing in 2017 and 2018 with more details about capex for construction projects, fab equipping, technology levels, and products, visit the SEMI Fab Database webpage (www.semi.org/en/MarketInfo/FabDatabase) and order the SEMI World Fab Forecast Report. The report, in Excel format, tracks spending and capacities for over 1,200 facilities including over 80 future facilities, across industry segments from Analog, Power, Logic, MPU, Memory, and Foundry to MEMS and LEDs facilities.

BY PETE SINGER, Editor-in-Chief

At a SEMICON West press conference, SEMI released its Mid-year Forecast. Worldwide sales of new semiconductor manufacturing equipment are projected to increase 19.8 percent to total $49.4 billion in 2017, marking the first time that the semiconductor equipment market has exceeded the market high of $47.7 billion set in 2000. In 2018, 7.7 percent growth is expected, resulting in another record-breaking year—totaling $53.2 billion for the global semiconductor equipment market.

“It’s really an exciting time for the industry in the terms of technology, the growth in information and data and that’s all going to require semiconductors to enable that growth,” said Dan Tracy, senior director, IR&S at SEMI.

The average of various analysts forecast the semiconductor industry in general 12% growth for the year. “It’s a very good growth year for the industry,” Tracy said. “In January, the consensus was about 5% growth for the year and with the improvement in the market and the firmer pricing for memory we see an increase in the outlook for the market.”

The SEMI Mid-year Forecast predicts wafer processing equipment is anticipated to increase 21.7 percent in 2017 to total $39.8 billion. The other front-end segment, which consists of fab facilities equipment, wafer manufacturing, and mask/reticle equipment, will increase 25.6 percent to total $2.3 billion. The assembly and packaging equipment segment is projected to grow by 12.8 percent to $3.4 billion in 2017 while semiconductor test equipment is forecast to increase by 6.4 percent, to a total of $3.9 billion this year.

“Based on the May outlook, we are looking at a record year in terms of tracking equipment spending. This is for new equipment, used equipment, and spending related to the facility that installed the equipment. It will be about a $49 billion market this year. Next year, it’s going to grow to $54 billion, so we have two years in a row of back to back record spending,” Tracy said.

In 2017, South Korea will be the largest equipment market for the first time. After maintaining the top spot for five years, Taiwan will place second, while China will come in third. All regions tracked will experience growth, with the exception of Rest of World (primarily Southeast Asia). South Korea will lead in growth with 68.7 percent, followed by Europe at 58.6 percent, and North America at 16.3 percent.

SEMI forecasts that in 2018, equipment sales in China will climb the most, 61.4 percent, to a total of $11.0 billion, following 5.9 percent growth in 2017. In 2018, South Korea, Taiwan, and China are forecast to remain the top three markets, with South Korea maintaining the top spot to total $13.4 billion. China is forecasted to become the second largest market at $11.0 billion, while equipment sales to Taiwan are expected to reach $10.9 billion.

The ConFab – an exclusive conference and networking event for semiconductor manufacturing and design executives from leading device makers, OEMs, OSATs, fabs, suppliers and fabless/design companies – announces the 2018 event will be held at THE COSMOPOLITAN of LAS VEGAS on May 20-23.

Pete Singer, Conference Chair of The ConFab and Editor-in-Chief of Solid State Technology had this to say, “The ConFab is a unique combination of business, technology and social interactions that make this industry gathering of influencers and leaders so valuable. In 2018, we will take a close look at the new applications driving the semiconductor industry, the technology that will be required at the device and process level to meet new demands, and – perhaps most importantly – the kind of strategic collaboration that will be required.” He also stated, “the key to continued business success for both guests and presenters will be the crucial insights that will be gained at the conference about critical market trends; and how to take advantage of emerging opportunities. Our goal is to “connect the dots” and how what’s going on in the end semiconductor application space (IoT, AI, 5G, VR, automotive, etc.) will ultimately impact semiconductor manufacturing and design.”

Keynotes, panel discussions and technical sessions on new technology needed in manufacturing will be a focal point of The ConFab 2018. Topics include: EUV, now entering volume production and ushering in a new era of patterning for the 7 and 5nm generations. And the many new materials being considered, transistors that are evolving from FinFETs to gate-all-around nanowires, on chip communication with silicon photonics emerging, and advanced packaging/heterogeneous integration as ever more critical. How semiconductors are playing an increasingly important role in the healthcare industry, will also be in the robust 2018 agenda.

The ConFab is a high-level, 3 1/2 day conference for decision-makers and influencers to connect, innovate and collaborate in multiple sessions, one-on-one private business meetings, and other daily networking activities. For more information, visit www.theconfab.com.

IC Insights has revised its outlook for semiconductor industry capital spending and presented its new findings in the August Update to The McClean Report 2017.  IC Insights’ latest forecast is for semiconductor industry capital spending to climb 20% this year.

Figure 1 shows the steep upward trend of quarterly capital spending in the semiconductor industry since 1Q16. Although there was a slight pause in the upward trajectory in 1Q17, 2Q17 set a new record for quarterly spending outlays.   Moreover, 1H17 semiconductor industry spending was 48% greater than in 1H16.  IC Insights believes that whether industry-wide capital spending in the second half of 2017 can match the first half of the year is greatly dependent upon the level of Samsung’s 2H17 spending outlays.

Not only has Samsung Semiconductor been on a tear with regard to its semiconductor sales, surging into the number one ranking in 2Q17, but the company has also been on a tremendous capital spending spree for its semiconductor division this year.  As depicted in Figure 2, Samsung spent a whopping $11.0 billion in capital outlays for its semiconductor group in 1H17, more than 3x greater than the company spent in 1H16 and only $300 million less than the company spent in all of 2016!   In fact, Samsung’s capital expenditures in 1H17 represented 25% of the total semiconductor industry capital spending and 28% of the outlays in 2Q17.

While the company has publicly reported that it spent $11.0 billion in capital outlays for its semiconductor division in 1H17 (a $22.0 billion annual run-rate), Samsung has been very secretive about revealing its full-year 2017 budget for its semiconductor group (it might be afraid of shocking the industry with such a big number!).  In 2012, the year of Samsung’s previous first half spending surge before 1H17, the company cut its second half capital outlays by more than 50%, from $8.5 billion in 1H12 to $3.7 billion in 2H12.  Will the company follow the same pattern in 2017?  At this point, it is impossible to tell.  IC Insights believes that Samsung’s full-year 2017 capital expenditures could range from $15.0 billion to $22.0 billion!

Figure 1

Figure 1

If Samsung spends $22.0 billion in capital outlays this year, total semiconductor industry capital spending could reach $85.4 billion, which would represent a 27% increase over the $67.3 billion the industry spent in 2016.

It is interesting to note that two of the major spenders, TSMC and Intel, are expected to move in opposite directions with regard to their 2H17 capital spending plans. TSMC spent about $6.8 billion in capital outlays in 1H17. If it sticks to its $10.0 billion budget this year, which it reiterated in its second quarter results, it would only spend about $3.2 billion in 2H17, less than half its outlays in 1H17. In contrast, Intel spent only about $4.7 billion in 1H17, leaving the company to spend about $7.3 billion in 2H17 in order to reach its stated full-year 2017 spending budget of $12.0 billion.

Figure 2

Figure 2

TowerJazz, the global specialty foundry, and Tacoma Technology Ltd and Tacoma (Nanjing) Semiconductor Technology Co., Ltd (collectively known as “Tacoma”) announced today that Tower has received a first payment of $18 million net, rendering phase one of the framework agreement with Tacoma binding. This agreement maps the establishment of a new 8-inch semiconductor fabrication facility in Nanjing, China. According to the terms of the framework agreement, TowerJazz will provide technological expertise together with operational and integration consultation, for which the Company shall receive additional payments based on milestones during the next few years, subject to a definitive agreement specifying all terms and conditions.

In addition, from the start of production at the facility, TowerJazz will be entitled to capacity allocation of up to 50% of the targeted 40,000 wafer per month fab capacity, which it may decide to use at its discretion. This capacity will provide TowerJazz with additional manufacturing capability and flexibility to address its growing global demand.

Tacoma will be responsible to source funds for all activities, milestones and deliverables of the entire project, including the construction, commissioning and ramp of this facility, with the project being fully supported by Nanjing Economic and Technology Development Zone through its Administration Committee, Credito Capital as well as through potential funding from other third party investors and entities.

“This agreement with Tacoma is in line with our business strategy to focus on growing markets such as China. The fabless business in China has grown rapidly in the past years. The new 8-inch fabrication facility in Nanjing will provide us with a strategic footprint in China and the opportunity to extend our offerings in advanced specialty process technologies by enabling customers in China to optimize their product performance and time to market,” said Dr. Itzhak Edrei, TowerJazz President.

Russell Ellwanger, TowerJazz Chief Executive Officer, commented, “We are exploring multiple opportunities in China, and determined this agreement with Tacoma to be a good fit for TowerJazz, providing a roadmap for a meaningful long-term strategic partnership. China’s focus to develop its domestic semiconductor industry with full infrastructure presents additional opportunities for TowerJazz, as a global analog leader, to expand our served markets and geographic presence. This partnership will enable us to further fulfill our customers’ needs through additional available capacity as well as to be an active player in the growing Chinese market.”

Joseph Lee, Tacoma Chairman, stated: “Deeply engraved in the corporate culture of both Tacoma and TowerJazz is the core belief in working ‘SMART’ with ‘PASSION.’ Our people are committed to contributing to our business partners, the global semiconductor industry and society with the best endeavor and integrity. Tacoma will fully fund this project together with Credito Capital and other entities. This venture will become a dominant player in Asia and will raise the standard in the semiconductor industry to another level.”

A groundbreaking and signing ceremony took place in Nanjing, China, attended by TowerJazz Chairman Mr. Amir Elstein, President Dr. Itzhak Edrei, Business Development Vice President Mr. Erez Imberman, as well as the then Israeli Ambassador to China the Honorable Mr. Matan Vilnai. Pictured, the signing between Tacoma Chairman, Mr. Joseph Lee and TowerJazz CEO Mr. Russell Ellwanger, with among others the above cited attendees.

Chipmakers want every part of the wafer to produce, or yield, good die. Advances in process technologies over the years have just about made this a reality, even as feature dimensions continue to shrink and devices grow ever more complex. Now, the last frontier is improving yields at the edge of the wafer – the outer 10 mm or so – where chemical, physical, and even thermal discontinuities are simply much harder to control. Complicating matters, current strategies used to manage these edge issues involve tradeoffs between yield and manufacturing costs that result in less than ideal fab economics. At Lam, our technologists have been working on solutions to this challenge, and today, we released the new Corvus™ edge control technology for our Kiyo® conductor etch products to address these very issues and enhance edge yield.

Edge Challenges

Taking a closer look at the wafer’s edge, where up to ~10% of the die may be located, there are several issues at play that can impact yield. In all plasma etch reactors, the abrupt end of the wafer surface creates inherent electrical discontinuities at the edge region, forming voltage gradients that bend the plasma sheath. This, in turn, changes the direction of the plasma’s components (ions and neutrals), which impacts etch results and causes unwanted variability. In the case of 3D NAND devices, for example, this change in the plasma conditions at the wafer’s edge can cause tilted etch profiles or prevent features from being completely etched. In addition to affecting tilt angle, these edge effects can result in non-uniform critical dimensions (CDs) or changes in local overlay metrics.

LAMResearch1

Another challenge is that process drift creates CD uniformity and selectivity problems over time. As a way to manage this, chipmakers often add more chamber wet cleans to restore the equipment to a standard condition. However, this approach significantly reduces productivity because the chamber is not available for processing wafers during this maintenance. In addition, as process margins get tighter, more frequent wet cleans are required, which increases operational costs.

Corvus Solution

Lam’s new Corvus technology provides a novel capability to smooth out extreme edge discontinuities and enhance edge performance. It offers the ability to tune the plasma sheath at the edge to produce a constant, user-defined etch rate and ion angle. For example, etch rate can be tuned to be faster or slower at the edge relative to the rate over the rest of the wafer. With 3D NAND applications, Corvus technology has demonstrated the ability to minimize plasma sheath drift, preventing detrimental feature tilting at the wafer’s edge. Tuning to within 1.5 mm of the edge, the new technology can correct for inherent process variation in the edge region as well as for incoming film variations to optimize die yield. Furthermore, with Corvus, every wafer sees the same edge conditions for optimal yield, eliminating previously seen systematic wafer-to-wafer yield variability.

Corvus technology not only improves across-wafer uniformity, it also greatly reduces wafer-to-wafer and chamber-to-chamber variability and eliminates the historical tradeoffs among yield, operational flexibility, and cost. Customers have reported die yield improvements of 0.5-2% per wafer, which can be a significant advantage – especially when you consider how many thousands of wafers chipmakers process every day. Additionally, Corvus has demonstrated the ability to provide higher and more consistent yield over a longer period. It also greatly enhances productivity and lowers overall fab operating costs for high-volume manufacturing by requiring fewer chamber wet cleans. The new technology is being used for advanced patterning, mask open, and other challenging conductor etch applications where reducing variation in CD, profile, or selectivity and improving productivity helps enable continued scaling.

The new capability provided by Corvus complements Lam’s Hydra® technology, which enables fine tuning of within-wafer uniformity and actively compensates for incoming variation. Together, these advanced process control technologies are reducing variability across the entire wafer surface, improving yield, and enabling the production of next-generation logic and memory devices.

Welch Foundation, the Army Research Office and the National Science Foundation supported the research.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $97.9 billion during the second quarter of 2017, an increase of 5.8 percent over the previous quarter and 23.7 percent more than the second quarter of 2016. Global sales for the month of June 2017 reached $32.6 billion, an uptick of 2.0 percent over last month’s total of $32.0 billion, and a surge of 23.7 percent compared to the June 2016 total of $26.4 billion. Cumulatively, year-to-date sales during the first half of 2017 were 20.8 percent higher than they were at the same point in 2016. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“The global semiconductor industry has enjoyed impressive sales growth midway through 2017, posting its highest-ever quarterly sales in Q2 and record monthly sales in June,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Sales into the Americas market were particularly robust in June, and all regional markets saw growth of at least 18 percent year-over-year. Conditions are favorable for continued market growth in the months ahead.”

Regionally, sales increased compared to June 2016 in the Americas (33.4 percent), China (25.5 percent), Asia Pacific/All Other (19.5 percent), Europe (18.3 percent), and Japan (18.0 percent). Sales also were up across all regions compared to last month: the Americas (5.1 percent), Europe (1.9 percent), China (1.5 percent), Japan (1.0 percent), and Asia Pacific/All Other (0.8 percent).

June 2017

Billions

Month-to-Month Sales                              

Market

Last Month

Current Month

% Change

Americas

6.27

6.59

5.1%

Europe

3.11

3.16

1.9%

Japan

2.95

2.98

1.0%

China

10.25

10.41

1.5%

Asia Pacific/All Other

9.43

9.50

0.8%

Total

32.00

32.64

2.0%

Year-to-Year Sales                         

Market

Last Year

Current Month

% Change

Americas

4.94

6.59

33.4%

Europe

2.68

3.16

18.3%

Japan

2.52

2.98

18.0%

China

8.29

10.41

25.5%

Asia Pacific/All Other

7.95

9.50

19.5%

Total

26.38

32.64

23.7%

Three-Month-Moving Average Sales

Market

Jan/Feb/Mar

Apr/May/Jun

% Change

Americas

5.96

6.59

10.5%

Europe

2.96

3.16

7.1%

Japan

2.84

2.98

4.8%

China

10.06

10.41

3.4%

Asia Pacific/All Other

9.02

9.50

5.4%

Total

30.84

32.64

5.8%

TECHCET CA, an advisory service firm providing electronic materials information, today announced that the silicon wafer supply for semiconductor device fabrication is forecasted to appreciably lag demand starting next year, and could remain in shortage through the year 2021 despite investments in China. Silicon wafer area demand is forecasted to steadily increase at a CAGR of ~3.1% over the 2016-2021 period to reach over 13,000 million square inches (MSI). Executives of silicon wafer suppliers have stated that average selling prices have remained too low to allow for investment in 300mm expansions, as detailed in a quarterly update to the TECHCET Critical Materials Report, “Silicon Wafers Market & Supply-Chain.”

The silicon wafer supply-chain is dominated by two suppliers–Shin-Etsu Handotai and SUMCO–combining to capture almost two-thirds of the global wafer market in 2016, and the top five representing over 92% of total revenues. The silicon wafer market is maturing as evidenced by recent mergers and acquisitions, the two most notable being the acquisition of SunEdison Semi by GlobalWafers (Taiwan) and the assumption of majority ownership of LG Siltron by SK Holdings (Korea).

“Over the last five years, the average selling price per square inch of semiconductor-grade silicon wafers has declined by about a third and more than a half from the 2007 level,” explained Michel Walden, lead author of the report and senior technology analyst with TECHCET. “However, current tightness in the supply-chain has led to greater stability and even price increases in some cases, all of which is likely needed for the long-term health of the wafer suppliers.”

Over the past few years, silicon suppliers decommissioned roughly 25% of the peak capacity for 200mm wafers. Of the remaining 200mm capacity, roughly 65% of the total demand is for epitaxial (epi) wafers, and a series of epi service companies have embraced this opportunity and provide a variety of layer configurations for their customers.

BY ELISABETH BRANDL, THOMAS UHRMANN and MARTIN EIBELHUBER, EV Group, St. Florian, Austria

Fan-out packaging is an established technology for many mobile applications. Whereas early semiconductor packages have been single-chip packages, the continuing trend of expanding the wiring surface to support increased functionality has led to more complex packages, stacked packages, systems inpackageaswellashigh-performancepackages. With this development, fan-out technology is bridging a gap between cost-competitive packaging and high performance. For all aforementioned packages, temporary bonding will be needed, either to enable the thinning of wafers to address the need for smaller form factors, to achieve cost savings on mold materials or to serve as a processing platform for redistribution-layer (RDL) first processes.

Temporary bonding requires both a bonding and debonding process. Determining the right debonding technology can be difficult and confusing as every application from fan-out wafer-level packaging (FoWLP) to power devices has its own requirements in terms of process temperature, mechanical stress and thermal budget, to name just a few considerations. In this article, we will focus on laser debonding, where high- temperature compatible materials are available. We will point out for which applications the laser debond characteristics fit well.

To limit the thermal input associated with debonding, UV lasers are utilized for debonding where several materials from different temporary bonding material suppliers are available. To confine the maintenance effort to a minimum, a diode-pumped solid-state (DPSS) laser is the right choice in combination with beam-shaping optics for high process control and minimum heat input.

Screen Shot 2017-07-27 at 9.09.58 AM

Challenges of temporary bonding for FoWLP

FoWLP has gained significant industry interest in part due to carrier, the requirements of the temporary bonding material in terms of chemical and thermal compat- ibility are high. Certain kinds of polyimides comply with this harsh environment and are also suitable for laser debonding.

By just comparing these two processes, the require- ments differ significantly even though both are FoWLP processes. By looking at the wide variety of semiconductor processes for various applications, it becomes clear that no single debonding process solution is compatible with all semiconductor processes, but rather several solutions are necessary. This is the reason why a variety of debonding processes (temporary bonding is characterized by the debonding technology) have been developed and are still in use today.

Comparison of the mainstream debonding technologies

The most common debonding methods are thermal slide-off debonding, mechanical debonding and UV laser debonding. These three methods are all in high- volume manufacturing and differ strongly in their process compatibility.

Thermal slide-off is a method that employs a thermo-plastic material as an adhesive interlayer between the device and carrier wafer. The debonding method uses the reversible thermal behavior of the thermoplastic material, meaning that at elevated temperatures the material experiences a drop in viscosity, which enables debonding to be accomplished by simply sliding the wafers off of each other. The character- istics of thermal slide-off debonding is bonding and debonding at elevated temperatures, which depending on the thermoplastic material being used can range between 130 and 350°C. Temperature stability depends in large part on mechanical stress, which can be observed due to the thermoplastic’s low viscosity at high temperatures [1].

Mechanical debonding is a method that is highly dependent on the surface properties of the wafers involved as well as the adhesion and cohesion of the temporary bonding material. For most material systems, a mechanical release layer is applied to achieve a controlled debonding mechanism. Key characteristics of mechanical debonding include processing at room temperature and a strong dependence on mechanical stress. Since mechanical debonding needs a low adhesion between the temporary bonding material and the wafer for a successful debond process, it can be tricky to use it for FoWLP applications. This is because the high wafer stress associated with FoWLP processing can lead to spontaneous debonding, even during the thinning process, which in turn can result in a drastic drop in yield [2].

Laser debonding is a technology that has been implemented with several different variations. The debond mechanism depends on the type of laser as well as the temporary bonding adhesive or the specific release layer used for the process. Infrared lasers work on the principle of the photo thermal process, where light is absorbed and transferred into heat, which leads to high temperatures within the bond interface. UV laser debonding typically uses the photo chemical process, where light is absorbed and the energy is used for breaking chemical bonds. Breaking the chemical bonds of a polymer results in the production of fragments of the original polymer. These fragments comprise gases, which increase the pressure within the interface to support the debonding process. For FoWLP applications, this method is a good fit due to the high adhesion of the temporary bonding adhesive to the wafers before the debonding process.

Optimized solution for FoWLP applications

UV lasers are advantageous for FoWLP processing due to their limited thermal input through the debonding process. The carrier wafer must be transparent to the UV laser’s wavelength to ensure efficient use of the laser energy and also ensure a higher lifetime of the carrier wafer. Two main types of UV lasers are available (solid-state laser and excimer laser), with each having several different wavelength options. Choosing a laser with a wavelength larger than 300nm is optimal for several reasons. First, commercially available laser debond materials effectively absorb and therefore debond at wavelengths higher than 300nm. Second, it allows a standard glass wafer to be used as the carrier since glass enables high transmission in this wavelength regime.

Solid-state lasers have the advantage of lower maintenance costs because they do not need halogen gas, which must be replaced on a regular basis. For solid-state lasers, the consumables are very low, and depending on the amount of power used by the laser there are examples of lasers used for laser debonding on a 24/7 basis that have required no laser consumables in the first five years of operation. Additionally, a smaller footprint can also be achieved due to a compact optical setup. Solid-state lasers typically have Gaussian beam profiles, pictured in FIGURE 3.

Screen Shot 2017-07-27 at 9.10.14 AM

UV laser debonding is a threshold process, meaning that debonding occurs above a certain value of radiant exposure. In Figure 3, the area with the blue criss-cross lines indicates the radiant exposure, which is used for the debonding process. The energy that is below or above that value (areas in red in the picture) cannot be used for debonding and is typically trans- ferred into heat, which can lead to carbonization and particle creation. Because of the lack of sufficient energy at the edge of the Gaussian laser beam profile, a certain overlap of the pulses is necessary, which is an additional variable that must be optimized in order to achieve successful debonding without carbonization. Additionally, the excess energy in the beam center can cause carbonization. A Gaussian beam profile is not suitable to limit thermal effects during debonding.

Gaussian beam profiles can be transferred into quasi top hat beam profiles by using a proprietary optical setup for beam shaping. By employing this optical setup, a highly reproducible beam for debonding (whereby the beam shape does not change over time) is achieved with constrained thermal input similar to what is seen in the “top hat” beam profile in FIGURE 4. This gives tighter process control, which in combination with the high pulse repetition rate of this laser type and the ability to scan across the surface of a fixed wafer leads to a well-controlled, high-throughput debonding process. The scanning process is pictured in FIGURE 5 where — in contrast to an excimer laser — the wafer is fixed on a static stage and the laser spot is controlled by a galvo scanner over the wafer. leads to a well-controlled, high-throughput debonding process.

Screen Shot 2017-07-27 at 9.10.24 AM

Screen Shot 2017-07-27 at 9.10.34 AM Screen Shot 2017-07-27 at 9.10.42 AMAs shown in FIGURE 6, a test wafer is used to determine the optimum radiant exposure for debonding. Even with a top hat beam profile, it is important to use a radiant exposure value close to the debonding threshold to minimize heat effects [3]. Small overlaps are necessary nonetheless because the adhesion between the temporary bonding material and the wafers is very high.

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Temporary bonding for future FoWLP

Ultrathin and stacked fan-out packages, also called Package on package (PoP), are already on several industry roadmaps due to their ability to enable higher device densities. However, the need for reconstituted wafers to become even thinner for PoP versus current FoWLP will give rise to more challenges for temporary bonding. For example, the bow of the temporary bonded wafer stack consisting of a molded wafer and a carrier wafer must be minimized to ensure uniform thinning. The maximum total thickness variation (TTV) will also become tighter depending on the final thickness. As for every 3D application, questions regarding interconnects, such as choosing via first or via last, also arises for PoP, where several processes are also available and where no standard process exists that is employed by all fan-out packaging houses.

Summary

UV laser debonding is a suitable method for both chip- first and chip-last/RDL-first FoWLP processes because it offers debonding at room temperature, and because chemically stable materials are available. The UV laser debonding solutions presented in this article combine the advantages of the solid-state laser with low mainte- nance, low consumables costs and high pulse frequencies combined with high spatial control due to the special beam-shaping optics.

Further Readings

1. Critical process parameters and failure analysis for temporary bonded wafer stacks. Karine Abadie, Elisabeth Brandl, Frank Fournel, Pierre Montméa, Wimplinger, Jürgen Burggraf, Thomas Uhrmann, Julian Bravin. Fountain Hills, Arizona: iMaps, 2016. iMaps Device Packaging Conference.

2. Temporary Wafer Carrier Solutions for thin FOWLP and eWLB-based PoP. Jose Campos, André Cardoso, Mariana Pires, Eoin O’Toole, Raquel Pinto, Steffen Kröhnert, Emilie Jolivet, Thomas Uhrmann, Elizabeth Brandl, Jürgen Burggraf, Harald Wiesbauer, Julian Bravin, Markus Wimplinger and Paul Lindner. San Jose, California : SMTA International, 2015. iWLPC (International Wafer Level Packaging Conference).

3. Key Criteria for Successful Integration of Laser Debonding. Elisabeth Brandl, Thomas Uhrmann, Jürgen Burggraf, Martin Eibelhuber, Harald Wiesbauer, Mariana Pires, Philipp Kolmhofer, Matthias Pichler, Julian Bravin, Markus Wimplinger and Paul Lindner. San Jose, California : SMTA Inter- national, 2016. iWLPC.