Category Archives: Wafer Level Packaging

North America-based manufacturers of semiconductor equipment posted $2.29 billion in billings worldwide in June 2017 (three-month average basis), according to the June Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI.

SEMI reports that the three-month average of worldwide billings of North American equipment manufacturers in June 2017 was $2.29 billion. The billings figure is 0.8 percent higher than the final May 2017 level of $2.27 billion, and is 33.4 percent higher than the June 2016 billings level of $1.72 billion.

“Through the first half of the year, 2017 equipment billings are 50 percent above the same period last year,” said Dan Tracy, senior director, Industry Research & Statistics, SEMI.  “While month-to-month growth is slowing, 2017 will be a remarkable growth year for the semiconductor capital equipment industry.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.
Billings
(3-mo. avg)
Year-Over-Year
January 2017
$1,859.4
52.3%
February 2017
$1,974.0
63.9%
March 2017
$2,079.7
73.7%
April 2017
$2,136.4
46.3%
May 2017 (final)
$2,270.5
41.8%
June 2017 (prelim)
$2,288.9
33.4%

Source: SEMI (www.semi.org), July 2017
SEMI publishes a monthly North American Billings report and issues the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) report in collaboration with the Semiconductor Equipment Association of Japan (SEAJ). The WWSEMS report currently reports billings by 24 equipment segments and by seven end market regions. SEMI also has a long history of tracking semiconductor industry fab investments in detail on a company-by-company and fab-by-fab basis in its World Fab Forecast and SEMI FabView databases. These powerful tools provide access to spending forecasts, capacity ramp, technology transitions, and other information for over 1,000 fabs worldwide. For an overview of available SEMI market data, please visit www.semi.org/en/MarketInfo.

 

Multitest’s new 0.3 mm pitch Atlas contactor successfully passed a demanding customer production floor evaluation. The customer’s evaluation measures confirmed that the Atlas did reduce the customer’s cost of test while improving test yield and increasing throughput. Based on the evaluation results, the customer ordered a significant number of Atlas 030 contactors to support their new product WLCSP production ramp.

The customer is a long time user of Multitest contactors and after reviewing the new Atlas design they were eager to evaluate it. It is the added strength of the Atlas cruciform tip that captured the customer’s attention.  Not only is the Atlas mechanically superior, the Atlas offers electrical performance that allows the customer to test to the true performance of the device. The evaluation ended with the customer placing an order for a significant quantity of Atlas 030 contactors.
The key to the WLCSP Atlas’s high performance, high reliability and superior electrical contacting is the combination of increased mechanical tip strength and short probe electrical performance.  Atlas WLCSP test contactors achieve mechanical reliability with a rigid “cruciform” tip applied to Multitest’s QuadTech flat probe technology.  The Atlas 030 offers a short electrical path, with lower capacitance and inductance that is ideal for functional and AC parametric testing of WLCSP devices that require high system bandwidth and throughput gains in large multisite test applications.

The cruciform tip provides increased tip rigidity with a much greater immunity to breakage than traditional WLCPS probes used in earlier-generation test sockets. The Atlas 030 has 0.310 mm of compliance for bump structures that requires a larger compliance window for reliable contacting in high parallel test applications.

Bert Brost, Senior Product Managers, explains: “We are very proud of the positive result of the evaluation. The evaluation by the customer confirmed what we already knew, the Atlas 030 contactor is a high performance solution for WLCSP testing.”

Advances in semiconductor and related devices are driving significant progress in our increasingly digital world, and the place to learn about cutting-edge research in the field is the annual IEEE International Electron Devices Meeting (IEDM), to be held December 2-6, 2017 at the Hilton San Francisco Union Square hotel. Highlights for 2017 include:

  • A talk on transformative electronics by Dr. Hiroshi Amano, who received the 2014 Nobel Prize in Physics along with Isamu Akasaki and Shuji Nakamura for the invention of efficient blue LEDs, which sparked a revolution in innovative, energy-saving lighting.
  • The above talk is part of an exceptional slate of plenary talks to be given by some of the industry’s leading figures. IEDM plenary presenters include the CEO of Advanced Micro Devices, Inc.; the research chief of TSMC, which is the industry’s largest foundry driving technology forward; a leading academic authority on energy-efficient computing, which is a key societal goal; as well as Dr. Amano’s fourth, additional plenary talk. It will be given on Wednesday, Dec. 6.
  • Focus Sessions will be held on the following topics: 3D Integration and Packaging; Modeling Challenges for Neuromorphic Computing; Nanosensors for Disease Diagnostics; and Silicon Photonics: Current status and perspectives.
  • A vendor exhibition will be held again, based on the success of last year’s first-ever such event at the IEDM.
  • The IEEE Magnetics Society will host a poster session on MRAM (magnetic RAM memories).

The IEDM paper submission deadline this year is August 2 and the deadline for late-news papers is September 11. Only a limited number of late-news papers will be accepted.

Each year at the IEDM, the world’s best technologists in micro/nano/bioelectronics converge to participate in a technical program consisting of more than 220 presentations along with special luncheon talks and a variety of panels, special sessions, tutorials, Short Courses, IEEE/EDS award presentations and other events that highlight leading work in more diverse areas of the field than any other conference.

“This year’s IEDM will feature talks, courses and panels by world experts on what is perhaps the broadest array of topics in recent memory,” said Dr. Barbara De Salvo, Scientific Director at Leti. “The unique technical program can lead one to view the IEDM as a crystal ball of sorts, because many of the developments reported at the conference invariably make their way into commercial products a few years down the road. As an example, this year’s IEDM conference marks 10 years since the industry transition from aluminum to copper interconnect began in earnest.”

Here are details of some of the events that will take place at this year’s IEDM:

Focus Sessions

  • 3D Integration and Packaging – Packaging technology is taking on an increasingly important role in semiconductor manufacturing, and this session will provide an industry perspective on forthcoming approaches ranging from “Simpler is better” to “Advanced packaging saves the day for continued scaling.” The session will address the latest in 3D, from alternative packaging to 3D stacking, and applications and technologies for Integrated Power Microelectronics.
  • Modeling Challenges for Neuromorphic Computing – This session will address the opportunities and challenges of efficient synaptic processes, from learning models to device-circuit implementations of neuromorphic architectures.  Half of the session will discuss learning models in stochastic processes, with the other half devoted to RRAM (resistive RAM) memory for deep neural networks and neuromorphic computing.
  • Nanosensors for Disease Diagnostics — From microfluidics to nanosensing, this session will review the latest advances for the detection of diseases such as cancer, sepsis and diabetes, using biomarkers ranging from (bio)molecules and individual cells to in-vitro tissue models.
  • Silicon Photonics: Current Status and Perspectives – This session addresses the state-of-the-art in silicon photonics technology, ranging from topics on high-volume manufacturing, optical transceivers and interconnects, to femto-joule per bit integrated nanophotonics for upcoming market applications in optical computing.

90-Minute Tutorials – Saturday, Dec. 2
A program of 90-minute tutorial sessions on emerging technologies will be presented by experts in the fields, bridging the gap between textbook-level knowledge and leading-edge current research. Advance registration is recommended.

  • The Evolution of Logic Transistors Toward Low Power and High Performance IoT Applications, Dr. Dae Won Ha, Samsung Electronics
  • Negative Capacitance Transistors, Prof. Sayeef Salahuddin, UC Berkeley
  • Fundamental, Thermal, and Energy Limits of PCM and ReRAM, Prof. Eric Pop, Stanford University
  • Hardware Opportunities in Cognitive Computing: Near- and Far-Term, Dr. Geoffrey Burr, Principal Research Staff Member, IBM Research-Almaden
  • 2.5D Interposers and High-Density Fanout Packaging as Enablers for Future Systems Integration, Dr. Sundaram Venkatesh, Associate Director, Georgia Tech 3D Systems Packaging Research Center
  • Silicon Photonics for Next-Generation Optical Interconnects, Dr. Joris Van Campenhout, Program Director Optical I/O, IMEC

Short Courses – Sunday, Dec. 3
Short Courses provide the opportunity to learn about important areas and developments, and provide the opportunity to network with experts from around the world. Advance registration is recommended.

  • Performance Boosters and Variation Management in Sub-5nm CMOS, organized by Sandy Liao, Intel
  • Merged Memory-Logic Technologies and Their Applications, organized by Kevin Zhang, TSMC

Plenary Presentations – Monday, Dec. 4

  • System Scaling Innovation for Intelligent Ubiquitous Computing, Jack Sun, VP of R&D, TSMC
  • Driving the Future of High-Performance Computing, Lisa Su, President & CEO, AMD
  • Energy-Efficient Computing and Sensing: From Silicon to the Cloud, Adrian Ionescu, Professor, EPFL

Plenary Presentation – Wednesday, Dec. 6

  • Development of a Sustainable Smart Society by Transformative Electronics, Hiroshi Amano, Professor, Nagoya University

Evening Panel Session – Tuesday evening, Dec. 5
The IEDM offers attendees an evening session where panels of experts give their views on important industry topics. Audience participation is encouraged to foster an open and vigorous exchange of ideas.

  • Who Will Lead the Industry in the Future? Moderator: Prof. Philip Wong, Stanford University

Entrepreneurs Lunch
The topic and speaker are yet to be determined, but this popular luncheon jointly sponsored by IEDM and the IEEE Electron Devices Society will be held once again.

Further information about IEDM
For registration and other information, visit www.ieee-iedm.org.

SUNY Polytechnic Institute (SUNY Poly) announced today that Interim Dean of Graduate Studies Dr. Fatemeh (Shadi) Shahedipour-Sandvik and her team of collaborators have been selected to receive $720,000 in federal funding from the U.S. Department of Energy’s Advanced Research Projects Agency-Energy (ARPA-E). The grant will be used to develop more efficient and powerful high-performance power switches at SUNY Poly for power electronics applications, such as for enabling a more efficient energy grid, for example. The research is in partnership with Dr. Woongje Sung of SUNY Poly, the Army Research Lab, Drexel University, and Gyrotron Technology, Inc.

“On behalf of SUNY Poly, I am excited to congratulate Professor Shahedipour-Sandvik as her wide-bandgap-focused research is recognized by the Department of Energy for its potential to improve power devices that are all around us to make our technological world more energy efficient and robust,” said SUNY Poly Interim President Dr. Bahgat Sammakia. “This award highlights SUNY Poly’s unique and advanced research capabilities, as well as its superb faculty who are developing the innovations of tomorrow right now in New York State.”

“This award is a strong indicator of how SUNY Poly’s resources and facilities are enabling the types of research that have the potential to improve power electronics devices which have become ubiquitous, from those utilized to make the power grid more efficient, to those that can improve electric car capabilities,” said SUNY Poly Vice President of Research Dr. Michael Liehr.

“I am proud that the U.S. Department of Energy’s ARPA-E has recognized our leading-edge power electronics-focused research, which holds the incredible potential to drive innovation for practical applications that could lead to worldwide energy savings. Advanced power electronic devices offer significant advances in power density, efficiency, and reduced total lifecycle cost,” said Prof. Shahedipour-Sandvik. “This grant allowing our SUNY Poly team and partners at the Army Research Lab, Drexel University and Gyrotron Technology, Inc. to explore advanced doping and annealing techniques for gallium nitride-based power devices is a testament to how SUNY Poly’s resources and leadership in areas like power electronics can help power the future in exciting and meaningful ways.” 

The SUNY Poly grant is part of a total of $6.9 million in funding that the U.S. Department of Energy ARPA-E is providing through its Power Nitride Doping Innovation Offers Devices Enabling SWITCHES (PNDIODES) program to seven institutions and organizations. With PNDIODES, ARPA-E is tackling a specific challenge in wide-bandgap semiconductor production. Wide-bandgap semiconductors are an important area of research because the materials, such as gallium nitride (GaN), allow for electronic devices to operate at higher temperatures and/or frequencies, for example, than current silicon-based computer chips, which is why technical advances in power electronics promise energy efficiency gains throughout the United States economy. Achieving high power conversion efficiency in these systems, however, requires low-loss power semiconductor switches. Power converters based on GaN could potentially meet the challenge by enabling higher voltage devices with improved efficiency—while also dramatically reducing size and weight of the device, for example.

The PNDIODES-funded research focuses on a process called selective area doping, in which a specific impurity is added to a semiconductor to change its electrical properties and achieve performance characteristics that are useful for electronics. Implemented well, this process can allow for the fabrication of devices at a competitive cost compared to their traditional, silicon-based counterparts. Developing a reliable and usable doping process that can be applied to specific regions of GaN and its alloys is an important obstacle in the fabrication of GaN-based power electronics devices that PNDIODES seeks to overcome. Ultimately, the PNDIODES project teams, including the Shahedipour-Sandvik team and Dr. Sung at SUNY Poly as well as the institution’s partners, will develop new ways to build semiconductors for high performance, high-powered applications like aerospace, electric vehicles, and the grid.

Prof. Shahedipour-Sandkvik team’s research, “Demonstration of PN-junctions by ion implantation techniques for GaN (DOPING-GaN),” will focus on ion implantation as the centerpiece of its approach and use new annealing techniques to develop processes to activate implanted silicon or magnesium in GaN to build p-n junctions, which are used to control the flow of electrons within an integrated circuit. Utilizing a unique technique with a gyrotron beam, a high-power vacuum tube that generates millimeter-wave electromagnetic waves, the team’s research aims to understand the impact of implantation on the microstructural properties of the GaN material and its effects on p-n diode performance.

In addition to this GaN-focused research being conducted by Prof. Shahedipour and her team at SUNY Poly, which also provides hands-on research opportunities for a number of the institution’s students, SUNY Poly and General Electric also lead the New York Power Electronics Manufacturing Consortium (NY-PEMC) with the goal of developing and producing low cost, high performance 6″ silicon carbide (SiC) wafers for power electronics applications. The consortium announced its first successful production of SiC-based patterned wafers in February at the Albany NanoTech Complex’s 150mm SiC line, with production coordinated with SUNY Poly’s Computer Chip Commercialization Center (Quad-C), located at its Utica campus where the SiC-based power chips will be packaged, a process that combines them with a housing that allows for interconnection with an application.

Durcan_Mark_2400x3000_1_smlThe Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, announced Mark Durcan, former CEO of Micron Technology, Inc., and a longtime leader in advancing semiconductor technology, has been named the 2017 recipient of SIA’s highest honor, the Robert N. Noyce Award. SIA presents the Noyce Award annually in recognition of a leader who has made outstanding contributions to the semiconductor industry in technology or public policy. Durcan, who retired as Micron CEO on May 8, 2017, will accept the award at the SIA Annual Award Dinner on Tuesday, Nov. 14, 2017 in San Jose, an event that will also commemorate SIA’s 40th anniversary.

“Throughout his impressive career, Mark Durcan has demonstrated the best the semiconductor industry has to offer: hard work, ingenuity, and a relentless focus on promoting innovation,” said John Neuffer, president and CEO, Semiconductor Industry Association. “From his engineering roots to his recent work leading one of the world’s top manufacturers of memory products, Mark has strengthened our industry, advanced semiconductor technology, and reinforced America’s leadership of the global semiconductor market. On behalf of the SIA board of directors, it is a pleasure to announce Mark’s selection as the 2017 Robert N. Noyce Award recipient in honor of his outstanding accomplishments.”

A 30-year company veteran, Durcan rose from his first role as a Process Integration Engineer to Chief Technical Officer, President, and, ultimately, CEO in 2012. A key technical decision maker in bringing Micron’s next-generation technologies to market, Durcan expanded Micron’s global presence and enhanced its capabilities with strategic acquisitions, including Elpida (2012) and Rexchip (2012) and Inotera Memories, Inc. (2016). He also forged long-lasting partnerships with industry leaders such as Intel.

Durcan served as Chairman of the Micron Technology Foundation, Inc., which was formed to advance STEM education and support civic and charitable institutions in the communities in which Micron has facilities. He also currently serves on the board of directors for AmerisourceBergen Corp. and St. Luke’s Health System, a non-profit hospital system in Idaho. Durcan earned both bachelor’s and master’s degrees in chemical engineering from Rice University.

“It is a true honor to be selected for this award, and to join the ranks of its distinguished recipients, who are industry pioneers and icons,” said Durcan. “Nothing that I have accomplished during my career would have been possible without the influence of so many innovative and dedicated colleagues at Micron as well as our customers, suppliers, and partners. It is with sincere appreciation for their contributions to our industry that I gratefully accept this award.”

The Noyce Award is named in honor of semiconductor industry pioneer Robert N. Noyce, co-founder of Fairchild Semiconductor and Intel.

Leti today announced that the European FP7 project PLAT4M has now been completed with results that exceeded expectations.

Si photonics has long been expected to bring substantial breakthroughs in very high speed data communications, telecommunications and supercomputing. In addition, it is one of the most promising industrial-production candidates because of its potential for large-scale and low-cost production capability in existing CMOS foundries.

The European Commission launched the 15-member PLAT4M project in 2012 to build a Si photonics supply chain in Europe that would speed industrialization of the technology by enabling its seamless transition to commercial production.

The main objective of PLAT4M was to advance existing silicon photonics research foundries and seamlessly transition to pilot line operation and industrial manufacturing of products based on silicon photonics. The supply chain is based on three different but complementary technology platforms of Leti, STMicroelectronics and imec.

Leti Platform

Leti’s 8,500m2 cleanroom facility includes a 200mm pilot line that enables fabrication of passives, detectors, modulators and integrated lasers with a focus on high-bandwidth devices. The project team developed a new Si-photonic platform based on a 310nm silicon film on top of an 800nm buried oxide (BOX) on a high-resistivity silicon substrate. Since the targeted applications for the project were O-band transceivers and receivers, most of the developed devices are suitable for 1310nm operations.

CEA-LETI has developed 3 PDKs which are dedicated to Multi Project Wafers (MPW) runs on this silicon photonics technology which is now offered via the brokers CMP and Europractice. Moreover, III-V Lab has designed and co-fabricated a state-of-the-art integrated hybrid III-V/Si transmitter using a wafer bonding technique on this platform.

STMicroelectronics Platform 

STMicroelectronics, the first 300mm wafer silicon photonics device manufacturer, is a key solution provider for 100 Gbps transceiver products since 2016. In parallel to its industrial activity, during the PLAT4M project ST developed another silicon photonics technology aimed at generating and nurturing further application specific industrial nodes. This technology platform creates an advanced photonic nanoscale environment, and combines state-of-the-art CMOS foundry tools with the flexibility necessary to support R&D efforts. Strong collaboration with research partners such as CEA LETI and University Paris Sud have been devoted to advanced studies in power consumption management, optical excess loss reduction and higher data-rate transmissions using complex modulation formats, signal multiplexing and higher Baud-rate devices. With R&D exploration that goes as far as core-to-core optical interposers, ST has also evaluated notions of device and circuit footprints toward Large System Integration (LSI).

In the context of PLAT4M, the participants chose a 4×25G transceiver as a Wavelength Division Multiplexing (WDM) data-communication demonstrator to validate both LETI and ST R&D platforms. The device functionalities were evaluated for compatibility with the 100GBase-LR4 standard, implying a signal transmission over 4 channels, spaced by 800 GHz around 1310 nm window, one fiber out and one fiber in.

imec Platform

In the course of the PLAT4M project imec has consolidated and further developed its silicon photonics technology platform ISIPP25G using its 200mm pilot line facilities located in Leuven to support industrial prototyping for various applications and markets. The imec platform component portfolio has been expanded to specific devices for sensing and high power free space applications. Furthermore, imec’s technology is supporting state-of-the-art modulation and detection at 50Gb/s and beyond with a variety of modulator options (GeSi EAM, Si MZM, Si MRM) now offered under its ISIPP50G technology along with both edge and surface fiber coupling technology and a library of O-Band and C-Band high quality passive components.

The technology is accessible through imec’s PDK, which is supported by software tools from several vendors including project partner PhoeniX Software. In collaboration with Mentor, a Siemens business, imec has also explored LVS verifications to reduce design errors and performed litho-friendly design analysis to improve the patterning predictability. Using the imec technology with new processing steps, TNO has demonstrated a multi-channel ring resonator based sensor system. Polytec demonstrated the operation of Multichannel Laser Doppler Vibrometer. THALES has demonstrated an integrated FMCW LiDAR system with 8 switchable output channels, enabling to scanning directions as well as a coherent beam combiner with 16 beams with linear operation up to a maximum input power of 26dBm. The thermal phase-shifter elements achieved a power efficiency of 10mW for a p-phase shift.

Finally, imec has demonstrated new advances in its technology such as a very low loss silicon waveguide technology (~0.6dB/cm for a 220nmx450nm waveguide) applying leading edge CMOS patterning technology developed in its 300mm pilot line with immersion lithography. It has also demonstrated a further reduction of thermal phase-shifter elements down to 4mW for a p-phase shift.

In an Unified Design Environment

The PLAT4M project has led to a qualitative leap of the design flow for silicon photonics, allowing the photonics community to design more complex and more robust circuits. Mentor and PhoeniX Software have worked closely together on an integrated electronics/photonics co-design workflow. This has been accomplished by building on existing tool-sets wherever possible and developing new technologies when required.

The supply chain includes EDA solutions such as Mentor’s Pyxis™ and Calibre®, which were extended to “understand” photonics. Interfaces were developed between these tools and Photonic IC design solution OptoDesigner from PhoeniX Software to create integrated design flows using the best practices from both photonics and electronics design. In addition, process design kit elements were developed for Mentor’s Calibre DRC, Calibre LVS, and Pyxis tools, incorporating new components, added models and fabrication information.

Producing a Packaging toolkit 

Packaging played a key role in the development of the project demonstrators. The skills and processes developed by Aifotec and Tyndall, advanced the development of the Silicon Photonic packaging toolkit. This toolkit establishes standardised packaging processes for optical fibres, active devices, electronic components and thermo-mechanical systems to ensure that PICs can be more easily packaged in a timely and cost-effective way. A design rule document was made available through EuroPractice by Tyndall and also implemented into PDKs for OptoDesigner.

Perspectives 

“The consortium developed advanced technologies and tools by building a coherent design flow, demonstrating manufacturability of elementary devices and process integration, and developing a packaging toolkit,” said Jean-Marc Fedeli, coordinator of the PLAT4M project. “The high level of maturity of the technology offered by these platforms makes them readily accessible to a broad circle of users in a fabless model.”

By Pete Singer

At a SEMICON West press conference yesterday, SEMI released its Mid-year Forecast. Worldwide sales of new semiconductor manufacturing equipment are projected to increase 19.8 percent to total $49.4 billion in 2017, marking the first time that the semiconductor equipment market has exceeded the market high of $47.7 billion set in 2000. In 2018, 7.7 percent growth is expected, resulting in another record-breaking year ─ totaling $53.2 billion for the global semiconductor equipment market.

Figure 1 copy

“It’s really an exciting time for the industry in the terms of technology, the growth in information and data and that’s all going to require semiconductors to enable that growth,” said Dan Tracy, senior director, IR&S at SEMI.

The average of various analysts forecast the semiconductor industry in general 12% growth for the year. “It’s a very good growth year for the industry,” Tracy said. “In January, the consensus was about 5% growth for the year and with the improvement in the market and the firmer pricing for memory we see an increase in the outlook for the market.”

The SEMI Mid-year Forecast predicts wafer processing equipment is anticipated to increase 21.7 percent in 2017 to total $39.8 billion. The other front-end segment, which consists of fab facilities equipment, wafer manufacturing, and mask/reticle equipment, will increase 25.6 percent to total $2.3 billion. The assembly and packaging equipment segment is projected to grow by 12.8 percent to $3.4 billion in 2017 while semiconductor test equipment is forecast to increase by 6.4 percent, to a total of $3.9 billion this year.

“Based on the May outlook, we are looking at a record year in terms of tracking equipment spending. This is for new equipment, used equipment, and spending related to the facility that installed the equipment. It will be about a $49 billion market this year. Next year, it’s going to grow to $54 billion, so we have two years in a row of back to back record spending,” Tracy said.

In 2017, South Korea will be the largest equipment market for the first time. After maintaining the top spot for five years, Taiwan will place second, while China will come in third. All regions tracked will experience growth, with the exception of Rest of World (primarily Southeast Asia). South Korea will lead in growth with 68.7 percent, followed by Europe at 58.6 percent, and North America at 16.3 percent.

SEMI forecasts that in 2018, equipment sales in China will climb the most, 61.4 percent, to a total of $11.0 billion, following 5.9 percent growth in 2017. In 2018, South Korea, Taiwan, and China are forecast to remain the top three markets, with South Korea maintaining the top spot to total $13.4 billion. China is forecasted to become the second largest market at $11.0 billion, while equipment sales to Taiwan are expected to reach $10.9 billion.

Figure 2

Each year at SEMICON West, the “Best of West” awards are presented by Solid State Technology and SEMI. More than 26,000 professionals from the electronics manufacturing supply chain attend SEMICON West and the co-located Intersolar. The “Best of West” award was established to recognize new products moving the industry forward with technological developments in the electronics supply chain.

Selected from over 600 exhibitors, SEMI announced today that the following Best of West 2017 Finalists will be displaying their products on the show floor at Moscone Center from July 11-13:

  • Mentor, a Siemens Business: Tessent® Cell-Aware Diagnosis – With FinFETs in high volume, finding systematic yield issues at the transistor level is important. The Tessent Cell-Aware Diagnosis technology significantly improves diagnosis of defects beyond the inter-connect and inside the logic cells. (Process Control, Metrology and Test Category; North Hall Booth #6661)
  • Microtronic Inc.: EAGLEview 5 Macro Defect Management Platform – EagleView 5 is the new, yield-enhancing, breakthrough macro defect inspection platform that was developed – and deployed in production — through collaboration with several leading device manufacturers who wanted to standardize and unify wafer defect management throughout their fab. Innovations include: dramatically improved defect detection; level-specific sorting; and integration with manual microscopes. (Process Control, Metrology and Test Category; North Hall Booth #5467)
  • SPTS Technologies Ltd: SentinelTM End-Point Detection System for Plasma Dicing after Grind – The Sentinel™ End-Point Detection System improves the control of plasma dicing processes and protects taped wafers for improved yields.  In addition to signaling exposure of the tape, Sentinel™ also detects loss of active cooling during the process to enable intervention to prevent yield loss. (Process Control, Metrology and Test Category; West Hall Booth #7617)
  • TEL: Stratus P500 – The Stratus P500 system electroplates panel substrates with wafer level processing precision.  As redistribution layers (RDL) reduce to widths below 10 µm line/space, and package sizes increase, conventional plating systems are challenged to meet system-on-package requirements. The P500 makes panel scale fine line RDL and feature filling applications possible. (Assembly/Packaging Solutions Category; North Hall Booth #6168)

Congratulations to each of the Finalists. The Best of West Award winner will be announced during SEMICON West (www.semiconwest.org) on Wednesday, July 12, 2017.

BY PETE SINGER, Editor-in-Chief

What if the automotive industry had achieved the incredible pace of innovation as the semiconductor industry during the last 52 years? A Rolls Royce would cost only $40, go around the world eight times on a gallon of gas, and have a top speed of 2.4 million miles per hour.

That point was made by Subi Kengeri speaking at The ConFab in May. Kengeri is vice president, CMOS Business Unit, at GlobalFoundries. He also noted that if one of today’s high performance graphics chips were produced using 1960 vs state-of-the-art “it would be the size of a football field.”

Clearly, no other industry can match the pace of innovation of the semiconductor industry. “The transistor count per square inch in 1965 was roughly 100. In 52 years, if you follow Moore’s Law of 2 years per innovation cycle, that gives 26 innovation cycles. That’s 100 millionX improvement (2X26),” Kengeri noted.

Of course, there has been plenty of innovation in the automotive industry. Interestingly, most of the exciting new innovations such as backup cameras, collision avoidance, navigation/ infotainment, self-parking, and anti-lock brakes are only possible because of semiconductor technology.

Kengeri said that Moore’s Law scaling will continue – “there’s no question about it,” he said – but there’s a growing need for new innovation to address the increasingly diverse array of semicon- ductor applications. These are driven by growth in mobile computing, development in IoT computing, the emergence of intelligent computing and augmented/virtual reality.

“Leading edge innovation will continue and all the leading manufacturers continue to invest, whether it is litho scaling in terms of EUV, or device archicture,” Kengeri said. “What is really important is how do we continue to innovate, how do we continue to get the value at competitive costs? Trying to get the scaling at any cost is not what is needed in the majority of the markets. It’s still okay at the very high end, for CPUs and servers, but in all markets, managing cost is really critical.”

“On top of all of that, we have to continue to deliver on time. Because of the complexity, things aren’t getting slower. We’re doing everything we can do continue to keep the same pace as we used to,” he added.

Kengeri said continued advances mean changing the way we think about innovation. It will require continued technical Innovation (materials and processes, device architecture and design-technology co-optimization), but – perhaps more importantly – business model innovation. This includes new thinking about long-term R&D focus/ investment, shared investments/learning/reuse, and consolidation and collaboration.

Industry experts answer questions about the new standard in a virtual roundtable.

In recent years, energy consumption has decreased due to several innovations that have helped to improve the energy efficiency of process tools and sub-fab equipment, but an increase in the number of processes and the growing complexity of processing at the current node has resulted in a spike in energy consumption in the fab. Approximately 43% of the energy consumed in the fab is due to the processing equipment and, of this, 20% is vacuum and abatement (8% overall).

A new standard from SEMI, E175, defines energy saving modes, which combined with the EtherCAT signaling standard, can help fabs save energy and other gas/utility costs when the tool is not processing and with no impact on subsequent wafer processing.

EtherCAT, based on industrial Ethernet, provides high- speed control and monitoring. It is the communication standard of choice for the latest semiconductor tool controllers to connect to sensors and actuators around the tool, including vacuum and abatement systems.

SEMI E175 defines how process tools communicate with sub-fab equipment, such as vacuum pumps and gas abatement systems, to reduce utility consumption at times when wafers are not being processed by the tool, and returning to full performance when the tool is again required to process wafers. It builds on SEMI E167, which defines communication between the fab host/ WIP controller and the process tools for the purpose of utility saving.

Collaboration between the E175 and EtherCAT groups has seen a harmonization of the communication standards to provide co-ordinated energy saving across devices in the fab.
We invited experts in this area to answer a few questions in a virtual roundtable. The participants are:

• GERALD SHELLEY, Senior Product Manager Communication and Control at Edwards, and the EtherCAT Chair Abatement / Roughing pump working groups, E175 task force.

• MIKE CZERNIAK, Environmental Solutions Business Development Manager at Edwardsm Co-Chair of SEMI International Standards E167 & E175, and campaigner for energy saving

• GINO CRISPIERI, Applied Materials – Past Co-chair of E175 (originally SEMATECH/ISMI, then independent consultant, prior to Applied Materials)

• MARTIN ROSTAN, Executive Director, EtherCAT Technology Group

Q: Please explain what drove the standards work on energy saving and the achievements to date.

SHELLEY: There is increased pressure on the industry to reduce energy and utility saving from both a cost and environmental standpoint. Subfab equipment is a major consumer of utilities, which is wasted when a tool is not in use. Different manufacturers have implemented energy saving solutions, with minimal direct connection to the tool. However, direct tool connection has emerged as the best way to maximize saving without any risk to wafer processing.

CZERNIAK: This work originated in the ISMI part of SEMATECH as a follow-on to generic work aimed at reducing the overall utilities footprint of modern fabs. In response to this and requests from customers, Edwards developed vacuum pumps and gas abatement systems that had energy-saving functionality. However, it soon became clear that the limitation to implementing such savings was the absence of standardised signalling between the process tool and sub-fab equipment.

CRISPIERI: A SEMATECH project around 2009 started to look into opportunities for saving energy in the semiconductor factories. At that time, suppliers of pumps and abatement systems already had started initiatives to provide their own solutions to the initiative. Since that time, the industry has adopted two new standards: SEMI E167 Specification for Equipment Energy Saving Mode Communication (between factory and semicon- ductor equipment) and SEMI E175 Specification for Subsystem Energy Saving Mode Communication (between semiconductor equipment and subsystems).

Q: Please describe how the energy saving task force was born and why you decided to get involved.

CRISPIERI: Back in 2009 while working for SEMATECH in Austin, Texas, prior to SEMATECH’s move the New York, Thomas Huang an assignee for GlobalFoundries to the EHS Program approached and asked me if I would be interested in helping him drive a standard for equipment suppliers to enable their equipment to save energy during idle times. Because of my previous experience working with equipment suppliers and developing standards for equipment and factory communication, I accepted to chair a task force to drive the equipment supplier’s new capability requirement into a standard. At first, we thought it would be an easy task and that everyone would jump to help create and approve the standard in a short amount of time because of its benefits. A two phase approach was defined to drive the standardization process and engage semiconductor and sub-fab equipment suppliers accordingly. It took almost three years to complete the Phase I (2013) and another three to complete the Phase II (2016) standards.

SHELLEY: The task force was an extension of E167 which previously defined the communication into the tool from the supervisory systems, however to achieve maximum benefit signalling to tool subsystems was key and the E175 task force was the result.

CZERNIAK: Following-on from the above, the ISMI working group became a SEMI Standards Task Force and began work at developing a standard, initially for Host to process tool (E167) and then from tool to sub-fab (E175), which I was co-chair for to ensure continuity and clear the signalling “roadblock”.

Q: How have suppliers collaborated on E175?

CRISPIERI: Compared with the suppliers who partic- ipated in SEMI E167 development, the suppliers involved in the development and approval of SEMI E175 were more committed to make it happen and helped drive the standardization process to conclusion much more efficiently. Edwards, AMAT, TEL, Hitachi- Kokusai and DAS-Europe regularly participated and provided inputs to standardize behavior and require- ments for their own equipment. We run into some difficulty getting aligned with other standard activities that were driven by SEMI’s EHS Committee because their changes affected our standardization process. I must note that the overall participation was excellent in particular from Edwards Vacuum and AMAT.

ROSTAN: Within the ETG Semiconductor Technical Working Group individual task groups already had multiple suppliers collaborating on the detail of the EtherCAT profiles for all devices, with technical support from the EtherCAT Technical Group. We were fortunate to have a delegate from Edwards in both the Semi E175 Task Force and key EtherCAT Task Groups to informally broker agreement between the teams.

SHELLEY: The suppliers were able to use their collective experience to work through a number of options to find the optimum way of controlling subfab equipment, tackling variability in wakeup time and control architec- tures between device types and equipment technology.

CZERNIAK: Suppliers, automation providers, tool OEMs and end-users have all collaborated to help develop a standard that works for everyone and aligns with earlier standards like S23.

Q: How was the EtherCAT collaboration beneficial to E175?

SHELLEY: By sharing information and understanding in real time we demonstrated the E175 concept is achievable using the favored protocol for new tool platforms and defined how it would be implemented. We co-operated to take both these standards to alignment in one simul- taneous step, saving considerable committee time on both sides that would have been necessary to resolve any divergence of the detail.

ROSTAN: By devising the implementation of E175 in parallel the EtherCAT Task Groups involved were able to feedback detailed technical proposals and show the E175 standard could be implemented relatively easily within the existing EtherCAT standards.

CRISPIERI: Participation and collaboration from the EtherCAT Working Group was critical to accelerate the implementation and adoption of the standard. Dry Contacts and EtherCAT communication protocol messages were added to two Related Information sections and included in the SEMI E175 standard at the time of its publication.

CZERNIAK: This enables a “richer” signalling environment than simple dry contacts (which are also supported) that enables even greater utility savings to be made.

Q: How has EtherCAT been able to support the require- ments of the tool and Semi E175?

CZERNIACK: By providing timing information; the longer the time the tool is inactive, the greater the savings possible.

ROSTAN: As the control network of choice for the latest semiconductor tools, EtherCAT has been ideally placed to support enhancements, such as the energy saving connectivity increasingly being requested by the fabs. In particular, it was good to see the Pump and Abatement Task Groups of the existing Semiconductor Technical Working Group formulate an E175 compliant solution within the timescales of the second release of the EtherCAT semiconductor device profiles. The EtherCAT Technology Group was also more than happy to support the publication of extracts of the EtherCAT standards being used as protocol examples in the Imple- mentation guidelines of the Semi E175 document.

SHELLEY: EtherCAT has the fast / deterministic connec- tivity and proven integration with tool controllers that allows E175 functionality to be easily added without any loss of performance. By including the requirements of Semi E175 in the EtherCAT standards, both equipment suppliers and tool vendors can establish energy saving communication quickly and easily.

CRISPIERI: The coordination between EtherCAT Working Group and the SEMI ESEC task force group was conducted by Mr. Gerald Shelley from Edwards Vacuum. With his help and leadership, we reached effortlessly agreement and acceptance for the required messages, parameters and values into the EtherCAT respective Pump and Abatement Profile documents. Havingworking usage scenarios and support from the EtherCAT Working Group has been invaluable.

Q: Why is energy saving important to the industry?

ROSTAN: In the industrial world, EtherCAT users are increasingly using our communication and control technologies to drive down energy consumption. The semiconductor industry operates in parts of the world where energy is a limited and expensive resource, whilst the latest wafer processing requires more power. The manufacturers are therefore in great need for energy saving opportunities, such as when the tool subsystems are not in use.

SHELLEY: The fabs are being squeezed by an increase in the complexity and number of processes involved in manufacturing a wafer, driving consumption up and increasing scarcity of energy supply. This is further compli- cated with associated cost and government pressure to “keep the lights on”.

CRISPIERI: It is not hard to see why is so important for device makers or the semiconductor manufacturing industry to adopt and require energy conservation capabilities in their factories. Energy consumed by many equipment components and support systems, such as pumps and abatement systems, never stop from running even when the equipment is idle and waiting for product to be delivered for processing. These components and support systems can save millions of dollars each year if their power consumption is reduced. This energy consumption reduction extends their life cycle thus reducing costs of maintenance and parts replacement. Any effort to reduce energy consumption helps lower costs and adds gains to not only the manufacturer but to those who have to generate the energy for consumption.

CZERNIACK: Cost reduction is always important, but electrical supply is limited in some areas.