Category Archives: Wafer Level Packaging

BY DR. ZHIHONG LIU, Chairman and CEO, ProPlus Design Solutions

Semiconductor processes have long been a mystery for many circuit designers. They didn’t need to worry about how chips were fabricated most of the time, thanks to the many EDA innovations that make their jobs easier and complex designs possible.

The success of the foundry-fabless business model over the past 20 years has been one of the main drivers of the booming of semiconductor industry. The cooperation between foundries and IC designs in fabless companies for process development worked so well that process engineers and circuit designers only needed to focus on their area of expertise. EDA flows simplified the interaction by using process design kits (PDKs) as the information carrier for circuit designs and sent tapeout databases (GDSII) back to the foundry for chip fabrication. Most designers didn’t need to dig into the process.

That was then. The designer now is forced to understand process and devices when moving to smaller nodes in order to achieve more competitive designs. Because process is the least understood, the loose link between process and design should be enhanced to improve design and tapeout confidence.

Knowing processes and devices would help designers make better use of the process platform and improve designs. Device geometries are getting smaller and new structures such as FinFET and FD-SOI are becoming mainstream leading to complicated device characteristics and SPICE models, the most critical components in the PDK. They represent a process platform’s performance and device characteristics, fundamental to good circuit design. A solid understanding of SPICE models becomes necessary to make full use of the process. This is true not only for designs at advanced nodes at 28nm beyond, such as 16nm, 14nm and10nm, but critical for some refreshed older technologies for IoT/Wearable applications.

Running a full evaluation of process and device performance would provide guidance to better select device types, optimize device sizes and bias conditions, trade-off circuit speed and power. The same logic can be applied to generic circuit designs at any technology node, such as analog
designs at 180nm or above.

This practice is used mostly within IDMs where process and design teams have fairly direct channels to work cooperatively. Recently, fabless companies strengthened links with foundries to under- stand the process and devices to improve design output or for process-circuit co-design for high-end chip designs with more aggressive speed, power and performance specifications.

These efforts are significant. Most companies don’t have the resources and time to build a dedicated team and flow and there have been no available EDA tools dedicated to helping designers understand process and facilitate process development interactions. Increasing time-to-market pressures and tough competition drive the need to a higher priority.

Without an EDA tool, current practices can easily take weeks or months to build, maintain and run a flow by creating scripts or SPICE netlists for different evaluation items. It’s practically impossible to run through the cases to generate a full picture of process platform for designers within a short turnaround time.

As a result, it’s hard to come up with a set standard for process evaluation before using it in design, as efforts can vary for different projects. For a big corporation with many design projects, dealing with multiple foundries, using multiple technology nodes and different process platforms, this type of work is critical to its success however becomes overloaded.

Furthermore, the complexity of SPICE models is exploding. Thousands of parameters in each model and a huge model library file with more than 100K lines of code are quite common. Macro models with complicated layout- dependent effects and random variations add more dimensions of complexity.

Complexity and time pressures are huge. An EDA tool to manage both would be indispensable.

One tool could use the PDK library as the input to explore, compare and verify models. It could help designers under- stand and explore the process-design space to guide process platform selection and enable quick adoption of the process and assist designs. It would help designers dig into the process from different angles, including a high-level summary of the process and device performance, device characteristics, statistical behavior and circuit performance related to the application. This should enable designers quickly adopt and make full use of a process platform that suits their needs.

Mentor Graphics Corporation (NASDAQ:  MENT) today announced the first phase of the new Xpedition printed circuit design (PCB) flow to address the increasing complexity of today’s advanced systems designs. The increasing densities of electronics products are forcing companies to develop highly compact system designs with more functionality, and at lower costs. To efficiently manage the density and performance requirements for advanced PCB systems, the new Xpedition flow provides advanced technologies to enable design and verification of 3D rigid-flex structures, and to automate layout of high-speed topologies with advanced constraints.

“Our customers are industry leaders developing the world’s most advanced electronics systems. They require access to technologies that enable deployment of advanced technologies and techniques, from design for high performance, advanced packaging, growth of rigid-flex, and higher speeds and densities,” said AJ Incorvaia, vice president and general manager, Mentor Graphics Board Systems Division. “To deliver the latest Xpedition Enter­prise flow, we have partnered with our customers to address their strategic initiatives to manage increasing complexity, increase organizational collaboration, drive greater end-product quality, and facilitate enterprise IP management.”

Managing advanced rigid flex design complexity

Flex and rigid-flex PCBs are now found in all types of electronics products, from small consumer devices to aerospace, defense and automotive electronics where high reliability and safety are critical. The Xpedition rigid-flex technology enables a streamlined design process from initial stack-up creation through manufacturing.

Engineers can design complex rigid and flex PCBs in a fully supported 3D environment (3D design and verification—not just a 3D view), resulting in a correct-by-construction methodology for optimum reliability and product quality. 3D verification ensures that bends are in the right position, and elements on the board do not interfere with folding; this can be reviewed early in the design stage to prevent costly redesigns. Users can then export a 3D solid model to MCAD for efficient bi-directional PCB-enclosure co-design.

Integration with Mentor’s leading HyperLynx high-speed analysis technology enables optimization of signal and power integrity across complex rigid-flex stack-up structures. For fabrication preparation, the Xpedition flow provides all flex and rigid information using the ODB++ common data format. This methodology eliminates data ambiguities by clearly communicating the finished board intent to the fabricator. The new Xpedition flow is the optimum solution designed specifically for flex and rigid-flex design, from conception through fabrication output.

“Mentor’s new Xpedition flow provides multiple board outlines, stack-ups, and bend areas which allow us to define a rigid flex within the design environment, and export a folded 3D step model for efficient mechanical design integration,” stated Charles Ietswaard, PCB design engineer at NIKHEF, the national institute for sub-atomic physics in The Netherlands. “The automated rigid-flex capabilities in Xpedition help us manage the growing complexities of today’s advanced PCB systems with ease, higher productivity and overall product reliability.”

SEMI today announced that SEMICON Japan 2016, at Tokyo Big Sight on December 14-16, has increased exhibition and programming to keep pace with high-growth semiconductor segments in Japan. SEMICON Japan, celebrating its 40th anniversary, is the leading electronics event in Japan, with more than 700 exhibitors and 35,000 attendees.

With the world’s largest installed fab capacity of over 4.1 million (200mm equivalent) wafers per month and its diverse product mix, Japan is well-positioned to meet the increasing demands of the new world of electronics – from innovations in mobile technologies to the growing “World of IoT” devices.  SEMICON Japan 2016 connects the players and companies across the electronics manufacturing supply chain by facilitating communications and partnerships. Highlights of the exhibition area include:

  • Themain exhibit zone includes a Front-end Process zone and a Back-end/Materials Process zone.
  • “World of IoT (Internet of Things)”, a “show-within-a-show,” is where semiconductor manufacturing intersects IoT applications including wearable, health care, medical, automotive, and more. The World of IoT this year newly expands its scope to include flexible hybrid electronics (FHE), an essential enabling technology for IoT applications. Exhibiting companies include Japanese flexible and printed electronics companies from key institutes and associations for the industry area.
  • The Sustainable Manufacturing Pavilion, features solutions for the expanding IoT market driving 200mm lines; exhibitors include used and refurbished equipment, cleanroom-related, environmental safety, and more.
  • The Manufacturing Innovation Pavilion showcases innovations for leading-edge lower-cost semiconductor devices; exhibitors include advanced lithography, 2.5D/3D-IC, innovative manufacturing systems, specialty materials, OLED/LED/PE manufacturing equipment and materials.
  • Innovation Village, an interactive exposition showcase arena. Exhibitors are early-stage startups seeking funding, partners, and media exposure in the domain of electronics, materials, IT, tele-communications, bio, med-tech, environment, security or hardware.

For complete information of exhibits and programs, visit www.semiconjapan.org/en.

 

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $79.1 billion during the second quarter of 2016, an increase of 1.0 percent over the previous quarter and a decrease of 5.8 percent compared to the second quarter of 2015. Global sales for the month of June 2016 reached $26.4 billion, an uptick of 1.1 percent over last month’s total of $26.1 billion, but down 5.8 percent from the June 2015 total of $28.0 billion. Cumulatively, year-to-date sales during the first half of 2016 were 5.8 percent lower than they were at the same point in 2015. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Global semiconductor sales increased slightly from Q1 to Q2 but remain behind the pace from last year, due largely to global economic uncertainty and sluggish demand,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Sales into Japan and China have been a bright spot midway through 2016, and a modest rebound in sales is projected during the second half of the year.”

Regionally, sales increased compared to June 2015 in China (1.7 percent), but fell in Asia Pacific/All Other (-11.0 percent), the Americas (-10.8 percent), Europe (-5.5 percent), and Japan (-1.3 percent). Sales were up slightly compared to last month in the Americas (3.0 percent), China (2.2 percent) and Europe (1.7 percent), but down somewhat in Japan (-1.0 percent) and Asia Pacific/All Other (-0.6 percent).

sales graph sales table

Ultratech, Inc. (Nasdaq: UTEK), a supplier of lithography, laser­ processing and inspection systems used to manufacture semiconductor devices and high-brightness LEDs (HBLEDs), as well as atomic layer deposition (ALD) systems, today announced that it has received an ‘Outstanding Supplier Award’ from SJ Semiconductor Corp. Based in China, SJ Semiconductor is a pure play Middle-End-Of-Line (MEOL) semiconductor foundry house specializing in advanced wafer-level packaging. The award was presented to Ultratech by SJ Semiconductor CEO Cui Dong on July 27, at the company’s ‘Phase-I Mass Production, Outstanding Supplier Event’ at their facility in China. This award is further validation of Ultratech’s market leadership position in the advanced packaging lithography segment.

Rezwan Lateef, Ultratech’s General Manager and Vice President of Lithography Products, stated, “Ultratech has maintained its market leadership in the advanced packaging lithography segment by offering superior on-wafer results with industry leading cost-of-ownership and reliability in high-volume manufacturing environments. In recent years, Ultratech has expanded its presence in China, both in personnel and infrastructure, to support the burgeoning Chinese OSAT market. Ultratech believes that the SJ Semiconductor ‘Outstanding Supplier Award’ is a validation of our efforts in this region. We look forward to our continued partnership and to working closely with this valued customer to meet their future production and technology requirements.”

Ultratech is a supplier of lithography steppers for advanced packaging applications that include traditional copper pillar and wafer-level packaging (WLP), as well as the more advanced fan-out WLP and 3D ICs. The AP300 family of lithography systems is built on Ultratech’s customizable Unity Platform, delivering superior overlay, resolution and side wall profile performance while enabling cost-effective manufacturing. These systems are particularly well suited for copper pillar, fan-out, through-silicon via (TSV) and silicon interposer applications. In addition, the platform has numerous application-specific product features to enable next-generation packaging techniques, such as Ultratech’s award winning dual-side alignment (DSA) system, utilized around the world in volume production.

SJ Semiconductor Corp. (SJSemi) and Qualcomm Technologies, Inc., a subsidiary of Qualcomm Incorporated (NASDAQ:  QCOM), jointly announced that SJSemi has begun mass production of 14nm wafer bumping for Qualcomm Technologies. In the wake of 28nm wafer bumping mass production, and with further improvement of its processing techniques and capabilities, SJSemi has become China’s first semiconductor company to enter the industrial chain with 14nm advanced process node mass production. Mass production of the 14nm wafer bumping in China is part of Qualcomm Technologies’ efforts to continuously drive the development of the Chinese integrated circuit industry, and it further reinforces Qualcomm Technologies’ commitment to China through industrial chain optimization, localized services, and superior offers to Chinese customers.

Founded in August 2014, SJSemi is a joint venture between Semiconductor Manufacturing International Corp. (SMIC) and Jiangsu Changjiang Electronics Technology Co., Ltd (JCET). In December 2015, Qualcomm Global Trading Pte Ltd., a subsidiary of Qualcomm Incorporated, participated in an additional investment in SJSemi. SJSemi realized mass production of the 28nm wafer bumping in early 2016, within two years of its inception, and it now ships 12-inch wafers in high volume every month. SJSemi has sharpened its unique competitive edge in 28nm bumping technology by achieving not only a first-class yield rate but also industry-leading key technical indicators such as contact resistance control over high-density copper pillar bumping. SJSemi will continue to expand the capacity of its 12-inch wafer bumping line, securing the supply chain for its customers. Currently, SJSemi has reached the production capacity of bumping 20,000 12-inch wafers per month.

“We are grateful to Qualcomm Technologies for its consistent support. With its assistance, we have managed to set up an advanced 12-inch bumping line with stable and efficient production to offer mass production services to our customers,” said Mr. Dong Cui, Chief Executive Officer of SJSemi. “The mass production of our 14nm wafer bumping technology is in recognition of our capabilities and strengths, and indicates our ability to offer comprehensive services to first-class global customers like Qualcomm Technologies. We expect to continuously keep pace with customer demand, further improve our technical capability, enrich our process methods, and boost our added value to the industrial chain.”

“The 14nm bumping production from SJSemi is very important to Qualcomm Technologies and has begun mass production, which demonstrates SJSemi’s world-class manufacturing capabilities in leading-edge bumping process technology,” said Dr. Roawen Chen, Senior Vice President, QCT global operations, Qualcomm Technologies, Inc. “We are pleased to work with SJSemi to expand our semiconductor supply chain footprint in China, which further shows our commitment to support China’s local IC manufacturing and better serve our Chinese customers.”

Over the past 20 years, China has become increasingly frustrated over the gap between its IC imports and indigenous IC production (Figure 1).  It has oftentimes been quoted over the last couple of years that China’s imports of semiconductors exceeds that of oil.

In its upcoming Mid-Year Update to The McClean Report 2016 (released at the end of this week), IC Insights examines the “Three-Phase” history of China’s attempt at strengthening its position in the IC industry that started in earnest in the late 1990s (Figure 2).

Figure 1

Figure 1

Figure 2

Figure 2

In the late 1990s, China began to contemplate ways to grow its indigenous IC industry and assisted in creating Hua Hong NEC, which was founded in 1997 as a joint venture between Shanghai Hua Hong and Japan-based NEC (it merged with Grace in 2011).  Then, as part of the country’s 10th Five Year Plan (2000-2005), establishing a strong China-based IC foundry industry became a priority.  As a result, pure play foundries SMIC and Grace (now Hua Hong Semiconductor) were both founded in 2000 and XMC was founded in 2006.  This effort is categorized by IC Insights as Phase 1 of China’s IC industry strategy.

In the early 2000s, to help boost the sales of its indigenous foundries, as well as ride the strong wave of fabless IC supplier growth, the Chinese government began attempts to foster a positive environment for the creation of Chinese fabless companies. It should be noted that eight of the current top 10 Chinese fabless IC suppliers were started between 2001 and 2004 and seven of them were in the top 50 worldwide ranking of fabless IC companies last year. This stage of China’s IC industry strategy is labeled by IC Insights as Phase 2.

IC Insights believes that Phase 3 of China’s attempt at creating a strong China-based IC industry began in 2014, just before the start of its 13th Five Year Plan which runs from 2015 through 2020.  As discussed in detail in the Mid-Year Update, this Phase is being supported by a huge “war chest” of cash that is intended to be used to purchase IC companies and their associated intellectual property, provide additional funding to China’s existing IC producers (e.g., SMIC, Grace, XMC, etc.), and to help establish new IC producers (e.g., Sino King Technology, Fujian Jin Hua, etc.).

In 1Q16, the U.S. Department of Commerce slapped an export ban on U.S. IC suppliers’ shipments of ICs to China-based telecom giant ZTE in response to the company allegedly shipping telecommunications equipment to Iran while it was under trade sanctions by the U.S. This ban, if fully enacted, would have a devastating effect on ZTE’s telecom equipment sales (including mobile phones). Thus far, the export ban has been postponed until August 30, 2016 pending further investigation by the U.S. Department of Commerce.

The situation regarding ZTE and the abrupt announcement earlier this year of export controls on the company by the U.S. government sent shock waves throughout the Chinese government as well as China’s electronic system manufacturers.  At this point in time, such potentially drastic measures taken by the U.S. government against such a large Chinese electronics company has bolstered the Chinese government’s resolve to make China more self-sufficient regarding IC component production, spurring increased emphasis on “Phase Three.”

Applied Materials, Inc. today announced the appointment of Judy Bruner to serve on its Board of Directors. Ms. Bruner has also been appointed to serve as a member of the Audit Committee of the Board.

“As a well-respected chief financial officer with deep experience in the global high-tech industry, Judy will be an asset to Applied Materials’ Board of Directors,” said Wim Roelandts, chairman of the board of Applied Materials. “Having built her career in increasingly sophisticated finance roles across some of Silicon Valley’s top hardware companies, she is a welcome addition to our team of directors and will be a valued member of our Audit Committee.”

Judy Bruner served as Executive Vice President, Administration and Chief Financial Officer of SanDisk Corporation, a supplier of flash storage products, from June 2004 until its acquisition by Western Digital in May 2016. Previously, she was Senior Vice President and Chief Financial Officer of Palm, Inc., a provider of handheld computing and communications solutions, from September 1999 until June 2004. Prior to Palm, Inc., Ms. Bruner held financial management positions at 3Com Corporation, Ridge Computers and Hewlett-Packard Company. She currently serves as a member of the board of directors of Brocade Communications Systems, Inc. and a member of the board of trustees of the Computer History Museum.

Worldwide semiconductor capital spending is projected to decline 0.7 percent in 2016, to $64.3 billion, according to Gartner, Inc. (see Table 1). This is up from the estimated 2 percent decline in Gartner’s previous quarterly forecast.

“Economic instability, inventory excess, weak demand for PC’s, tablets, and mobile products in the past three years has caused slow growth for the semiconductor industry. This slowdown in electronic product demand has driven semiconductor device manufacturers to be conservative in increasing production,” said David Christensen, senior research analyst at Gartner. “Looking ahead, it appears the second half of 2016 may see improved demand. However, following Brexit, semiconductor inventory levels may rise in the third and fourth quarters, which could lead to reduced production volumes.”

Table 1

Worldwide Semiconductor Capital Spending and Equipment Spending Forecast, 2015-2018 (Millions of Dollars)

2015

2016

2017

2018

Semiconductor Capital Spending ($M)

64,750.8

64,278.3

66,010.5

68,523.7

Growth (%)

0.3

-0.7

2.7

3.8

Wafer-Level Manufacturing Equipment ($M)

33,248.1

32,890.9

34,842.2

37,704.3

Growth (%)

-1.1

-1.1

5.9

8.2

Wafer Fab Equipment ($M)

31,485.4

31,071.8

32,862.1

35,491.5

Growth (%)

-1.3

-1.3

5.8

8.0

Wafer-Level Packaging and Assembly Equipment ($M)

1,762.7

1,819.1

1,980.1

2,212.9

Growth (%)

4.1

3.2

8.9

11.8

Source: Gartner (July 2016)

The PC, ultramobile (tablet) and smartphone production forecast for the second half of 2016 has been lowered from 2015, as the industry slowdown continues. These reductions have resulted in a forecasted 3 percent decline for the semiconductor market. Memory revenue growth for 2016 is also revised downward compared with the previous forecast, due to a weaker pricing outlook.

“While currency exchange rates are another reason for the ongoing revenue decrease, the aggressive pursuit of semiconductor manufacturing capability by the Chinese government and related investment companies is becoming a major factor,” said Mr. Christensen. “This will dramatically affect the competitive landscape of the global semiconductor manufacturing in the next few years as China becomes a major market for semiconductor usage and manufacturing.”

This research is produced by Gartner’s Semiconductor Manufacturing program. This research program, which is part of the overall semiconductor research group, provides a comprehensive view of the entire semiconductor industry, from manufacturing to device and application market trends. Additional analysis on the outlook for the market can be found at “Forecast: Semiconductor Capital Spending, Worldwide, 2Q16 Update.”

North America-based manufacturers of semiconductor equipment posted $1.71 billion in orders worldwide in June 2016 (three-month average basis) and a book-to-bill ratio of 1.00, according to the June Equipment Market Data Subscription (EMDS) Book-to-Bill Report published today by SEMI.  A book-to-bill of 1.00 means that $100 worth of orders were received for every $100 of product billed for the month.

SEMI reports that the three-month average of worldwide bookings in June 2016 was $1.71 billion. The bookings figure is 2.1 percent lower than the final May 2016 level of $1.75 billion, and is 12.9 percent higher than the June 2015 order level of $1.52 billion.

The three-month average of worldwide billings in June 2016 was $1.71 billion. The billings figure is 7.0 percent higher than the final May 2016 level of $1.60 billion, and is 10.2 percent higher than the June 2015 billings level of $1.55 billion.

“Although order activity slowed for the most recent month,” said Denny McGuirk, president and CEO of SEMI. “Billings activity for equipment companies based in North America are at their highest level since February 2011.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill
January 2016

$1,221.2

$1,310.9

1.07
February 2016

$1,204.4

$1,262.0

1.05
March 2016

$1,197.6

$1,379.2

1.15
April 2016

$1,460.2

$1,595.4

1.09
May 2016 (final)

$1,601.5

$1,750.5

1.09
June 2016 (prelim)

$1,714.0

$1,713.2

1.00

Source: SEMI (www.semi.org), July 2016