Category Archives: Wafer Level Packaging

For more than six decades, the annual IEEE International Electron Devices Meeting (IEDM) has been the world’s largest and most influential forum for technologists to unveil breakthroughs in transistors and related micro/nanoelectronics devices.

That tradition continues this year with a few new twists, including a supplier exhibition and a later paper-submission deadline (August 10) of a final, four-page paper. Accepted papers will appear in the proceedings without any changes. This streamlined process will ensure that even as the pace of innovation in electronics quickens, IEDM remains the place to learn about the latest and most important developments.

The 62nd annual IEDM will be held in San Francisco December 3 – 7, 2016, beginning with a weekend program of 90-minute tutorials and all-day Short Courses taught by industry leaders and world experts in their respective technical disciplines. These weekend events will precede a technical program of some 220 papers and a rich offering of other events including thought-provoking plenary talks, spirited evening panels, special focus sessions on topics of great interest, IEEE awards and an event for entrepreneurs sponsored by IEDM and IEEE Women in Engineering.

“The industry is moving forward at an accelerated pace to match the increasing complexity of today’s world, and a later submission deadline enables us to shorten the time between when results are achieved in the lab and when they are presented at the IEDM,” said Dr. Martin Giles, IEDM 2016 Publicity Chair, Intel Fellow, and Director of Transistor Technology Variation in Intel’s Technology and Manufacturing Group.

Tibor Grasser, IEDM 2016 Exhibits Chair, IEEE Fellow and Head of the Institute for Microelectronics at TU Wien, added, “We have decided to have a supplier exhibition in conjunction with the technical program this year, as an added way to provide attendees with the knowledge and information they need to advance the state-of-the-art.”

Here are some of the noteworthy events that will take place at this year’s IEDM:

Special Focus Sessions

  • Wearable Electronics and Internet of Things
  • Quantum Computing
  • System-Level Impact of Power Devices
  • Ultra-High-Speed Electronics

90-Minute Tutorials – Saturday, Dec. 3

A program of 90-minute tutorial sessions on emerging technologies will be presented by experts in the fields, bridging the gap between textbook-level knowledge and leading-edge current research. Advance registration is recommended.

  • The Struggle to Keep Scaling BEOL, and What We Can Do Next, Rod Augur, Distinguished Member of the Technical Staff, GLOBALFOUNDRIES
  • Electronic Circuits and Architectures for Neuromorphic Computing Platforms, Giacomo Indiveri, Univ. of Zurich and ETH Zurich
  • Physical Characterization of Advanced Devices, Robert Wallace, Univ. Texas at Dallas
  • Present and Future of FEOL Reliability—from Dielectric Trap Properties to Reliable Circuit Operation, Ben Kaczer, Principal Scientist, imec
  • Spinelectronics: From Basic Phenomena to Magnetoresistive Memory (MRAM) Applications, Bernard Dieny, Chief Scientist, Spintec CEA
  • Technologies for IoT and Wearable Applications, Including Advances in Cost-Effective and Reliable Embedded Non-Volatile Memories, Ali Keshavarzi, Vice President of R&D, Cypress Semiconductor

Short Courses – Sunday, Dec. 4

The Short Courses provide the opportunity to learn about important areas and developments, and to benefit from direct contact with world experts. Advance registration is recommended.

  • Technology Options at the 5-Nanometer Node, organized by An Steegen and Dan Mocuta of imec (Sr. Vice President of Technology Development/Director of Logic Device and Integration, respectively)
  • Design/Technology Enablers for Computing Applications, organized by John Chen, Vice President of Technology and Foundry Management, NVIDIA

Plenary Presentations – Monday, Dec. 5

  • Memory Scaling – Challenges and Opportunities, Seok-Hee Lee, Executive Vice President and Head of DRAM Product and Technology, Hynix
  • Brain-Inspired Computing, Dharmendra S. Modha, IBM Fellow and Chief Scientist for Brain-Inspired Computing, IBM
  • Differentiating Technologies and Novel Opportunities for the Future Internet of Everything: the Quest for Power Efficiency, Marie-Noëlle Semeria, CEO, Leti

Evening Panel Session – Tuesday evening, Dec. 6

The IEDM offers attendees two evening sessions where experts give their views on important industry topics. Audience participation is encouraged to foster an open and vigorous exchange of ideas.

  • How Will the Semiconductor Industry Change to Enable 50 Billion Connected Devices? Moderator: Prof. Aaron Thean, University of Singapore
  • Challenges and Opportunities for Neuromorphic and Machine Learning, Moderator: Marc Duranton, Sr. Member of the Embedded Computing Lab, CEA

Entrepreneurs Lunch – Wednesday, Dec. 7

Jointly sponsored by IEDM and IEEE Women in Engineering, the Entrepreneurs Lunch will feature Vamsee Pamula, co-founder of Baebies, Inc. a company developing digital microfluidics technology for newborn screening and pediatric testing. Pamula co-founded Baebies in 2014, following the sale of a predecessor microfluidics company that he also co-founded – Advanced Liquid Logic – to Illumina, Inc.

Vamsee has years of experience with digital microfluidics. He has served as Principal Investigator on several National Institutes of Health-funded projects, and has led many talks and published more than 60 articles, five book chapters and a book on the topic. He has more than 200 issued and pending patents, a PhD in Electrical and Computer Engineering from Duke University, and also serves as Adjunct Professor there.

Late-News Deadline

A very limited number of Late News Papers will be accepted, focusing on very recent developments, with a submission deadline of September 12. The submission format is the same as for regular papers.

Further information about IEDM

For registration and other information, visit www.ieee-iedm.org.

BY DR. PHIL GARROU, Contributing Editor

At the ECTC conference in May, in the “Advances in Fan Out Packaging” session, Matt Lueck of RTI International discussed the results of their joint program with X-Celeprint.

A common aspect to all fan-out packaging is the requirement to physically assemble devices into dispersed arrays, often called reconfigured wafers, which provides the real estate needed to fan-out. Devices made in sub-mm chip sizes can impose cost and performance challenges to FO-WLP using serial pick-and place assembly technologies. RTI and X-Celeprint joined forces to develop a fan out package for sub mm IC using the X-Celeprint massively parallel assembly technology called micro transfer-printing, which is well-suited for handling very thin and fragile devices.

In their micro transfer-printing technology a polymer layer is first applied to the substrate before the assembly process, and the devices are assembled in a face-up configuration. Following the formation of the reconfigured substrates, conventional redistribution layer (RDL) and solder ball processing was performed. Two different photo-imageable spin on dielectrics, HD4100 PI and Intervia 8023 epoxy, were used as the RDL dielectrics. The fan-out package contains no molding compound and is made using standard wafer-level packaging tools.

There are potential benefits from fan-out packaging strat- egies that do not require molding compound. The process described here does not suffer from the “die drift” that occurs during compression molded fan-out packaging which often requires special adaptive alignment techniques. It also does not suffer from the wafer and package warpage that can occur in molding compound based fan-out packages.

Micro-transfer printing was used to assemble reconfigured wafers of devices (80um x 40um chips with a redistribution metal and six contact pads), onto 200mm wafers. After assembly, they undergo a standard wafer level redistribution and bumping process. The final fan-out package pitch on the 200 mm wafer is 1.4mm x 1.0mm with six 250 μm solder bumps. The fan-out packages were assembled and reflowed onto FR4 test boards.

The Figure shows (A) the chiplet source wafer after partial removal of chiplets with the elastomer stamp; (B) a completed fan out package before solder ball placement; (C) close-up of the interconnect to the chi pads; (D) Final FO-WLP. Initial yields are reported to be 97%.

Screen Shot 2017-04-21 at 12.08.29 PM

Two PCB test vehicles populated with 60 die each were built for thermal cycle testing. The board level thermal cycle testing was run under -40°C to 125°C. None of the die showed more than 0.2 ohm change in average resistance.

By Pete Singer, Editor-in-Chief

Fan-out wafer level packaging (FOWLP) is gaining traction, leading to higher I/Os and larger formats, and new mobile displays are pushing the limits of pixel per inch (PPI) while also moving to larger formats. Both trends are driving new requirements for lithography equipment, including steppers, track systems and photoresists. Both packages and displays are employing new types of materials and thinner substrates as well. “There’s a lot of commonality between the advanced display technologies and packaging technologies,” said Rich Rogoff, vice president and general manager of Rudolph’s Lithography Systems Group. “The step-and-repeat system approach is ideally suited to address those challenges.”

Key lithographic challenges of advanced packaging and displays are shown in Figure 1.

Figure 1. Key lithographic challenges of advanced packaging and displays are shown.

Figure 1. Key lithographic challenges of advanced packaging and displays are shown.

Rogoff said another big challenge is the ability to manage what he calls dimensionally unstable material. “These are materials that change with time, with temperature, with humidity and with process steps, every time they come back through a lithography step they can change form. Steppers have to be able to deal with that,” he said.

Rogoff also said he’s seeing changes in imaging chemistries which are creating another challenges. “We’re doing things now from broadband resist to i-line resist, from thin-films to thick films, to dry films to organic chemistries. It’s all over the field here with respect to what types of chemistries are being used to image, and the challenge is of course when going from a thick material to a thin material and varied compositions, you get a much different kind of imaging characteristic. Really you need to be able to manage all of those without having to change your lithography system,” he said.

In packaging applications, large topography is yet another challenge. In a fan-out type of situation, there can be significant differences in heights between the substrate and the die, for example. “You’re having to image through, in some cases, >20 microns of photoresist for a two or three micron line, and that becomes a very big challenge,” Rogoff said. “The package size and the display sizes are also getting bigger, and so you need to try to get as much as you can into one imaging field. The lenses need to have a very large field of view.”

FOWLP, where individual die are connected on redistribution layer, is expected to lead to a major change in process equipment. Today, die are “reconstituted” on a wafer. In the future, as volume increases, a move to high density panels is expected. “As the demand goes up, certainly panels make the most sense,” Rogoff said.

Earlier this year, Rudolph announced that a leading outsourced assembly and test facility (OSAT) has placed an order for the JetStep Lithography System for the semiconductor advanced packaging industry’s first panel manufacturing line. “That’s the first true panel fan-out application that’s moving forward, especially in the OSAT world,” Rogoff said.

While the stepper part of the litho equation is ready for “panelization,” the rest of the industry infrastructure is working from two directions. One, from printed-circuit board type solutions where thick resist are dry films. The other, from the display side, uses thin chemical resists. “Somehow we have to bridge the gap between a thin film and a thick film,” Rogoff said. “These are some of the infrastructure things that are still being worked out, but I think those are relatively easy to solve.”

Elvino da Silveira, Rudolph’s vice president of marketing, said he’s seen some recent changes. “Last year, when we were talking to the various customer and partners that we interact with in terms of the panel level fan out, everybody was really focused on doing reconstituted panels, the face-down type chips. Basically taking the EWLB process and scaling it up to the panel level. As time has gone on, and with TSMC bringing out InFO and so forth, there have been several players that are more open to doing this on a carrier. It adds some costs, but at least based on the general feedback we’ve gotten from some of the industry , scaling up to the larger substrate offsets the additional cost of the carrier,” he said.

Figure 2 (presented at SEMI’s Industry Strategy Symposium in January by Babak Sabi, corporate vice president, director, assembly and test technology department, Intel Corp.) shows the expected progression of packaging technology as IO density increases. Flip chip, ball grid array on the left (the orange box) has 15-60 micron feature sizes depending on the layer and the type of feature being exposed.

Figure 2. As IO density increases, new packaging technologies will be required (SWIFT, SLIT, SLIM and INFO-WLP are trademarks of Amkor, ASE and TSMC). Source: Intel (SEMI Industry Strategy Symposium 2016)

Figure 2. As IO density increases, new packaging technologies will be required (SWIFT, SLIT, SLIM and INFO-WLP are trademarks of Amkor, ASE and TSMC). Source: Intel (SEMI Industry Strategy Symposium 2016)

The next generation, (the yellow box) indicates fan out packaging. “We’re still more towards that boundary between the orange and the yellow, because really no one’s producing sub-five microns in HVM today. Most of it is between 5 and 10,” da Silveira said.

The next level (the green box) indicates embedded technology, such as Intel’s Embedded Multi-die Interconnect Bridge (EMIB). Instead of using a large silicon interposer typically found in other 2.5D approaches, EMIB uses a very small bridge die, with multiple routing layers. Here, the IOs are getting much higher, and the feature sizes are getting pushed toward two microns. As technology moves from the yellow box to the green box, expect a switch from wafers to panels.

9:00 am – 10:00 am
“CONNECT” Executive Summit
SEMI’s Denny McGuirk moderates a panel of execs from Lam, Qualcomm, Intel and Entegris
Keynote Stage

9:00 am – 3:00 pm
Women in Technology Forum
Room 304, Esplanade

12:30 am –2:00 pm
The Business Case for Supplier Diversity: Why it Matters to You
Intel presentation and panel discussion
Rm 308, Esplanade

1:00 pm – 5:00 pm
From Collision to Convergence: Co-creating Soutions in the Semiconductor and MEMS/Sensors Industries
San Francisco Marriott Marquis

2:00 pm – 4:00 pm
World of IoT Innovation
Innovation and IoT Theater

3:00 pm –4:30 pm
Bulls & Bears Panel
W Hotel

200mm fabs reawakening


July 13, 2016

By David Lammers, Contributing Editor

Buoyed by strong investments in China, 200mm wafer production is seeing a re-awakening, with overall 200mm capacity expected to match its previous 2006 peak level by 2019 (Figure 1).

Figure 1. By 2019, 200mm fab capacity should be close to the previous peak seen in 2006, according to SEMI. Several new 200mm fabs are expected to open in China. (Source: SEMICON West presentation by Christian Dieseldorff).

Figure 1. By 2019, 200mm fab capacity should be close to the previous peak seen in 2006, according to SEMI. Several new 200mm fabs are expected to open in China. (Source: SEMICON West presentation by Christian Dieseldorff).

Speaking at a SEMI/Gartner market symposium at SEMICON West, SEMI senior analyst Christian Dieseldorff said over the next few years “we don’t see 200mm fabs closing, in fact we see new ones beginning operation. To me, that is just amazing.”

The numbers back up the rebound. Excluding LEDs, the installed capacity of 200mm fabs will reach about 5.3 million wafers per month (wspm) in 2018, almost matching the 2007 peak of 5.6 million wspm. As shown in Figure 1, By 2019 as new 200mm fabs start up in China, 200mm wafer production will surge beyond the previous 2007 peak, a surprising achievement for a wafer generation that began more than 25 years ago. Figure 2 shows how capacity, which held steady for years, is now on the increase.

Figure 2. 200mm fab capacity, which remained relatively constant for years, is now increasing.

Figure 2. 200mm fab capacity, which remained relatively constant for years, is now increasing.

Case in point: On the opening day of Semicon West, Beijing Yangdong Micro announced a new OLED 200mm fab that will be opening in the second half of 2018 to make OLED drivers, according to Dieseldorff.

Over the past few years, Japan-based companies have closed 10 200mm fabs, mostly outdated logic facilities, while expanding production of discrete power and analog ICs on 200mm wafers. But with China opening several new 200mm fabs and the expansions of existing 200mm fabs worldwide, SEMI sees an additional 274,000 wafer starts per month of 200mm production over the 2015-2018 period, adding expansions and additional fabs, and subtracting closed facilities.

“One message from our research is that we believe the existing 200mm fabs are full. Companies have done what they can to expand and move tools around, and that is coming to an end,” he said. SEMI reckons that 19 new 200mm fabs have been built since 2010, at least six of them in China.

SEMI’s Christian Dieseldorff.

SEMI’s Christian Dieseldorff.

Dieseldorff touched on a vexing challenge to the 200mm expansion: the availability of 200mm equipment. “People have problems getting 200mm equipment, used and even new. The (200mm) market is not well understood by some companies,” he said. With a shortage of used 200mm equipment likely to continue, the major equipment companies are building new 200mm tools, part of what Dieseldorff described as an “awakening” of 200mm manufacturing.

 

China is serious

Sam Wang, a research vice president at Gartner who focuses on the foundry sector, voiced several concerns related to 200mm production at the SEMI/Gartner symposium. While SMIC (which has a mix of 200mm and 300mm fabs) has seen consistently healthy annual growth, the five second-tier Chinese foundries – — Shanghai Huahong Grace, CSMC, HuaLi, XMC, and ASMC — saw declining revenues year-over-year in 2015. Overall, China-based foundries accounted for just 7.8 percent of total foundry capacity last year, and the overall growth rate by Chinese foundries “is way below the expectations of the Chinese government,” Wang said.

The challenge, he said, is for China’s foundries which rely largely on legacy production to grow revenues in a competitive market. And things are not getting any easier. While production of has shown overall strength in units, Wang cautioned that price pressures are growing for many of the ICs made on 200mm wafers. Fingerprint sensor ICs, for example, have dropped in price by 30 percent recently. Moreover, “the installation of legacy nodes in 300mm fabs by large foundries has caused concern to foundries who depend solely on 200 mm.”

But Wang emphasized China’s determination to expand its semiconductor production. “China is really serious. Believe it,” he said.

New markets, new demand

The smart phone revolution has energized 200mm production, adding to a growing appetite for MEMS sensors, analog, and power ICs. Going forward, the Internet of Things, new medical devices, and flexible and wearable products may drive new demand, speakers said at the symposium.

Jason Marsh, director of technology for the government and industry-backed NextFlex R&D alliance based in San Jose, Calif., said many companies see “real potential” in making products which have “an unobtrusive form factor that doesn’t alter the physical environment.” He cited one application: a monitoring device worn by hospital patients that would reduce the occurrence of bed sores. These types of devices can be made with “comparatively yesteryear (semiconductor) technology” but require new packaging and system-level expertise.

Legacy devices made on 200mm wafers could get a boost from the increasing ability to combine several chips made with different technologies into fan out chip scale packages (FO CSPs). Bill Chen, a senior advisor at ASE Group, showed several examples of FO CSPs which combine legacy ICs with processors made on leading-edge nodes. “When we started this wafer-level development around 2000 we thought it would be a niche. But now about 30 percent of the ICs used in smart phones are in wafer-level CSPs. It just took a lot of time for the market forces to come along.”

More coverage from this year’s SEMICON West can be found here.

Rudolph Technologies, Inc. (NYSE: RTEC) today unveiled its new patented Clearfind technology, which can detect organic defects that are difficult or impossible to see with conventional white-light imaging techniques. Organic contaminants are often the root cause of field failures, which occur after the material has been exposed to operating conditions for extended periods. Rudolph has been actively collaborating with several key customers to fully understand their inspection challenges and how the new technology addresses them, and plans to incorporate Clearfind technology in its upcoming defect inspection systems for advanced packaging applications.

“As advanced packaging processes become more complex, process windows are shrinking and manufacturers are seeking better methods for control and inspection that balance the need for high throughput against the ‘escape’ of true defects and the ‘false positive’ detection of nuisance defects,” said Mike Goodrich, vice president and general manager of Rudolph’s Process Control Group. “Organic defects, in particular, have become more troublesome as die interconnects shrink and there is less surface area for good adhesion. Clearfind technology will help our customers see these defects earlier in the process, permitting faster action to mitigate the root cause and reducing the amount of product in jeopardy.”

Goodrich continued, “Using laser illumination we are able to clearly identify residue defects that typical white-light optics would miss. In addition to optimizing the wavelength of the illumination to enhance detection, we have specifically designed the mechanics of the system to accommodate the high warpage found in advanced packaging applications.”

Clearfind technology highlights organic residues on bumps and bond pads or at the bottoms of vias so that they are easy to detect. On metals, it eliminates the high-contrast graininess seen under conventional illumination, resulting in an obvious defect signal against a featureless background. This same graininess in conventional imaging can also cause false positives, which are especially costly at this stage of the process where the sunk cost of unnecessarily rejected good product is high. Finally, Clearfind technology readily detects shorts and opens in metal lines when inspected with an underlying organic layer. Rudolph believes these capabilities will significantly increase its customer’s ability to detect process and manufacturing related issues earlier in the process resulting in significant yield, which equates to millions of dollars in savings, especially for processes utilizing known-good die. Rudolph’s customers see this as a critical technology to improve quality for their customers in order to avoid the high costs of replacement and penalties.

For more information about the new Clearfind technology, please visit Rudolph at SEMICON West, booth 6543, in the North Hall.

clearfind-images-final

Applied Micro Circuits Corporation (NASDAQ:AMCC) today announced that it has adopted 7nm process technology from TSMC, a world-leading foundry, to enable AppliedMicro’s silicon products for cloud computing and networking applications.

“We are excited to extend our relationship with TSMC to ultimately bring cutting-edge technology to the cloud computing market,” said Paramesh Gopi, President and CEO of AppliedMicro. “We will work closely with TSMC to ensure our flagship silicon products benefit from their manufacturing excellence that is renowned throughout the industry. Together we will introduce technology to revolutionize the rapidly growing data-center market to deliver an unprecedented bundle of compute and connectivity performance, energy efficiency and bandwidth utilization at a low total cost of ownership.”

“We are pleased to be a part of AppliedMicro’s success,” said Dr. B.J. Woo, TSMC Vice President of Business Development. “TSMC’s advanced 7nm technology will empower AppliedMicro to deliver the critical performance needed in computing and connectivity applications.”

Recently introduced innovations from AppliedMicro include X-Gene 3 at ARM TechCon in November 2015, and single lambda, mixed signal 100G X-Weave PAM4 at the Optical Fiber Communications Conference in March 2016.  Both product functions were validated  with TSMC 16FF+ shuttle and are expected to sample to customers by early 2017.

The health of the semiconductor industry is increasingly tied to the health of the worldwide economy. Rarely can there be strong semiconductor market growth without at least “good” worldwide economic growth to support it. Consequently, IC Insights expects annual global semiconductor market growth rates to continue to closely track the performance of worldwide GDP growth (Figure 1).  In its upcoming Mid-Year Update to The McClean Report 2016 (to be released at the end of July), IC Insights forecasts 2016 global GDP growth of only 2.3%, which is below the 2.5% level that is considered to be the global recession threshold.

Figure 1

Figure 1

In many areas of the world, local economies have slowed.  China, which is the leading market for personal computers, digital TVs, smartphones, new commercial aircraft, and automobiles, is forecast to continue to lose economic momentum in 2016.  Its GDP is forecast to increase 6.6% this year, which continues a slide in that country’s annual GDP growth rate that started in 2010 when growth rates exceeded 10%.

IC Insights believes that the worldwide economy will be negatively impacted, at least over the next year or two, by the Brexit vote this past June.  At this point, since the U.K. is unlikely to officially be able to leave the European Union (EU) for a couple of years, the biggest negative effect on economic growth is the uncertainty of the entire situation.  Some of the uncertainty created by the vote includes:

•    Whether the U.K. will actually leave the EU.  Since the Brexit vote is not legally binding, and still needs to be approved by the U.K. government, there is uncertainty if its departure from the EU will actually happen.

•    Whether the U.K. will come apart itself.  There are rumblings about Scotland breaking away from being a part of the U.K. in order for it to remain as part of the EU.

•    What trade deals will be made by the U.K. if it does leave the EU?  As part of its exit from the EU, the U.K. will need to establish numerous new trade deals with the EU.  There is tremendous uncertainty regarding whether these deals would have a positive or negative effect on the U.K. economy.

•    Will other countries follow the U.K. and depart from the EU?  Anxiety persists over whether the EU will fall apart as other countries attempt their own exit.  Some countries mentioned as possibly following the U.K. out of the EU include the Netherlands (Nexit), France (Frexit), Italy, Austria, and Sweden (Swexit).

The other major “culprit” dragging down semiconductor industry growth this year is the very weak DRAM market.  At $45.0 billion, the DRAM market was the largest single product category in the semiconductor industry in 2015.  IC Insights forecasts that the DRAM market will register a 19% drop of $8.5 billion this year to $36.5 billion.  The DRAM market alone is forecast to shave three percentage points off of total semiconductor market growth this year. Semiconductor market growth excluding DRAM is forecast to be +2%.

Most of the DRAM market decline expected for this year is due to a rapid decline in DRAM pricing over the past 18 months.  For 2016, the average price for a DRAM device is forecast to drop to $2.55, a steep 16% decline as compared to 2015’s DRAM ASP of $3.03. Further trends and analysis relating to semiconductor market forecasts through 2020 will be covered in the 250-plus-page Mid-Year Update to the 2016 edition of The McClean Report.

By Paula Doe, SEMI

Emerging opportunities for advanced packaging solutions for heterogeneous integration include a lot more than logic, memory and sensors. There’s also the challenges of packaging integrated photonics, flexible electronics, and high-voltage, high-temperature wide-bandgap power devices. Speakers from the National Network for Manufacturing Innovation Institutes targeting these new growth markets will update the SEMICON West 2016 audience on their efforts to cut the time and cost of moving from R&D to volume production for U.S. companies by supporting development of key technologies, U.S.-based facilities for fabrication and packaging, and education of the workforce.

ap forum 2016-1

Integrating silicon with optics

The new American Institute for Manufacturing Integrated Photonics (AIM Photonics) is ramping up its program to spur development of U.S. technology and manufacturing capability for integrated photonics, for next-generation high performance computing, telecommunications, and sensors. In the packaging space, first steps will be a university-industry effort to develop passive fiber-to-silicon assembly technology and automated test equipment, with a manufacturing facility targeted for 2017.

“We’re focusing on packaging, assembly and test since it accounts for most of the cost of integrated photonics,” says CEO Michael Liehr, who will update on the plans to facilitate U.S. manufacturing in this emerging sector in the Packaging Photonics session at SEMICON West on July 12.

Attaching an optical fiber of 120µm diameter to a waveguide of only several thousand angstroms remains a major challenge, typically requiring active alignment.  Volume production will need a passive alignment solution, which will require some combination of major improvement in precision of current placement tools (such as with image recognition) with some way to make the coupling more fault tolerant ─ such as by using an interposer to bridge the gap. Tool makers will need standard package interfaces to make common, not custom equipment. The institute will also work on the packaging issues of integrating the laser with the waveguides and other optical features on silicon.

“Key elements are also missing for test,” Liehr notes. “The in-line part is missing. No one has put together a commercially available system that includes the prober, the optical detection, and the coupler needed.”  The institute is putting together a university and industry team to develop solutions, and then will equip a facility to do the test, assembly and packaging of these photonic integrated circuits.

AIM Photonics also targets a Process Design Kit (PDK) design kit by the end of the year for its multi-project photonic wafers run in its front-end fab. Besides data center and telecommunications applications of integrated photonics, AIM Photonics is working with companies on phased arrays and optical sensors for healthcare and defense applications. The organization is a public-private venture, funded by the U.S. Department of Defense, the States of New York, Massachusetts, California, Arizona, and university and industry members.

Integrating silicon die into flexible, conformable electronics systems

Another emerging “packaging” opportunity is integrating silicon intelligence into  flexible, stretchable products. “People have been talking for decades now about a purely printed solution, but printed transistors do not have enough mobility for the needed performance, and in a switching application will burn out in about a day” notes Jason Marsh, Director of Technology at NextFlex, the Manufacturing Innovation Institute for Flexible, Hybrid Electronics, who will talk about this effort at the SEMICON program on flexible packaging July 14. “But there is real demand for flexible, conformable products for medical wearable and implantable devices and for IoT edge devices.”  The collaborative program aims to develop the manufacturing technology to enable these products, by integrating silicon die into flexible, stretchable environments.

This will require the development of new processes for bridging directly from ~100µm-scale printed electronic circuits to 50µm-scale PCB artwork to much finer die-level bond-pad pitch, eliminating the usual intervening steps ─ of wirebond/flip chip, package, interposer, circuit board, connector ─ all at low temperature and with good signal integrity. Potential approaches could include flip chip with an anisotropic conductor connection, or alternatively, printing the traces directly on bigger pond pads. The institute aims to develop the basic building blocks of the technology and put together a U.S. supply chain that companies can then use to develop and manufacture their own products. NextFlex is building a facility in San Jose for the technology, which members can use to develop prototypes and build their pilot products.

Building this new manufacturing supply chain means re-thinking the traditional food chain of circuit board, packaging and assembly. “We may need to do things in different order, with die attach to the substrate before circuitization, and may need big arrays on big substrates, with new process tools to handle them,” suggests Marsh. “Package and assembly suppliers will need to understand more of the full end-to-end process, with assembly companies understanding packaging, and packaging companies understanding interposers.” The project aims to help bring these suppliers together, and also to help develop the necessary technical expertise in the workforce in the U.S. “The goal is to accelerate the speed of development from some 5-6 years to 1-2 years,” says Marsh.

The program is funded by $75 million from the U.S. government, and $96 million from the City of San Jose, and other corporate, academic, and government partners.

Building a U.S. ecosystem for wide bandgap power semiconductor manufacturing

PowerAmerica, the Next Generation Power Electronics Manufacturing Innovation Institute, aims to build the U.S. ecosystem for manufacturing wide bandgap power semiconductors, by supporting R&D, production facilities, and workforce development to accelerate the adoption of these smaller, lighter and more energy efficient power systems, and to make it easier for new and small U.S. companies to develop products.

“It’s about driving down cost and validating the reliability of SiC and GaN for demanding power electronics applications. The physics are clear. Wide bandgap semiconductors can offer very high-power densities and higher performance with a lower cost bill of materials. We are rapidly approaching the tipping point where market demand and production volume will bring the price of wide bandgap devices down to match silicon in $/Amp,” says John Muth, PowerAmerica’s deputy director, who will update on the effort in the power packaging program at SEMICON West on July 12.

Taking full advantage of the physical properties of wide bandgap semiconductors for high performance will require highly optimized packages that can handle high voltages while minimizing inductance and efficiently remove heat, with more reliable materials for interconnections, die attach, and baseplate/substrates, and better cooling solutions. One result of the packaging projects to date are the low inductance, high performance power modules recently announced by Wolfspeed.

PowerAmerica activities across the supply chain range from the 6-inch SiC foundry at X-Fab in Lubbock, Texas, now being used by five members, to products under development by end users across in transportation, renewable energy, motor drives, data centers, and the power grid, at members such as ABB, Agile Switch, Atom Power, John Deere, Navitas, Lockheed-Martin, and Toshiba.

The institute has recently also started to invite unsolicited proposals that solve a technical problem to help grow and strengthen the supply chain or to accelerate adoption of SiC or GaN into new products. All projects have 1:1 cost sharing, and require a clear path to market. Other efforts include aggressive demonstrations of wide bandgap semiconductor performance by universities, industry-led road mapping activities, and curriculum development at member universities, and tutorials and short courses to bring industry engineers quickly up to speed in GaN and SiC technology.

The five-year $146 million program is funded by $70 million from DOE and another $76 million from cost matching from its members and the state of North Carolina.

To learn more about SEMICON West 2016, visit the Schedule-at-a-Glance and learn about the eight forums.

Correction: The first draft of this article stated in error that Jason Marsh’s talk would take place on July 12. Jason Marsh will speak on flexible packaging at SEMICON West on July 14.

BY DR. PHIL GARROU, Contributing Editor

Earlier this year, a Taipei Times headline read “New packaging may spur TSMC growth” adding that despite its weak revenue growth guidance for this quarter, TSMC, might see stronger growth from next quarter thanks to its InFO (integrated fan out) packaging technology (see FIGURE).

The Times reports that InFO could help TSMC beat rival Samsung and win more A10 application processor orders from Apple, because the technology offers “…lower costs, higher speed and thinner form factor when compared to conventional flip chip packaging.” TSMC is preparing a complete InFO portfolio aimed at different package sizes and applications. In a conference call with investors in April, TSMC CEO C.C. Wei stated that they have almost completed equipment installation and expect to complete customer product qualification shortly. They plan to ship volume production shortly. Estimates are that the revenue contri- bution from InFO packaging could total US$300 million this year.

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I have previously reported that TSMC had purchased a facility in Longtan, Taiwan (from Qualcomm for $85MM) and was turning it into a facility devoted to the manufac- turing of integrated fan-out wafer-level packaging (InFO- WLP) technology.

Apple is expected to unveil its new iPhone in the second half of this year. Daiwa Capital Markets analysts estimates that Apple’s order split for A9 processors (last generation) was 45% for TSMC and 55% for Samsung, but projects TSMC could take more than 50% of the A10 processor business, due in part to the superior packaging technology now being offered by TSMC. Other smartphone chip vendors are reportedly looking at adopting TSMC InFO packaging technology in the near future.

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I have also previously reported that TSMC lost the chance for making Apple A3 processors to Samsung because it lacked the capability to package and test the chips.

YSIC (Yuanta Securities Investment Consulting) claims the InFO technology is at least 20 percent cheaper than flip chip packaging. YSIC notes that “… it is becoming more difficult to solely rely on front-end tech node migration to drive better performance and cost,” a statement that should be very familiar to readers of this column.

In 2014, I discussed TSMCs announced ambition of becoming a major player in full back-end packaging services with their plans to ramp IC packaging revenues to US $1 billion in 2015 and $2B in 2016 Based on this roadmap, TSMC would become the 3rd leading packaging company in Taiwan by 2016, trailing only ASE and SPIL.