Category Archives: Wafer Level Packaging

Amkor Technology announced on September 10th the opening of its new manufacturing and test plant at Longtan Science Park in Taiwan.

“Demand for Amkor’s advanced assembly and test services in Taiwan continues to increase. The opening of our fourth factory in Taiwan will allow us to keep pace with that demand,” said Steve Kelley, Amkor’s president and CEO. “Our new Longtan facility will focus on wafer probe and die processing, complementing the wafer-level and other advanced packaging capabilities of our other three factories.”

The new facility is Amkor’s first manufacturing plant in Longtan Science Park, which is well known for incubating Taiwanese high-tech businesses, including those in the semiconductor industry. The Science Park has strict environmental protection standards and only companies that are in full compliance are permitted. Amkor is also seeking ISO 15408 Common Site Criteria certification for the Longtan plant to ensure rigorous security protection during the manufacturing process.

“I am pleased to announce the opening of our new factory in Longtan, which enters its production phase this month,” said YongChul Park, Amkor’s executive vice president, Worldwide Manufacturing. “This expansion signifies Amkor’s ongoing commitment to invest globally and showcases our ability to leverage resources internationally.”

Below are photos taken during Monday’s opening ceremony at Amkor’s new Taiwan factory.

Japan is at the heart of the semiconductor industry as the era of artificial intelligence (AI) dawns. SEMICON Japan 2018 will highlight AI and SMART technologies in Japan’s industry-leading event. Registration is now open for SEMICON Japan, Japan’s largest global electronics supply chain event, December 12-14 at Tokyo Big Sight in Tokyo.

Themed “Dreams Start Here,” SEMICON Japan 2018 reflects the promise of AI, Internet of Things (IoT) and other SMART technologies that are shaping the future. Japan is positioned to help power a semiconductor industry expansion that is enabling this new path ahead, supplying one-third of the world’s semiconductor equipment and half of its chip IC materials.

According to VLSI Research, seven of the world’s top 15 semiconductor equipment manufacturers in 2017 are headquartered in Japan. In the semiconductor materials market, Japanese companies dominate silicon wafers, photoresists, sputtering targets, bonding wires, lead frames, mold compounds and more. For SEMICON Japan visitors, the event is the ideal platform for connecting with Japan’s leading suppliers.

The SMART Application Zone at SEMICON Japan will once again connect SMART industries with the semiconductor supply chain to foster collaboration across the electronics ecosystem.

SEMICON Japan Keynotes

SEMICON Japan opening keynotes will feature two young leaders of Japan’s information and communications technology (ICT) industry sharing their vision for the industry:

Motoi Ishibashi, CTO of Rhizomatiks, will discuss the latest virtual and mixed reality technologies. Rhizomatiks, a Japanese media art company that staged the Rio Olympic Games closing ceremony, will orchestrate the opening performance at SEMICON Japan 2018. The company is dedicated to creating large-scale commercial projects combining technology with the arts.

Toru Nishikawa, president and CEO at Preferred Networks, will explore computer requirements for enabling deep learning applications. Preferred Networks, a deep-learning research startup, is conducting collaborative research with technology giants including Toyota Motors, Fanuc, NVIDIA, Intel and Microsoft.

Registration

For more information and to register for SEMICON Japan, visit www.semiconjapan.org/en/. Registration for the opening keynotes and other programs will open October 1.

SEMI announced today the October 9 deadline for presenters to submit abstracts for the annual SEMI Advanced Semiconductor Manufacturing Conference(ASMC). ASMC, May 6-9, 2019, in Saratoga Springs, New York, will feature technical presentations of more than 90 peer-reviewed manuscripts covering critical process technologies and fab productivity.

ASMC 2019 will feature keynotes, a panel discussion, networking events, technical sessions on advanced semiconductor manufacturing, and tutorials. The conference will also feature a special student poster session to highlight student projects related to semiconductor manufacturing.

Selected speakers will present to IC manufacturers, equipment manufacturers, materials suppliers, chief technology officers, operations managers, process engineers, product managers and academia. All technical papers will be published by IEEE, and authors also may receive an invitation to publish their papers in a special section for ASMC 2019 to be featured in IEEE Transactions on Semiconductor Manufacturing. Technical abstracts are due October 9, 2018, and can be submitted here. 

ASMC 2019 will cover the following topics:

  • Advanced Equipment Processes and Materials
  • Advanced Metrology
  • Advanced Equipment Processes and Materials
  • Advanced Patterning / Design for Manufacturability
  • Advanced Process Control
  • Contamination Free Manufacturing
  • Big Data Management and Mining
  • Defect Inspection and Reduction
  • Discrete and Power Devices
  • Enabling Technologies and Innovative Devices
  • Equipment Reliability and Productivity Enhancements
  • Factory Automation
  • The Fabless Experience
  • Green Factory
  • Industrial Engineering
  • Lean Manufacturing
  • MOL and Junction Interfaces
  • Smart Manufacturing
  • Yield Enhancement/Learning
  • Yield Methodologies
  • 3D Packaging and Through Silicon Via

ASMC, in its 30th year, continues to fill a critical need for the industry, providing a venue for professionals to network, learn and share knowledge about semiconductor manufacturing best practices.

Details on how to upload abstracts can be found here. To learn more about the conference and the selection process, please contact Margaret Kindling at [email protected] or call 1.202.393.5552.   

Papers co-authored by device manufacturers, equipment or materials suppliers, and/or academic institutions that demonstrate innovative, practical solutions for advancing semiconductor manufacturing are highly encouraged.

ASMC is organized by SEMI Americas to connect more than 2,000 member companies and 1.3 million professionals worldwide to advance the technology and business of electronics manufacturing

SEMI and TechSearch International today announced a new edition of the Worldwide OSAT Manufacturing Sites Database – the only outsourced semiconductor assembly and testing (OSAT) supplier database available in the market. The report, an essential business tool for anyone interested in device packaging, tracks facilities that provide packaging and testing services to the semiconductor industry.

The new edition includes more than 80 updates spanning packaging technology offerings, product specialization, new facility announcements, as well as ownership/shareholder updates, bringing the total number of facilities tracked in the report to 320.

Combining the expertise of SEMI and TechSearch International, the Worldwide OSAT Manufacturing Sites Database update also features a new section listing the revenues of the world’s top 20 OSAT companies in 2016 and 2017 and captures changes in technology capabilities and service offerings at various facilities.

The Worldwide OSAT Manufacturing Sites Database is a comprehensive report offering insights into global OSAT facilities in China, Taiwan, Korea, Japan, Southeast Asia, Europe, and the Americas. The report highlights new and emerging packaging offerings by manufacturing location and by companies. Specific details tracked include:

  • Plant site location, technology, and capability: Packaging, Test, and other product specializations, such as sensor, automotive and power devices are highlighted.
  • Packaging assembly service offered: BGA, specific leadframe type such as QFP, QFN, SO, flip chip bumping, WLP, Modules/SIP, and sensors.
  • New manufacturing sites announced, planned or under construction.

Tracking advances in packaging technology, which directly affects chip performance, reliability and cost, requires understanding company offerings by location. Key features of the updated report include:

  • More than 120 companies and 300 facilities
  • Over 90 facilities offering leadframe CSP
  • Over 25 bumping facilities, including 20 with 300mm wafer bumping capacity
  • More than 45 facilities offering WLCSP technology
  • New facilities offering FOWLP and FOPLP
  • 92 facilities in China, 89 in Taiwan, 39 in Southeast Asia

The database findings are based on information gathered and compiled from over 120 companies globally. All information in the Worldwide OSAT Manufacturing Sites Database was gathered by SEMI and TechSearch International. Report licenses are available for single-user and multi-users. SEMI members save 16 percent or more depending on the type of license.

For more information about the Worldwide OSAT Manufacturing Sites Database and to order a sample copy, please click here. For pricing and ordering information, please click here.

By Richard Allen

The arrival of Fan-Out Panel Level Packaging (FO-PLP) appears to be at a perfect time: This technology will leverage processes developed for Three Dimensional Stacked Integrated Circuits (3DS-IC) as well as panel processing technologies developed for industries such as solar panels and large-screen TVs.  In this combination, FO-PLP promised the improved performance of 3DS-IC, without the expense. There was just one problem…

That problem is the size of the panels to be processed. As different companies developed FO-PLP processes, they chose panels sized to meet certain technical or business goals, or chose a size based on familiarity. So, processes were being developed for more than ten sizes, each of which had one or more companies championing them.

For people in the wider semiconductor industry, the development of many processes, each with a unique panel size brought a feeling of déjà vu, reminding them of the 1970s, when each device manufacturer created their own specification for wafer size, forcing them to manufacture their own wafer processing equipment since no external manufacturer was willing to produce tools usable only by a single customer.

SEMI responded by developing an industry consensus silicon wafer standard – which described basic parameters, including diameter and thickness – to resolve the issue. Almost overnight the landscape changed, and new tool manufacturers sprung up, enabling the incredible growth that has persisted over more than 40 years.

Recently, Cristina Chu (TEL NEXX) presented the state of FO-PLP to the North America Chapter of the SEMI Three-Dimensional Packaging and Integration (3DP&I) Technical Committee, suggesting that the Committee develop a single standard dimension that would enable the technology to move into high-volume manufacturing.

The Committee began by surveying the industry to determine the interest level in such a standard as well as its contents.  A key finding came in response to the question “Would you support a standardized panel size?” Overwhelmingly, over 70 percent of the respondents supporting the idea for the standard, with less than 2 percent opposed. The survey also asked if other parameters should be standardized and, if so, which parameters. Majority responses pointed to edge profile, flatness, and warp, prompting the 3DP&I Committee to immediately form the FO-PLP Panel Task Force (TF) to develop such a standard. Chu and Richard Allen (NIST) agreed to chair the TF and respondents to the survey were asked to participate as TF members.

The TF initially decided to follow the model of SEMI M1, Specification for Polished Single Crystal Silicon Wafers, and write the document as a purchase specification. The purchase specification would indicate a limited number of mandatory parameters, identified as those that serve as bottlenecks to the development of a FO-PLP ecosystem. Parameters that were not perceived as bottlenecks but might be useful for implementing a FO-PLP process would be included as optional.

Working under the SEMI Standards umbrella allowed the TF to take advantage of work done in the development of other standards, without having to recreate it from scratch. In particular, Flatness and Shape were repurposed from SEMI M1, ensuring consistent definitions of these parameters.

The TF could not come to consensus on how the other parameters should be categorized, so the decision was made to move the ordering table to a new Appendix as optional.

The TF will be balloting its first specification for panel substrate in the upcoming cycle, which opens September 5, 2018 (Cycle 7). The voting is open to all industry experts. Based on the feedback, the task force will continue to refine and otherwise improve the specification by incorporating other parameters that are critical to making FO-PLP a reality.

SEMI Standards development activities take place throughout the year in all major manufacturing regions. To get involved, join the SEMI International Standards Program at: www.semi.org/standardsmembership.

For more information regarding FO-PLP Panel Task Force activities, please contact Laura Nguyen at [email protected].

Richard Allen is a physicist in the Nanoscale Metrology Group in the Engineering Physics Division of the Physical Measurement Laboratory (PML) at the National Institute of Standards and Technology (NIST). 

Originally published on the SEMI blog.

Brewer Science, Inc. today from SEMICON Taiwan introduced the latest additions to its industry-leading BrewerBOND® family of temporary bonding materials, as well as the first product in its new BrewerBUILD™ line of thin spin-on packaging materials. BrewerBUILD delivers an industry-first solution to address manufacturers’ evolving wafer-level packaging challenges.

The BrewerBOND T1100 and BrewerBOND C1300 series combine to create Brewer Science’s first complete, dual-layer system for temporary bonding and debonding of product wafers. The new system was developed for power, memory and chip-first fan-out devices – all of which have stringent requirements with respect to temperature, power and performance. The system can be used with either mechanical or laser debonding methods.

The BrewerBUILD material was specifically created for redistribution-layer (RDL)-first fan-out wafer-level packaging (FOWLP). Developed to meet the needs of chipmakers looking to transition from chip-first FOWLP but not yet ready to tackle 2.5D/3D packaging, the single-layer material is compatible with both wafer- and panel-level temporary bonding/debonding processes.

“As industry requirements advance, Brewer Science continues to push forward the state of the art in our materials offerings,” said Kim Arnold, executive director, Advanced Packaging Business Unit, Brewer Science Inc. “Through close collaboration with our customers, we are driving the technology forward, leveraging our R&D braintrust to create unique solutions like these that are designed to meet customers’ needs – current and future.”

The Micron Foundation announced that it will commit $1 million to higher education institutions in Virginia as it invests in the next generation of technicians, scientists and engineers with a focus on women and underrepresented minorities in these fields. The investment will provide grants and funding at select community colleges and universities for several types of programs, organizations and individuals that inspire and enable future innovators.

“Today we are proud to expand our commitment with education partners across Virginia, which share our focus on developing a strong, vibrant and talented workforce,” said Micron Foundation Executive Director Dee Mooney. “These efforts reflect our company’s focus on investing in students and embracing diversity, as well as our long-term commitment to our Manassas facility and its team members. We look forward to working with community and education leaders to identify and support programs that will make a difference for decades to come.”

The $1 million fund will support programs in the area of cleanroom and nanotechnology labs, unmanned and autonomous automotive systems, robotics, big data, embedded systems and networking applications. Faculty members, program directors and student groups from universities and community colleges in the Commonwealth of Virginia will be eligible. With a focus on women and underrepresented minorities, programs that support low income and first-time college student programs will also receive special consideration.

Global semiconductor industry revenue grew 4.4 percent, quarter over quarter, in the second quarter of 2018, reaching a record $120.8 billion. Semiconductor growth occurred in all application markets and world regions, according to IHS Markit (Nasdaq: INFO).

“The explosive growth in enterprise and storage drove the market to new heights in the second quarter,” said Ron Ellwanger, senior analyst and component landscape tool manager, IHS Markit. “This growth contributed to record application revenue in data processing and wired communication markets as well as in the microcomponent and memory categories.”

Due to the ongoing growth in the enterprise and storage markets, sequential microcomponent sales grew 6.5 percent in the second quarter, while memory semiconductor revenue increased 6.4 percent. “Broadcom Limited experienced exceptional growth in its wired communication division, due to increased cloud and data-center demand,” Ellwanger said.

Memory component revenue continued to rise in the second quarter, compared to the previous quarter, reaching $42.0 billion dollars. “This is the ninth consecutive quarter of rising revenue from memory components, and growth in the second quarter of 2018 was driven by higher density in enterprise and storage,” Ellwanger said. “This latest uptick comes at a time of softening prices for NAND flash memory. However, more attractive pricing for NAND memory is pushing SSD demand and revenue higher.”

Semiconductor market share

Samsung Electronics continued to lead the overall semiconductor industry in the second quarter with 15.9 percent of the market, followed by Intel at 13.9 percent and SK Hynix at 7.9 percent. Quarter-over-quarter market shares were relatively flat, with no change in the top-three ranking. SK Hynix achieved the highest growth rate and record quarterly sales among the top three companies, recording 16.4 percent growth in the second quarter.

MRSI Systems (Mycronic Group), is expanding its high speed MRSI-HVM3 die bonder platform with the launch of the MRSI-HVM3P to offer configurations for active optical cable (AOC), gold-box packaging, and other applications in addition to chip-on-carrier (CoC).

This expansion is in response to our customer’s request to take advantage of the field-proven performance of the flexible high speed MRSI-HVM3 platform, for their other essential packaging applications in photonics manufacturing which are high volume and high mix by nature.

The new MRSI-HVM3P is the first major extension to the HVM3 family, equipped with inline conveyor for single fixture or multiple cassette inputs that can automatically transport large forms of carriers of the dies. This configuration is targeted at AOC or similar die-to-printed circuit board (PCB) applications, gold-box packaging, and CoC in fixture. The processes include eutectic, epoxy stamping, UV epoxy dispensing, and in-situ UV curing.

“With these extensions to our successful HVM3 platform, MRSI Systems is now able to offer flexible high volume die bonding solutions, not just for CoC, but also for PCB and box levels of packaging to our customers in photonics, sensors and other advanced technology fields,” said Dr. Yi Qian, Vice President of Product Management of MRSI Systems. “This is another demonstration of MRSI’s commitment to provide critical solutions promptly in response to our customers’ needs,” concluded Mr. Michael Chalsen, President of MRSI Systems.

Both MRSI-HVM3 and MRSI-HVM3P now carry the following options inherited from our long proven MRSI-M3 family:  localized heating, flip-chip bonding, and co-planarity bonding. These options are increasingly critical for new applications such as 400G transceivers and silicon photonics.

The MRSI-HVM3 product family delivers industry-leading speed, future-proof high precision (<3mm), and superior flexibility for true multi-process, multi-chip, high-volume production.

The launch of the MRSI-HVM3P builds on the success of our first configuration launched last year, the MRSI-HVM3 for CoC, Chip-on-Submount (CoS), and Chip-on-Baseplate (CoB) assembly using eutectic and/or epoxy stamping die bonding, which has proved to be the best-in-class die bonder with the leading speed, zero-time tool change between dies, and <3mm accuracy. The superior performance was enabled by dual head, dual stage, integrated “on-the-fly” tool changer, ultrafast eutectic stage, and multi-levels of parallel processing optimizations (see product launch press release August 14, 2017).

MRSI Systems is exhibiting at China International Optoelectronic Expo (CIOE) with our partner CYCAD Century Science and Technology (Booth #1C66) in Shenzhen, September 5-8, 2018 and ECOC (Booth #577) in Rome, Italy, September 24-26, 2018.

SEMI today announced that all legal requirements have been met for the ESD (Electronic Systems Design) Alliance to become a SEMI Strategic Association Partner.

Full integration of the Redwood City, California-based association representing the semiconductor design ecosystem is expected to be complete by the end of 2018. The integration will extend ESD Alliance’s global reach in the electronics manufacturing supply chain and strengthen engagement and collaboration between the semiconductor design and manufacturing communities worldwide.

As a SEMI Strategic Association Partner, the ESD Alliance will retain its own governance and continue its mission to represent and support companies in the semiconductor design ecosystem.

The ESD Alliance will lead its strategic goals and objectives as part of SEMI, leveraging SEMI’s robust global resources including seven regional offices, expositions and conferences, technology communities and activities in areas such as advocacy, international standards, environment, health and safety (EH&S) and market statistics.

With the integration, SEMI adds the design segment to its electronics manufacturing supply chain scope, connecting the full ecosystem. The integration is a key step in streamlining SEMI members’ collaboration and connection with the electronic system design, IP and fabless communities. The Strategic Association Partnership will also enhance collaboration and innovation across the collective SEMI membership as ESD Alliance members bring key capabilities to SEMI’s vertical application platforms such as Smart Transportation, Smart Manufacturing and Smart Data as well as applications including AI and Machine Learning.

“The addition of ESD Alliance as a SEMI Strategic Association Partner is a milestone in our mission to drive new efficiencies across the full global electronics design and manufacturing supply chain for greater collaboration and innovation,” said Ajit Manocha, president and CEO of SEMI. “This partnership provides opportunities for all SEMI members for accelerated growth and new business opportunities in end-market applications. We welcome ESD Alliance members to the SEMI family.”

“Our members are excited about becoming part of SEMI’s broad community that spans the electronics manufacturing supply chain,” said Bob Smith, executive director of the ESD Alliance. “Global collaboration between design and manufacturing is a requirement for success with today’s complex electronic products. Our new role at SEMI will help develop and strengthen the connections between the design and manufacturing communities.”

All ESD Alliance member companies, including global leaders ARM, Cadence, Mentor, a Siemens business, and Synopsys, will join SEMI’s global membership of more than 2,000 companies while retaining ESD Alliance’s distinct self-governed community within SEMI.