Category Archives: Wafer Level Packaging

For the first time, scientists at IBM Research have demonstrated reliably storing 3 bits of data per cell using a relatively new memory technology known as phase-change memory (PCM).

The current memory landscape spans from venerable DRAM to hard disk drives to ubiquitous flash. But in the last several years PCM has attracted the industry’s attention as a potential universal memory technology based on its combination of read/write speed, endurance, non-volatility and density. For example, PCM doesn’t lose data when powered off, unlike DRAM, and the technology can endure at least 10 million write cycles, compared to an average flash USB stick, which tops out at 3,000 write cycles.

This research breakthrough provides fast and easy storage to capture the exponential growth of data from mobile devices and the Internet of Things.

For the first time, scientists at IBM Research have demonstrated reliably storing 3 bits of data per cell using a relatively new memory technology known as phase-change memory (PCM). This research breakthrough provides fast and easy storage to capture the exponential growth of data from mobile devices and the Internet of Things. In this photo, IBM scientist , Nikolaos Papandreou holds the PCM chip under a magnifying lens in his lab. (Credit: IBM Research)

For the first time, scientists at IBM Research have demonstrated reliably storing 3 bits of data per cell using a relatively new memory technology known as phase-change memory (PCM). This research breakthrough provides fast and easy storage to capture the exponential growth of data from mobile devices and the Internet of Things. In this photo, IBM scientist , Nikolaos Papandreou holds the PCM chip under a magnifying lens in his lab. (Credit: IBM Research)

Applications 

IBM scientists envision standalone PCM as well as hybrid applications, which combine PCM and flash storage together, with PCM as an extremely fast cache. For example, a mobile phone’s operating system could be stored in PCM, enabling the phone to launch in a few seconds. In the enterprise space, entire databases could be stored in PCM for blazing fast query processing for time-critical online applications, such as financial transactions.

Machine learning algorithms using large datasets will also see a speed boost by reducing the latency overhead when reading the data between iterations.

How PCM Works 

PCM materials exhibit two stable states, the amorphous (without a clearly defined structure) and crystalline (with structure) phases, of low and high electrical conductivity, respectively.

For the first time, scientists at IBM Research have demonstrated reliably storing 3 bits of data per cell using a relatively new memory technology known as phase-change memory (PCM). In this photo, the experimental multi-bit PCM chip used by IBM scientists is connected to a standard integrated circuit board. The chip consists of a 2 × 2 Mcell array with a 4- bank interleaved architecture. The memory array size is 2 × 1000 μm × 800 μm. The PCM cells are based on doped-chalcogenide alloy and were integrated into the prototype chip serving as a characterization vehicle in 90nm CMOS baseline technology. (Credit: IBM Research)

For the first time, scientists at IBM Research have demonstrated reliably storing 3 bits of data per cell using a relatively new memory technology known as phase-change memory (PCM). In this photo, the experimental multi-bit PCM chip used by IBM scientists is connected to a standard integrated circuit board. The chip consists of a 2 × 2 Mcell array with a 4- bank interleaved architecture. The memory array size is 2 × 1000 μm × 800 μm. The PCM cells are based on doped-chalcogenide alloy and were integrated into the prototype chip serving as a characterization vehicle in 90nm CMOS baseline technology. (Credit: IBM Research)

To store a ‘0’ or a ‘1’, known as bits, on a PCM cell, a high or medium electrical current is applied to the material. A ‘0’ can be programmed to be written in the amorphous phase or a ‘1’ in the crystalline phase, or vice versa. Then to read the bit back, a low voltage is applied. This is how re-writable Blue-ray Discs* store videos.

Previously scientists at IBM and other institutes have successfully demonstrated the ability to store 1 bit per cell in PCM, but today at the IEEE International Memory Workshop in Paris, IBM scientists are presenting, for the first time, successfully storing 3 bits per cell in a 64k-cell array at elevated temperatures and after 1 million endurance cycles.

“Phase change memory is the first instantiation of a universal memory with properties of both DRAM and flash, thus answering one of the grand challenges of our industry,” said Dr. Haris Pozidis, an author of the paper and the manager of non-volatile memory research at IBM Research – Zurich. “Reaching 3 bits per cell is a significant milestone because at this density the cost of PCM will be significantly less than DRAM and closer to flash.”

To achieve multi-bit storage IBM scientists have developed two innovative enabling technologies: a set of drift-immune cell-state metrics and drift-tolerant coding and detection schemes.

More specifically, the new cell-state metrics measure a physical property of the PCM cell that remains stable over time, and are thus insensitive to drift, which affects the stability of the cell’s electrical conductivity with time. To provide additional robustness of the stored data in a cell over ambient temperature fluctuations a novel coding and detection scheme is employed. This scheme adaptively modifies the level thresholds that are used to detect the cell’s stored data so that they follow variations due to temperature change. As a result, the cell state can be read reliably over long time periods after the memory is programmed, thus offering non-volatility.

“Combined these advancements address the key challenges of multi-bit PCM, including drift, variability, temperature sensitivity and endurance cycling,” said Dr. Evangelos Eleftheriou, IBM Fellow.

The experimental multi-bit PCM chip used by IBM scientists is connected to a standard integrated circuit board. The chip consists of a 2 × 2 Mcell array with a 4- bank interleaved architecture. The memory array size is 2 × 1000 μm × 800 μm. The PCM cells are based on doped-chalcogenide alloy and were integrated into the prototype chip serving as a characterization vehicle in 90 nm CMOS baseline technology.

OpenPOWER 

At the 2016 OpenPOWER Summit in San Jose, CA, last month, IBM scientists demonstrated, for the first time, phase-change memory attached to POWER8-based servers (made by IBM and TYAN® Computer Corp.) via the CAPI (Coherent Accelerator Processor Interface) protocol. This technology leverages the low latency and small access granularity of PCM, the efficiency of the OpenPOWER architecture and the CAPI protocol. In the demonstration the scientists measured very low and consistent latency for 128-byte read/writes between the PCM chips and the POWER8 processor.

For more information on today’s announcement watch this video: https://youtu.be/q3dIw3uAyE8. Continue the conversation at @IBMResearch #3bitPCM.

IC Insights will release its May Update to the 2016 McClean Report later this month.  This Update includes a discussion of the 1Q16 semiconductor industry market results, an update of the capital spending forecast by company, a review of the IC market by electronic system type, and a look at the top-25 1Q16 semiconductor suppliers (the top 20 1Q16 semiconductor suppliers are covered in this research bulletin).

The top-20 worldwide semiconductor (IC and O S D—optoelectronic, sensor, and discrete) sales ranking for 1Q16 is shown in Figure 1.  It includes eight suppliers headquartered in the U.S., three in Japan, three in Taiwan, three in Europe, two in South Korea, and one in Singapore, a relatively broad representation of geographic regions.

The top-20 ranking includes three pure-play foundries (TSMC, GlobalFoundries, and UMC) and six fabless companies. If the three pure-play foundries were excluded from the top-20 ranking, U.S.-based IDM ON Semiconductor ($817 million), China-based fabless supplier HiSilicon ($810 million), and Japan-based IDM Sharp ($800 million) would have been ranked in the 18th, 19th, and 20th positions, respectively.

IC Insights includes foundries in the top-20 semiconductor supplier ranking since it has always viewed the ranking as a top supplier list, not a marketshare ranking, and realizes that in some cases the semiconductor sales are double counted.  With many of our clients being vendors to the semiconductor industry (supplying equipment, chemicals, gases, etc.), excluding large IC manufacturers like the foundries would leave significant “holes” in the list of top semiconductor suppliers.  As shown in the listing, the foundries and fabless companies are identified.  In the April Update to The McClean Report, marketshare rankings of IC suppliers by product type were presented and foundries were excluded from these listings.

Overall, the top-20 list shown in Figure 1 is provided as a guideline to identify which companies are the leading semiconductor suppliers, whether they are IDMs, fabless companies, or foundries.

Figure 1

Figure 1

In total, the top-20 semiconductor companies’ sales declined by 6% in 1Q16/1Q15, one point less than the total worldwide semiconductor industry decline of 7%.  Although, in total, the top-20 1Q16 semiconductor companies registered a moderate 6% drop, there were seven companies that displayed a double-digit 1Q16/1Q15 decline and three that registered a ≥25% fall (with memory giants Micron and SK Hynix posting the worst results).  Half of the top-20 companies had sales of at least $2.0 billion in 1Q16.  As shown, it took $832 million in quarterly sales just to make it into the 1Q16 top-20 semiconductor supplier list.

There was one new entrant into the top-20 ranking in 1Q16—U.S.-based fabless supplier AMD.  AMD had a particularly rough 1Q16 and saw its sales drop 19% year-over-year to $832 million, which was about half the $1,589 million in sales the company logged just over two years ago in 4Q13.  Although AMD did not have a good 1Q16, Japan-based Sharp, the only company that fell from the top-20 ranking, faired even worse with its 1Q16/1Q15 sales plunging by 30%!

In order to allow for more useful year-over-year comparisons, acquired/merged semiconductor company sales results were combined for both 1Q15 and 1Q16, regardless of when the acquisition or merger occurred.  For example, although Intel’s acquisition of Altera did not close until late December of 2015, Altera’s 1Q15 sales ($435 million) were added to Intel’s 1Q15 sales ($11,632 million) to come up with the $12,067 million shown in Figure 1 for Intel’s 1Q15 sales.  The same method was used to calculate the 1Q15 sales for Broadcom Ltd. (Avago/Broadcom), NXP (NXP/Freescale), and GlobalFoundries (GlobalFoundries/IBM).

Apple is an anomaly in the top-20 ranking with regards to major semiconductor suppliers. The company designs and uses its processors only in its own products—there are no sales of the company’s MPUs to other system makers. Apple’s custom ARM-based SoC processors had a “sales value” of $1,390 million in 1Q16, up 10% from $1,260 million in 1Q15.  Apple’s MPUs have been used in 13 iPhone handset designs since 2007 and a dozen iPad tablet models since 2010 as well as in iPod portable media players, smartwatches, and Apple TV units.  Apple’s custom processors—such as the 64-bit A9 used in iPhone 6s and 6s Plus handsets introduced in September 2015 and the new iPhone 6SE launched in March 2016—are made by pure-play foundry TSMC and IDM foundry Samsung.

Intel remained firmly in control of the number one spot in 1Q16.  In fact, it increased its lead over Samsung’s semiconductor sales from 29% in 1Q15 to 40% in 1Q16.  The biggest moves in the ranking were made by the new Broadcom Ltd. (Avago/Broadcom) and Nvidia, each of which jumped up three positions in 1Q16 as compared to 1Q15.

As would be expected, given the possible acquisitions and mergers that could/will occur this year (e.g., Microchip/Atmel), as well as any new ones that may develop, the top-20 semiconductor ranking is likely to undergo a significant amount of upheaval over the next few years as the semiconductor industry continues along its path to maturity.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that it has received multiple orders for its GEMINI FB XT automated fusion wafer bonders from multiple leading device manufacturers. The GEMINI FB XT offers wafer-to-wafer alignment accuracy, customizable pre- and post-processing configurations with faster handling and improved process flows that increase throughput by up to 50 percent compared to the previous-generation platform, as well as integrated metrology to maximize yields and productivity in high-volume manufacturing (HVM). These latest orders for the GEMINI FB XT system will support several leading-edge HVM applications, including 3D stacked image sensors, memory stacking, and die partitioning for next-generation 3D system-on-chip (SoC) devices.

GEMINI FB XT Automated Production Fusion Bonding System

GEMINI FB XT Automated Production Fusion Bonding System

Vertical stacking of devices has become an increasingly viable approach to driving continuous improvements in device density and performance without the need for increasingly costly and complex lithography processing. Wafer-to-wafer bonding is an essential process step to enable 3D stacked devices. However, tight alignment and overlay accuracy between the wafers is required to achieve good electrical contact between the interconnected devices on the bonded wafers, as well as to minimize the interconnect area at the bond interface so that more space can be made available on the wafer for producing devices.

“These latest orders for our GEMINI FB XT system from multiple leading manufacturers reflect the fact that our most advanced fusion bonding platform meets critical production requirements for a variety of 3D chip stacking applications, and further demonstrates our leadership in fusion bonding,” stated Hermann Waltl, executive sales and customer support director at EV Group. “Unparalleled wafer-to-wafer alignment accuracy supports IC manufacturers’ efforts to move wafer stacking upstream from back-end-of-line (BEOL) and mid-end-of-line (MEOL) applications to front-end-of-line (FEOL) processing where they can integrate more functionality into their product at the wafer level and further drive down manufacturing costs. The GEMINI FB XT has proven to fulfill the most stringent compatibility requirements and standards of front-end fabs. It also combines the capabilities necessary to bring new bonding technologies, like hybrid bonding for CMOS image sensors, into high-volume production. It is a true testament to our Triple-i philosophy of invent, innovate and implement.”

Leveraging EVG’s XT Frame platform and an equipment front-end module (EFEM), the GEMINI FB XT automated production fusion bonding system is optimized for ultra-high throughput and productivity. It incorporates EVG’s proprietary SmartView NT face-to-face aligner to achieve wafer-to-wafer overlay alignment accuracy below 200 nm (3 sigma), which leads the industry in performance and is essential to enabling 3D integration. In addition, the system can accommodate up to six pre-and post-processing modules for surface preparation, conditioning and metrology steps―such as wafer cleaning, plasma activation, alignment verification, debonding (allowing pre-bonded wafers to be separated automatically and re-processed if necessary) and thermo-compression bonding. This enables the GEMINI FB XT to support fully automated and integrated wafer loading, alignment, bonding and unloading of bonded wafers in HVM environments.

STATS ChipPAC Pte. Ltd., a provider of advanced semiconductor packaging and test services, announced today that it has shipped over one billion fan-out wafer level packages (FOWLP), also known in the industry as embedded Wafer Level Ball Grid Array (eWLB). FOWLP or eWLB is an advanced packaging technology platform that provides ultra-high density interconnection, superior electrical performance and the ability to integrate multiple heterogeneous dies in a cost effective, low-profile semiconductor package.

As the industry was beginning to learn about eWLB in 2008, STATS ChipPAC immediately recognized the significant potential, value and scalability of eWLB and designated it as a key technology for the company.  Within a year, STATS ChipPAC had ramped eWLB to high volume production and was driving a number of technology and manufacturing initiatives in this new packaging approach. STATS ChipPAC has led the industry in eWLB manufacturing capabilities, capacity and technology innovations, particularly in 2.5D and 3D package designs.  STATS ChipPAC became the first company in the semiconductor industry to implement significantly larger than 300mm eWLB wafer manufacturing capabilities and has a strong portfolio of innovative eWLB packages, including small die, large die, multi-die, multi-layer, Package-on-Package (PoP) and System-in-Package (SiP) architectures.

“We differentiated STATS ChipPAC by our unwavering commitment to eWLB technology over the years, beginning with our vision of how this scalable packaging platform can be leveraged to drive performance and size advantages for our customers’ applications.   Over the years we have made significant capital investments and process enhancements to fulfill our vision and raise the bar on manufacturing efficiency and productivity in the industry, adding further value for our customers,” said Dr. Han Byung Joon, President and Chief Executive Officer, STATS ChipPAC. “Although we have achieved multiple milestones with eWLB through the years, shipping over one billion eWLB packages is a testament to the ever expanding customer adoption in the industry and success which we knew was possible with this game changing technology.”

The exceptional success of eWLB in the mobile market, particularly in baseband processors, connectivity devices, Codec devices, RF transceivers and power management integrated circuits (PMICs), is a reflection of the ongoing pressure semiconductor companies face in cost effectively achieving higher input/output (I/O), higher bandwidths and lower power consumption in the smallest possible form factor. STATS ChipPAC has driven a number of eWLB technology achievements such as dense vertical interconnections as high as 500 – 1,000 I/O, very fine line width and spacing down to 2um/2um and ultra thin package profiles below 0.3mm (including solderball) for single packages and below 0.6mm for a stacked PoP with proven warpage control.

With the ability to partition silicon and embed passive devices and vertical interconnects (known as eBar) into a design, eWLB is a powerful integration technology for 2.5D and 3D PoP or SiP solutions for a wide range of new and emerging applications. The compelling performance, size and cost advantages of eWLB are accelerating the adoption of this advanced technology into new markets such as the Internet of Things (IoT) and wearable electronics, Micro-Electro-Mechanical Systems (MEMS) and automotive applications. Examples of new eWLB applications are Advanced Driver Assistance Systems (ADAS) in automobiles and bio-processors in the wearables market.

Advanced Semiconductor Engineering, Inc. and Deca Technologies, a subsidiary of Cypress Semiconductor Corp., announced the signing of an agreement whereby ASE will invest $60 million in Deca and will license Deca’s M-Series Fan-out Wafer-Level Packaging (FOWLP) technologies and processes. As part of the agreement, ASE and Deca will jointly develop the M-Series fan-out manufacturing process and will expand production of chip-scale packages using this technology. The technology is required for the reduced size and power consumption needed for portable Internet of Things (IoT) applications and smartphones. Deca’s version of it uses autoline technology developed by SunPower to decrease cost and manufacturing cycle time.

“At Cypress we have experienced the efficiency of Deca’s M-Series technology with our own chips and brought its benefits to our customers,” said T.J. Rodgers, Chairman of the Board at Deca Technologies and president and CEO of Cypress Semiconductor Corp. “With this investment from ASE, Deca now has strong validation of M-Series as a technology that will bring fan-out wafer-level packaging to mass production. This deal is a significant proof point for Deca and for Cypress’s ongoing strategy of investing in startups as part of our Emerging Technologies Division.”

The ability to put more functionality on ever-shrinking semiconductors, also known as Moore’s Law, is causing an unintended consequence in the semiconductor packaging industry, where chips using advanced silicon technologies are so small that all of the input and output balls cannot fit on the surface of the chip using conventional wafer-level chip-scale packaging (WLCSP) technology. Deca’s M-Series addresses this challenge with a FOWLP approach, where very small silicon chips are embedded into a larger plastic chip, and the CSP balls are redistributed onto both the native silicon chip and the expanded plastic chip. M-Series enables industry-leading manufacturability for FOWLP using Deca’s proprietary Adaptive Patterning™ technology, which tracks the alignment of each silicon IC in the redistributed plastic package. ASE has found M-Series to be a viable and effective high-volume manufacturing FOWLP solution.

“With the increasing demands to improve performance and reduce package size from the smartphone market and the emerging demand for IoT, the industry has been looking for a FOWLP technology with true manufacturability,” said Chris Seams, CEO of Deca Technologies. “Deca is excited to have ASE select our patented M-Series technology to meet this challenge. By leveraging ASE’s large customer base and world-class manufacturing expertise, we can bring FOWLP processing to high-volume reality.”

Deca’s fan-out wafer level packaging technologies will add to ASE’s advanced packaging portfolio, providing customers with a more diverse selection of offerings that are best suited for their IC designs. “Today’s announcement is a major milestone in ASE’s FOWLP roadmap and demonstrates ASE’s continued pursuit in industry leadership to build a complete manufacturing eco-system with key partners,” said Dr. Tien Wu, COO, ASE Group. “The incorporating of Deca’s M-Series and Adaptive Patterning technologies and manufacturing process will enable ASE to offer customers a proven FOWLP solution that is cost-effective due to the efficiency of large-panel-based processing.”

The proposed investment by ASE is subject to the various regulatory approvals or consents including but not limited to the approvals of the Taiwan government.

The Semiconductor Industry Association (SIA) this week announced worldwide sales of semiconductors reached $26.1 billion for the month of March 2016, a slight increase of 0.3 percent compared to the previous month’s total of $26.0 billion. Sales from the first quarter of 2016 were $78.3 billion, down 5.5 percent compared to the previous quarter and 5.8 lower than the first quarter of 2015. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Global semiconductor sales increased in March for the first time in five months, but soft demand, market cyclicality, and macroeconomic conditions continue to impede more robust growth,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Q1 sales lagged behind last quarter across nearly all regional markets, with the Americas showing the sharpest decline.”

Regionally, month-to-month sales increased in Japan (4.8 percent), Asia Pacific/All Other (2.3 percent), and Europe (0.1 percent), but fell in China (-1.1 percent) and the Americas (-2.8 percent). Compared to the same month last year, sales in March increased in Japan (1.8 percent) and China (1.3 percent), but decreased in Asia Pacific/All Other (-6.4 percent), Europe (-9.8 percent), and the Americas (-15.8 percent).

“Eighty-three percent of U.S. semiconductor industry sales are into markets outside the U.S., so access to overseas markets is imperative to the long-term strength of our industry,” Neuffer said. “The Trans-Pacific Partnership (TPP) is a landmark trade agreement that would tear down myriad barriers to trade with countries in the Asia-Pacific. The TPP is good for the semiconductor industry, the tech sector, the American economy, and the global economy. Congress should approve it.”

March 2016

Billions

Month-to-Month Sales                               

Market

Last Month

Current Month

% Change

Americas

5.03

4.89

-2.8%

Europe

2.66

2.67

0.1%

Japan

2.47

2.59

4.8%

China

8.02

7.93

-1.1%

Asia Pacific/All Other

7.83

8.01

2.3%

Total

26.02

26.09

0.3%

Year-to-Year Sales                          

Market

Last Year

Current Month

% Change

Americas

5.81

4.89

-15.8%

Europe

2.96

2.67

-9.8%

Japan

2.55

2.59

1.8%

China

7.83

7.93

1.3%

Asia Pacific/All Other

8.57

8.01

-6.4%

Total

27.70

26.09

-5.8%

Three-Month-Moving Average Sales

Market

Oct/Nov/Dec

Jan/Feb/Mar

% Change

Americas

5.75

4.89

-15.0%

Europe

2.77

2.67

-3.6%

Japan

2.57

2.59

0.8%

China

8.45

7.93

-6.1%

Asia Pacific/All Other

8.08

8.01

-0.8%

Total

27.62

26.09

-5.5%
Year-to-year percent change in world semiconductor revenues over the past 20 years.

Year-to-year percent change in world semiconductor revenues over the past 20 years.

According to the latest research study released by Technavio, the global semiconductor stepper system market is expected to reach over USD 6 billion by 2020.

This research report titled ‘Global Semiconductor Stepper System Market 2016-2020’, provides an in-depth analysis of market growth in terms of revenue and emerging market trends. This market research report also includes up to date analysis and forecasts for various market segments, including MEMS, advanced packaging, and LED devices.

“Due to an increasing demand for compact electronic devices in segments, such as consumer electronics, healthcare, and automotive, semiconductor IC manufacturers are forced to reduce the size of ICs. It has therefore given rise to the MEMS market, which is expected to experience a surge in its demand during the forecast period,” said Asif Gani, one of Technavio’s lead analysts for semiconductor equipment research.

“ICs are becoming denser with more transistors being installed in wafers, thus necessitating fine patterning. As the stepper system uses these processes, its demand for is likely to rise during the forecast period,” added Asif.

Segmentation of global semiconductor stepper system market by application 2015 (% share):

  • MEMs: 40.94%
  • Advanced Packaging: 31.50%
  • LED Devices: 27.56%

(Source: Technavio research)

Global semiconductor stepper system market by MEMS application

The global semiconductor stepper system market for MEMS application contributed a total revenue of USD 2.55 billion in 2015. MEMS has wide variety of applications in the consumer electronics, automotive, medical, industrial, telecom, and defense sectors. Consumer electronics is the largest market for MEMS applications, with mobile devices accounting for the largest share. Mobile devices include smartphones and wearables, which are installed with different types of MEMS sensors such as accelerometers, gyroscopes, and pressure sensors. These sensors are used for controlling screen orientation, gaming, navigation, and camera stabilization.

Global semiconductor stepper system market by LED devices application

The global semiconductor stepper system market for LED devices application contributed a total revenue of USD 1.71 billion in 2015. Stepper systems are used to manufacture LED devices with high brightness, including TVs, vehicle display screens, and tablet display screens. Lithography is a basic component in the manufacturing of LEDs. Technavio estimates an oversupply of semiconductor ICs in 2016 to reduce capital spending by semiconductor device manufacturers 2016, and it is expected to further reduce the demand for lithography and semiconductor stepper systems. However, the market will bounce back with the expected growth in semiconductor market from 2017 onwards.

Global semiconductor stepper system market by advanced packaging application

The global semiconductor stepper system market for advanced packaging application contributed a total revenue of USD 1.96 billion in 2015. As the semiconductor industry is moving toward miniaturization, manufacturers need to develop small-sized wafers with better performance and low cost. Therefore, advanced packaging technologies such as wafer-level packaging, flip-chip, and TSV provide better chip connectivity and low power consumption compared to conventional packaging techniques. These advantages drive the adoption of new technologies among manufacturers.

By Ed Korczynski, Senior Technical Editor

The world’s leading lithographers gather each year in San Jose, California at SPIE’s Advanced Lithography conference to discuss how to extend optical lithography. So of all the NGL technologies, which will win out in the end?

“Mix and Match” has long been a mantra for lithographers in the deep-sub-wavelength era of IC device manufacturing. In general, forming patterns with resolution at minimum pitch as small as 1/4 the wavelength of light can be done using off-axis illumination (OAI) through reticle enhancement techniques (RET) on masks, using optical proximity correction (OPC) perhaps derived from inverse lithography technology (ILT). Lithographers can form 40-45nm wide lines and spaces at the same half-pitch using 193nm light (from ArF lasers) in a single exposure.

Figure 1 shows that application-specific tri-layer photoresists are used to reach the minimum resolution of 193nm-immersion (193i) steppers in a single exposure. Tighter half-pitch features can be created using all manner of multi-patterning processes, including Litho-Etch-Litho-Etch (LELE or LE2) using two masks for a single layer or Self-Aligned Double Patterning (SADP) using sidewall spacers to accomplish pitch-splitting. SADP has been used in high volume manufacturing (HVM) of logic and memory ICs for many years now, and Self-Aligned Quadruple Patterning (SAQP) has been used in at least one leading memory fab.

FIGURE 1. Basic tri-layer resist (TLR) technology uses thin Photoresist over silicon-containing Hard-Mask over Spin-On Carbon (SOC), for patterning critical layers of advanced ICs. (Source: Brewer Science)

FIGURE 1. Basic tri-layer resist (TLR) technology uses thin Photoresist over silicon-containing Hard-Mask over Spin-On Carbon (SOC), for patterning critical layers of advanced ICs. (Source: Brewer Science)

Next-Generation Lithography (NGL) generally refers to any post-optical technology with at least some unique niche patterning capability of interest to IC fabs: Extreme Ultra-Violet (EUV), Directed Self-Assembly (DSA), and Nano-Imprint Lithography (NIL). Though proponents of each NGL have dutifully shown capabilities for targeted mask layers for logic or memory, the capabilities of ArF dry and immersion (ArFi) scanners to process >250 wafers/ hour with high uptime dominates the economics of HVM lithography.

The world’s leading lithographers gather each year in San Jose, California at SPIE’s Advanced Lithography conference to discuss how to extend optical lithography. So of all the NGL technologies, which will win out in the end?

It is looking most likely that the answer is “all of the above.” EUV and NIL could be used for single layers. For other unique patterning application, ArF/ArFi steppers will be used to create a basic grid/template which will be cut/trimmed using one of the available NGL. Each mask layer in an advanced fab will need application-specific patterning integration, and one of the rare commonalities between all integrated litho modules is the overwhelming need to improve pattern overlay performance.

Naga Chandrasekaran, Micron Corp. vice president of Process R&D, provided a fantastic overview of the patterning requirements for advanced memory chips in a presentation during Nikon’s LithoVision technical symposium held February 21st in San Jose, California prior to the start of SPIE-AL. While resolution improvements are always desired, in the mix-and-match era the greatest challenges involve pattern overlay issues.

“In high volume manufacturing, every nanometer variation translates into yield loss, so what is the best overlay that we can deliver as a holistic solution not just considering stepper resolution?” asks Chandrasekaran.

“We should talk about cost per nanometer overlay improvement.”

Extreme Ultra-Violet (EUV)

As touted by ASML at SPIE-AL, the brightness and stability and availability of tin-plasma EUV sources continues to improve to 200W in the lab “for one hour, with full dose control,” according to Michael Lercel, ASML’s director of strategic marketing. ASML’s new TWINSCAN NXE:3350B EUVL scanners are now being shipped with 125W power sources, and Intel and Samsung Electronics reported run their EUV power sources at 80W over extended periods.

During Nikon’s LithoVision event, Mark Phillips, Intel Fellow and Director of Lithography Technology Development for Logic, summarized recent progress of EUVL technology: ~500 wafers-per-day is now standard, and ~1000 wafer-per-day can sometimes happen. However, since grids can be made with ArFi for 1/3 the cost of EUVL even assuming best productivity for the latter, ArFi multi-patterning will continue to be used for most layers.

“Resolution is not the only challenge,” reminded Phillips. “Total edge-placement-error in patterning is the biggest challenge to device scaling, and this limit comes before the device physics limit.”

Directed Self-Assembly (DSA)

DSA seems most suited for patterning the periodic 2D arrays used in memory chips such as DRAMs. “Virtual fabrication using directed self-assembly for process optimization in a 14nm DRAM node” was the title of a presentation at SPIE-AL by researchers from Coventor in which DSA compared favorably to SAQP.

Imec presented electrical results of DSA-formed vias, providing insight on DSA processing variations altering device results. In an exclusive interview with Solid State Technology and SemiMD, imec’s Advanced Patterning Department Director Greg McIntyre reminds us that DSA could save one mask in the patterning of vias which can all be combined into doublets/triplets, since two masks would otherwise be needed to use 193i to do LELE for such a via array. “There have been a lot of patterning tricks developed over the last few years to be able to reduce variability another few nanometers. So all sorts of self-alignments.”

While DSA can be used for shrinking vias that are not doubled/tripled, there are commercially proven spin-on shrink materials that cost much less to use as shown by Kaveri Jain and Scott Light from Micron in their SPIE-AL presentation, “Fundamental characterization of shrink techniques on negative-tone development based dense contact holes.” Chemical shrink processes primarily require control over times, temperatures, and ambients inside a litho track tool to be able repeatably shrink contact hole diameters by 15-25 nm.

Nano-Imprint Litho (NIL)

For advanced IC fab applications, the many different options for NIL technology have been narrowed to just one for IC HVM. The step-and-pattern technology that had been developed and trademarked as “Jet and Flash Imprint Lithography” or “J-FIL” by, has been commercialized for HVM by Canon NanoTechnologies, formerly known as Molecular Imprints (http://cnt.canon.com/). Canon shows improvements in the NIL mask-replication process, since each production mask will need to be replicated from a written master. To use NIL in HVM, mask image placement errors from replication will have to be reduced to ~1nm, while the currently available replication tool is reportedly capable of 2-3nm (3 sigma).

Figure 2 shows normalized costs modeled to produce 15nm half-pitch lines/spaces for different lithography technologies, assuming 125 wph for a single EUV stepper and 60 wph for a cluster of 4 NIL tools. Key to throughput is fast filling of the 26mmx33mm mold nano-cavities by the liquid resist, and proper jetting of resist drops over a thin adhesion layer enables filling times less than 1 second.

FIGURE 2. Relative estimated costs to pattern 15nm half- pitch lines/spaces for different lithography technologies, assuming 125 wph for a single EUV stepper and 60 wph for a cluster of 4 NIL tools. (Source: Canon)

FIGURE 2. Relative estimated costs to pattern 15nm half- pitch lines/spaces for different lithography technologies, assuming 125 wph for a single EUV stepper and 60 wph for a cluster of 4 NIL tools. (Source: Canon)

Researchers from Toshiba and SK Hynix described evaluation results of a long-run defect test of NIL using the Canon FPA-1100 NZ2 pilot production tool, capable of 10 wafers per hour and 8nm overlay, in a presentation at SPIE-AL titled, “NIL defect performance toward high- volume mass production.” The team categorized defects that must be minimized into fundamentally different categories—template, non-filling, separation-related, and pattern collapse—and determined parallel paths to defect reduction to allow for using NIL in HVM of memory chips with <20nm half-pitch features.

To overcome the current market and technology constraints taking place today within the semiconductor industry, new advanced packaging technologies have been developed by industrial companies. Leaders in the advanced packaging industry have identified new solutions enabling more and more functionalities to be integrated along with many devices in the same package. Yole Développement analysts are currently noting plenty of excitement within the advanced packaging sector: research, innovation and industrialization are the key words of the current industry status.
In this context, NCAP China (NCAP) and Yole Développement (Yole) are pursuing their collaboration and have announced the second Advanced Packaging & System Integration Technology Symposium:
• The symposium will take place in Wuxi, China, on April 21 & 22.
• Click program & registration to see the schedule, list of speakers, abstracts, and more.

In 2014, the first symposium was a notable success: in addition to attracting more than 80 attendees, the show generated numerous valuable discussions, meetings and business collaborations. In 2016, NCAP and Yole are excited to welcome the leaders of the advanced packaging industry for the second time, and are expecting a similar success. They have announced an impressive list of executive speakers including:
•  Li Ming, R&D Director, ASM Pacific technology
•  Ruurd Boomsma, Sr. VP Die Attach & CTO Besi Die Attach & Besi Group
•  Farhang Yazdani, President & CEO, BroadPak Corporation
•  Herb He Huang, Ph.D., Sr. Director, 3DIC & Sensors Technology Development, Corporate R&D Center, Semiconductor Manufacturing International Corporation (SMIC)
•  And many more: the lists of speakers, biographies, and abstracts are available on the i-micronews website. To download the PDF version, click Program & Abstracts.

The collaboration between NCAP & Yole is based on strategic thinking from both organizations. Both names and their international reputation send a strong signal to the advanced packaging community.

NCAP is a technology development center. Its aim is to build up leading edges in advanced packaging by IP licensing and commercialization of technology development and transformation, with a smart combination of the packaging supply chain constraints. This organization has, of course, an important role to play at the national level by developing and supporting valuable advanced packaging expertise and capabilities with local industrial partners.

“The whole advanced packaging industry is facing unbalanced development of semiconductor equipment and materials,” explained Dr. Cao LiQiang, CEO of NCAP. “Prices and cost monitoring are crucial to ensuring the sustainability of the companies.”

For its part, as a “More than Moore” market research and strategy consulting company, Yole is pursuing its research within the advanced packaging world and is expanding its expertise and understanding of this industry, day after day. The number of technology and market reports available each year and dedicated custom collaborations with multiple companies throughout the advanced packaging supply chain show the leadership of the consulting company within this sector.

“At Yole, we expect solid advanced packaging market growth reaching US$30 billion by 2020,” explained Thibault Buisson, Business Unit Manager, Advanced Packaging & Semiconductor Manufacturing at Yole (Source: Status of the Advanced Packaging Industry 2015 report, Yole Développement, November 2015). And he added: “We currently see substantial activity in the Advanced Packaging ecosystem: many companies from different business models are getting involved in this area and the competition is intensifying, New innovative platforms such as System-in-Package, Fan-Out packages and 2.5D/3D technology are changing the industry landscape and turning a new page in Advanced Packaging evolution. This is the motivation behind the organization of the Advanced Packaging & System Integration Symposium. The symposium emphasizes the value transition in packaging and is aimed at providing answers to the current challenges and key questions that the industry is facing today.”

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“The Advanced Packaging & System Integration Technology Symposium taking place next week in China is the result of Yole & NCAP powerful collaboration, a combination of both technical know-how and market expertise,” said Jean-Christophe Eloy, President & CEO, Yole Développement. He adds, “It clearly represents a wonderful opportunity for advanced packaging companies to develop, exchange and expand their activities to the advanced packaging industry in China and also in all other countries.”

NCAP and Yole are extremely enthusiastic about the 2nd advanced packaging symposium. Both partners welcome all industry leaders including: Alpha Szenszor, ASE Group, ASM Pacific Technology, Besi, BroadPak, Evatec, EV Group, JCAP, HuaTian Technology, Huawei, Plasma-Therm, Sinyang, SPTS/Orbotech, STATS ChipPAC, Zeta Instruments, and more. To see the full schedule, please click here: Program.

Moreover, on the afternoon, and on a volunteer basis, NCAP will invite the participants to visit its facilites. Program includes NCAP Introduction, Material Consortium Plan Introduction, Lab Tour.
For more information about the schedule and registration, please contact: Clotilde Fabre ([email protected]), Communication Coordinator, at Yole Développement.

Worldwide semiconductor wafer-level manufacturing equipment revenue totaled $33.6 billion in 2015, a 1 percent decline from 2014, according to final results by Gartner, Inc. The top 10 vendors accounted for 77 percent of the market, down slightly from 78 percent in 2014.

“Slowing demand for key electronics end markets, combined with looming oversupply in memory, prompted semiconductor manufacturers to adopt conservative capital spending plans in 2015, which impacted spending on WFE,” said Bob Johnson, research vice president at Gartner. “Strength in memory spending was not sufficient to overcome caution in logic markets as major producers focused on logic process upgrades instead of adding new capacity.”

Applied Materials retained the No. 1 position in the WFE market with 1.3 percent growth (see Table 1). The industry’s investments in 3D device manufacturing, fin field-effect transistor (FinFET) and 3D NAND were the main drivers for the company’s growth in 2015. Lam Research experienced the strongest growth of the top 10 vendors in 2015, moving into the No. 2 position. The move of the industry to 3D device manufacturing pushed the company to 24.7 percent growth. Lam continues to be the dominant conductor etch manufacturer, but competition in the etch and deposition segment is expected to be fierce moving forward.

Table 1. Top 10 Companies’ Revenue From Shipments of Total Wafer-Level Manufacturing Equipment, Worldwide (Millions of U.S. Dollars)

Rank 2015

Rank 2014

Vendor

2015

Revenue

2015 Market Share (%)

2014

Revenue

2014-2015 Growth (%)

1

1

Applied Materials

6,420.2

19.1

6,335.1

1.3

2

4

Lam Research

4,808.3

14.3

3,857.0

24.7

3

2

ASML

4,730.9

14.1

5,634.5

-16.0

4

3

Tokyo Electron

4,325.0

12.9

4,666.7

-7.3

5

5

KLA-Tencor

2,043.2

6.1

2,129.2

-4.0

6

6

Screen Semiconductor Solutions

971.5

2.9

1,128.0

-13.9

7

10

Hitachi High-Technologies

788.3

2.3

937.3

-15.9

8

7

Nikon

724.2

2.2

818.1

-11.5

9

9

Hitachi Kokusai

633.8

1.9

599.3

5.7

10

13

ASM International

582.5

1.7

557.2

4.5

Others

7,576.7

22.5

7,271.2

4.2

Total Market

33,604.3

100

33,933.6

-1.0

Source: Gartner (April 2016)

“Capital spending in 2015 was selective, with logic manufacturers focused on upgrades and the latest technology buys, while memory added new capacity in response to increased demand and favorable pricing,” said Mr. Johnson. “However, there was another factor at work: Both the yen and euro declined significantly against the dollar in 2015. In a market which was essentially flat over the previous year, the changes in these exchange rates had a noticeable effect, especially in the lithography segment, where all tools are priced in either euros or yen.”

In dollar terms, lithography dropped 13 percent, the largest decline of any of the major segments. Two segments were especially strong: The ion implant segment grew 24 percent, and the material removal and clean segment grew 6 percent. Process control overall declined 2.5 percent, with the optical patterned wafer inspection segment dropping 15 percent as manufacturers held back on purchases of new inspection tools.

Additional information is provided in the Gartner report “Market Share: Semiconductor Wafer-Level Manufacturing Equipment, Worldwide, 2015.” The report provides rankings and market share for the top 10 vendors. In 2015, Gartner changed the segment reporting to focus on wafer-level manufacturing and is no longer providing segment details for die-level packaging or automatic test. This report is limited to wafer-level manufacturing equipment.