Category Archives: Wafer Level Packaging

Rudolph Technologies, Inc., has received an order for over $15 million from an unnamed foundry in Asia for multiple NSX 330 Systems.

The systems will be used for inspection of next-generation fan-out wafer level packaging products, including whole-wafer inspection and post-saw inspection. The systems will begin shipping in the fourth quarter of 2015 with the majority shipping in the first quarter of 2016.

“We are pleased to partner with this industry leader to provide the market-leading NSX System for their next-generation packaging line,” said Mike Goodrich, vice president and general manager of Rudolph’s Inspection Business Unit. “Key factors of this win were the systems’ superior inspection sensitivity, capture rate, and throughput for two-dimensional (2D) inspection, while meeting the automation challenges inherent with fan-out wafers and film frames. Additionally, all systems will be equipped with Rudolph’s Discover Yield Management Software that enhances the user’s process analysis capability in real-time, enabling fast yield improvement and increasing the productivity of each tool and the overall fab yield. This level of process visibility is quickly becoming essential to factory efficiency.”

“Rudolph has been enabling its customers’ development of advanced packaging processes for nearly two decades. We are pleased that our experience, combined with our unique fusion of hardware and software solutions, was selected to help our customer quickly ramp and control such a critical project,” said Mike Plisinski, CEO of Rudolph. “The development of advanced packaging solutions is a priority for many of our customers, as more of their customers specify packages utilizing fan-out, panel, and copper pillar technology to reduce the cost of devices while improving performance.”

Plisinski adds, “While the 2016 forecast for the overall semiconductor industry remains relatively subdued at 1.9 percent growth, according to Gartner, the development of next-generation advanced packaging processes continues to be an important growth driver for Rudolph. We are pleased that our comprehensive solutions-process, process control, and software-are helping to enable this growth.”

According to the newly released “Global Semiconductor Packaging Materials Outlook — 2015/2016 Edition,” the $18 billion semiconductor packaging materials will undergo steady single-digit unit volume growth for many material segments through 2019, including laminate substrates, IC leadframes, underfill, and copper wire. Segments such as wafer-level packaging (WLP) dielectrics will experience stronger unit volume growth over the same timeframe. The new report by SEMI and TechSearch International covers laminate substrates, leadframes, bonding wire, mold compounds, underfill materials, liquid encapsulants, die attach materials, solder balls, wafer level package dielectrics, and thermal interface materials.

Packaging materials are a key enabler to increasing the functionality of thinner, smaller packages consumed in smart phones and other mobile products. Many options are currently available to meet form factor requirements for mobile products such as stacked-die chip scale package (CSP), land grid array (LGA) and fine pitch ball grid array (FBGA) packages, package-on-package (PoP), wafer-level package (WLP), Quad Flat No-lead (QFN) and other packages, using both wirebond and flip chip interconnects.

Key observations include:

  • FO-WLP is emerging as a disruptive technology, changing the demand for the types of packaging materials used in the industry
  • Need for WLP dielectric materials for multi-layer redistribution layers
  • New materials for laminate substrates and underfill to pitch decreasing pitch and bump height trends in flip chip packaging
  • Improved mold compounds for warpage control and package reliability
  • For QFN packaging, cost optimization through enhanced designs and reduced plating area; higher lead counts (routable); improved power dissipation
  • Continued growth in copper and silver wire
  • Materials and processes compatible with tighter tolerances for higher density leadframes and substrate packaging, and for compact multi-die system-in-package (SiP) configurations

Constrained industry growth and the trend towards lower-cost electronics have reshaped the packaging material supplier landscape. Changes in material sets, the emergence of new package types, and cost reduction pressures have resulted in recent consolidation in various material segments. In addition, materials consumption in some segments is declining given the changes in package form factors and the trend towards smaller, thinner packaging (see Figure).

metal compound consump

Source: SEMI and TechSearch International, Global Semiconductor Packaging Materials Outlook 2015/2016 Edition

The findings in the report are based on over 150 in-depth interviews conducted with semiconductor manufacturers, fabless semiconductor companies, packaging subcontractors, and packaging materials suppliers throughout the world. The report covers details about the industry growth and trends for the various material segments. Information includes market size, regional data, unit trends, and market share. It includes previously unpublished data on revenue, unit shipments and market shares for each packaging material segment; a five-year forecast of revenue and units from 2015 to 2019; supplier rankings (for key segments) and listing (including new players); and an analysis of regional market trends and size. All of the information was derived from the SEMI Global Packaging Materials Outlook from 2015 to 2019 produced by SEMI and TechSearch International.

2016 bounce to modest gains


December 14, 2015

By Christian G. Dieseldorff, Industry Research & Statistics Group, SEMI

SEMI just published the latest quarterly update of its World Fab Forecast report.  While the year started with a positive outlook, the initial optimism has largely deflated, and the year will end largely flat. Fab equipment spending growth (new and used) for 2015 is expected to be 0.5 percent (US$ 35.8 billion). For 2016, spending is forecast to grow by 2.6 percent ($36.7 billion), with a possible continued upward trend.

Past trends prove again the close correlation of spending to global GDP and revenue.  The IMF predicted worldwide GDP to grow by 3.5 percent back in May, and has revised it down to only 3.1 percent.  Likewise, as of May, the year’s average revenue growth for the semiconductor industry was predicted to be in the mid- to high-single digits (according to ten leading market research firms).  Now these firms have revised their 2015 predictions to an average of just 1.3 percent.

Fab equipment spending (new, used and in-house) follows the same rollercoaster as revenue, and is now expected to grow by only 0.5 percent by the end of 2015, possibly 1 percent, according to SEMI.

Fab-Equipment-Spending

In 2015, 80 to 90 percent of fab equipment spending went to 300mm fabs, while only 10 percent was for 200mm or smaller.  SEMI’s recently published “Global 200mm Fab Outlook” provides more detail about past and future 200mm activities.

Cherish the Memory

Examining fab equipment spending by product type, Memory accounts for the largest share in 2015 and 2016. In 2015, DRAM spending was second in place but in 2016 3D Flash will, by far, outspend DRAM.

Most DRAM spending in 2015 went towards 21/20nm ramp.  In 2016, DRAM companies are expected to start risk production of 1xnm (for example, Samsung in 1H 2016; Hynix in 2H 2016; and Micron in 2016).

While 2015’s spending was dominated by DRAM, SEMI reports that 2016 will be dominated by Flash, mainly 3D-related architectures.  Capacity for 3D-NAND will continue to surge.  SEMI’s report tracks 10 major 3D producing facilities, with a capacity expansion of 47 percent in 2015 and 86 percent in 2016.

Foundry Segment Holds Steady

The Foundry segment is next in terms of the largest share of fab equipment spending in 2015 and 2016.  In general, the foundry segment shows steadier, more predictable spending patterns than other device product segments. The largest foundry player, TSMC, has a strong impact on the foundry industry.  In the second half of 2015, TSMC cut 2015 capex from $10.5 billion to $8 billion, due to a flagging market.  SEMI expects a stronger fourth quarter in 2015 for equipment spending for foundry as TSMC fulfills its capital expenditure for the year and we expect an increased capex in 2016.

TSMC recently announced revenue expectation for 2016 to be in double digits and expects to increase capex for 2016 as it ramps 16nm and adds initial 10nm capacity.

It’s Only Logical (and MPU)

Coming in third place in fab equipment spending, MPU had lower spending in 2015.  Intel revised its planned capex down four times, from $10 billion to $8.7 billion then to $7.7 billion, and finally to $7.3 billion, and it decided to delay the launch of 10nm products (Cannonlake) to 2H17.  Intel still announced lofty plans for 2016 capex, around $10 billion.  Especially in 2H16, spending will pick up for anticipated 10nm activities.

Meanwhile for Logic spending has been very strong in 2015, with 90 percent growth, driven by SONY’s CMOS image sensors.  This exuberant growth, however, is expected to slow down in 1H16.

Consequence of Consolidations: the End of Wild Times?

Between 2010 and 2014, change rates for equipment spending fluctuated wildly, from +16 percent in 2011 to -16 percent in 2012, -8 percent in 2013 to 15 percent in 2014. These drastic changes have been replaced by dampened spending growth rate for 2015 and into 2016.  Multiple reasons may apply: a more mature and lower growth industry, increased caution regarding capacity ramp, or perhaps the recent frenzy of consolidations further concentrating capex spending.  SEMI’s next quarterly publication, in February 2016, will give further insight into early indicators of 2017.  Will sedate, positive spending growth continue?

The SEMI World Fab Forecast Report in Excel format, tracks spending and capacities for 1,167 facilities across industry segments from Analog, Power, Logic, MPU, Memory, and Foundry to MEMS and LEDs facilities. It uses a bottoms-up approach methodology, providing high-level summaries and graphs and in-depth analyses of capital expenditures, capacities, technology and products by fab.  Learn more about the SEMI fab databases at: www.semi.org/MarketInfo/FabDatabase and www.youtube.com/user/SEMImktstats

SEMI, the global industry association for companies that supply manufacturing technology and materials to the world’s chip makers, this week reported that worldwide semiconductor manufacturing equipment billings reached US$9.6 billion in the third quarter of 2015. The billings figure is 3 percent higher than the second quarter of 2015 and 9 percent higher than the same quarter a year ago. The data is gathered jointly with the Semiconductor Equipment Association of Japan (SEAJ) from over 100 global equipment companies that provide data on a monthly basis.

Worldwide semiconductor equipment bookings were $8.7 billion in the third quarter of 2015. The figure is 7 percent lower than the same quarter a year ago and 14 percent lower than the bookings figure for the second quarter of 2015.

The quarterly billings data by region in billions of U.S. dollars, quarter-over-quarter growth and year-over-year rates by region are as follows:

 

3Q2015

2Q2015

3Q2014

3Q15/2Q15 (Qtr-over-Qtr)

3Q15/3Q14
(Year-over-Year)
Taiwan

2.85

2.34

2.30

22%

24%
China

1.70

1.04

0.96

63%

78%
Korea

1.56

2.00

1.00

-22%

56%
Japan

1.43

1.40

1.10

2%

30%
North America

1.18

1.55

2.16

-23%

-45%
Rest of World

0.58

0.53

0.64

9%

-10%
Europe

0.34

0.52

0.66

-36%

-49%
Total

9.64

9.39

8.82

3%

9%

Source: SEMI/SEAJ December 2015; Note: Figures may not add due to rounding.

The Equipment Market Data Subscription (EMDS) from SEMI provides comprehensive market data for the global semiconductor equipment market.

It is possible to fabricate copper pillars more than 100μm in height, with aspect ratios up to 6:1, using advanced packaging stepper lithography in conjunction with electroplating.

BY KEITH BEST, Rudolph Technologies, Wilmington, MA, and PHILLIP HOLMES, TEL NEXX, Billerica, MA

Recent years have seen rapid development in the area of advanced packaging. In general, advanced packaging processes are concerned with the interconnection of multiple chips in a single package to provide increased functionality and performance in a smaller volume. System Scaling Technology — the combination of front-end, middle-end and back-end to advance microelectronic systems—utilizes many different advanced packaging approaches, one of which is known as 2.5D packaging. The term “2.5D packaging” has not always been used consistently in literature. The definition used for the purpose of this paper can be summarized as follows: a 2.5D package utilizes an interposer between multiple silicon die and a system-in-package (SiP) substrate, where this interposer has through vias connecting the metallization layers on its front and back surfaces (FIGURE 1).

FIGURE 1. A 2.5D IC/SiP using an interposer and through vias.

FIGURE 1. A 2.5D IC/SiP using an interposer and through vias.

 

The development of these new packaging schemes is being driven primarily by the rapid growth in mobile handheld devices such as smartphones. Often, the manufacturing processes used are adaptations of well-established front-end processes. A number of different approaches are in development or already in production, including wafer-level chip scale packaging, copper pillar bumps on through silicon vias (TSVs), fan-out wafer level processing, and many more. Of particular interest is the replacement of solder bumps by fine pitch copper pillar bumps, which has been the subject of many new system- in-package designs. Here we investigate the lithography and plating of copper pillars, with focus on heights in excess of 100μm and diameters of 25μm, in anticipation of future SiP requirements.

The increase in the number of I/O channels required by multi-chip system designs has exceeded the density and pitch capabilities that traditional solder bump processes can deliver, so that an alternative connection scheme is required. For interposers, the key enabling technology has been the development of fine pitch copper pillar bumps to provide the high-density interconnection between the interposer and the die. Copper pillar bumps provide a number of advantages over the solder bumps they are supplanting. They can deliver finer pitches, 40μm and less have been demonstrated. They also provide superior electromigration performance in applications where high current-carrying capacity is required. However, lithography and electroplating for fine pitch copper pillar bumps can be particularly challenging. The pillars are electroplated into openings in a thick layer of photoresist which exceeds the capability of most front-end tools. Typically, today’s copper pillars range from 30-50μm in height, with height to width aspect ratios from 1:1 to around 2:1 Here we describe the lithography, resist, and electroplating systems and processes required to create 5:1 aspect ratio copper pillars with heights in excess of 100μm.

Photoresist

A negative tone photoresist (JSR THB-151N) was chosen for this work. Its acrylate groups cross-link on exposure and are developed in industry standard 2.38% TMAH developer. The photoresist was spun to a thickness of 120μm on 300mm silicon wafers with an under bump metallization (UBM) prepared seed layer. To reach the 120μm photoresist film thickness, two coatings of photoresist were required, soft baked at 130C, 300secs and 130C, 360secs respectively. After coating, the photo- resist film was allowed to rehydrate for one hour prior to exposure on a wafer stepper (Rudolph Technologies’ JetStep System).

Lithography

We used a customized test reticle that included a wide range of sizes and pitches to expose the wafer. When processing a thick photoresist, well-controlled sidewall angles are a critical requirement, especially when electroplating tall copper pillars. Most front-end tools have high numerical aperture (NA) lenses with low depth of focus (DOF) that prevent adequate exposure of thick films with sufficient image contrast to meet the sidewall angle and resolution requirements. Mask aligners also struggle with high aspect ratio imaging, not because of their NA, but because they are unable to provide the necessary focus offset required to expose the film at high resolution, ultimately limiting their aspect ratio and sidewall angle control. Although photoresist sidewall angles are primarily a function of the photoresist material and its processing (pre-bake, post-bake, developing, etc.), the exposure system plays an important role. Accurate focus control across the wafer or substrate is required to achieve consistent and accurate CD control with straight and perpendicular sidewalls.

The lithography stepper employed in this study refocuses for each exposure to ensure optimal focal plane height on advanced packaging substrates that are frequently warped by film stress and thermal cycling. The system’s 0.1 NA provides a large depth of focus to maintain image integrity and CD control through thick films. The stepper lens is achromatized and the installed “filter wheel” provides a choice of illumination wavelengths to expose the photoresist layers: “broadband” ghi (350-450nm), gh (390 to 450nm) or i-line (365nm). This study, with a photoresist thickness of 120μm, required high energy illumination of >1000 mJ/cm<sup>2</sup>, so broadband illumi- nation (g,h,i wavelengths) was employed to maintain high throughput.

The coated wafers were exposed using a focus exposure matrix wafer layout which provided a large number of programmed focus and exposure conditions at a fixed stepping distance to enable quick and efficient character- ization of the lithography process window for any pillar CD. After exposure, the wafers were developed for a total time of 180 secs, using 6 puddles in 2.38% TMAH. A number of wafers were processed in this way to provide images of the resist structures prior to the electroplating process. The SEM micrograph in FIGURE 2 shows a cross section of the photoresist via mold structures, the CD limit appears to be 25μm with this process, since the via is not open to the seed metal beyond this resolution.

lithography 2

It is interesting to note how the sidewall angle of the photoresist changes with decreasing CD suggesting that the plating will generate a “pedestal” type of copper pillar base at larger CDs, becoming progressively more vertical at smaller CDs. However, upon closer inspection of the smallest CDs, a slight “footing” can be observed at the base of the via (FIGURE 3), and this could result in slight undercut of the final copper pillar. The footing effect was most likely the result of our unoptimized develop process.

lithography 3

Electroplating

After the lithography processing, the wafers were sent to TEL NEXX for electroplating. The plating process employed the TEL NEXX Stratus P300 System, a fully automated electrochemical deposition system for advanced wafer-level packaging applications. The system deposits thick metal layers for wafer bumping, redistribution layers, TSVs, integrated passives, and MEMS.

In this study, we used a methanesulfonic acid copper chemistry with organic additives. The bath composition, operating temperature and current waveform were optimized for high speed copper plating into very thick resist features with flat bump profiles. After plating the photoresist was stripped using an immersion bath with EKC162 solution at 60 degrees. To preserve the profile of the photoresist mold the seed layer was not etched. The final copper pillar structures exhibit the inverse photo- resist mold profile (FIGURE 4).

lithography 4

The electroplating process successfully deposited copper in the photoresist via “molds” that were open to the copper seed material, producing good quality copper pillars with a final minimum copper pillar CD of 20μm, indicating a process bias of 5μm. This bias enabled the final copper pillar to reach a 6:1 aspect ratio as shown in FIGURE 5.

lithography 5

The final copper pillars exhibit excellent sidewall angle, 90 degrees for the smaller CDs. The profiles correlate well with the profiles observed in the photoresist SEM cross sections. The change in profile at the base of the photoresist for the smaller CDs did result in a slight undercut of the final copper pillar. The removal of this photoresist foot could be achieved by either increasing the de-scum time or modifying the develop recipe. The larger copper pillars tended to flare out slightly at the base (FIGURE 6) compensating for any undercut. This will benefit the structure during the removal of the copper seed layer.

lithography 6

The rheology of the copper pillar surface is very important for bonding reliability and the uniform plating of Sn solder, which was not performed during this particular study since it was not the primary objective. FIGURE 7 shows the flat top surface of a copper pillar which is free of voids and defects.

lithography 7

For advanced packaging applications, precise copper pillar height control is essential, and lithography CD control plays an important part in the plating process since CD variation directly affects plated height. The electroplating rate is proportional to current per unit area, i.e. the open area at the bottom of the photoresist openings at the beginning of the process, and the area of the evolving metal surface during deposition. Variation in CD or sidewall angle across the wafer will result in a corresponding change in copper pillar height. For example, in the case of copper pillar features a 5% change in CD can cause a 10% change in plated height.

Conclusion

The results of this study prove that it is possible to fabricate copper pillars more than 100μm in height, with aspect ratios up to 6:1, using advanced packaging stepper lithography in conjunction with electroplating. As advanced packaging requirements continue to evolve, the ability to create smaller copper pillar CDs at finer pitches in thick films will provide increased I/O density opportunities for SiP designers. Furthermore, it is clear that achieving high yield and reliability in the final package requires precise CD control throughout the entire photoresist profile to ensure consistent copper pillar height.

KEITH BEST is director applications engineering at Rudolph Technologies, Wilmington, MA. PHILLIP HOLMES is director of technology at TEL NEXX, Billerica, MA

Subtleties in thicknesses between the alternating Cu metal and dielectric layers within a build-up substrate can impact BLR performance.

BY JAIMAL WILLIAMSON, Texas Instruments, Dallas, TX

Managing an organization in an orderly and disciplined manner is known as “running a tight ship.” This mentality and discipline cannot be understated with build-up substrate supplier capability and manufacturing tolerances as it relates reliability and margin in a flip chip ball grid array (FCBGA) device. Build-up substrate technology is the backbone for flip chip packaging due to its ability to bridge high density interconnects and functionality enabling improved electrical performance in tandem with the semiconductor chip. Alternating metal and dielectric layers build up the substrate into the final composite structure. The range of thicknesses of the aforementioned metal and dielectric layers are dependent on associated substrate manufacturer design rules, which can have an impact on board level reliability (BLR). Having a keen awareness of substrate supplier design rules can aid not only troubleshooting, but improve understanding of reliability margin from a chip to package interaction standpoint for any array of commercial and automotive FCBGA applications.

Influence of copper and dielectric layers on reliability

To better understand the thickness variation impact of bottommost substrate copper (Cu) metal (15 +/- 5μm) and dielectric (30 +/-6μm) layers as it relates to strain energy density of BGA solder joint at die shadow area and package corner, a 3×3 factorial design of experiments (DoE) approach (FIGURE 1) was pursued. Through the use of finite elemental modeling, outputs of the study included both strain energy density under -40°C to 125°C and 0°C to 100°C BLR temperature cycle conditions and changes in coefficient of thermal expansion (CTE) as Cu metal and dielectric thicknesses varied. For the remainder of the article, results from the more stringent -40°C to 125°C BLR temperature cycle condition will be discussed.

FIGURE 1. 3x3 factorial DoE.

FIGURE 1. 3×3 factorial DoE.

Rationale of the study was based on a striking difference in BLR performance from two FCBGA daisy chain test vehicles having an identical substrate design, but manufactured at two different substrate suppliers (noted as supplier A and B in this article). The FCBGA daisy chain test vehicle comprises the following package attributes (see FIGURE 2 for a side view example):
• 40mm x 40mm body size
• 8-layer build-up stack (3/2/3)
• 400μm core thickness
• 1mm BGA pitch

FIGURE 2. Example of FCBGA package.

FIGURE 2. Example of FCBGA package.

Weibull analysis was generated from empirical BLR results at 5 percent and 63.2 percent cycles to failure. Specifically, at 5 percent cycles to failure supplier A exhibits ~25 percent reduced BGA solder joint fatigue life than counterparts from supplier B (as illustrated in FIGURES 3 and 4).

FIGURE 3. Weibull plot of supplier A.

FIGURE 3. Weibull plot of supplier A.

FIGURE 4. Weibull plot of supplier B.

FIGURE 4. Weibull plot of supplier B.

In a similar study focusing on component level reliability (CLR), it was observed that bottommost substrate Cu layer thickness can impact stress underneath die shadow area. For these reasons, a more detailed examination was done to measure bottommost substrate Cu layer thickness from daisy chain units of suppliers A and B. Based on package construction analysis, supplier A was found to target the nominal value of 15μm; whereas supplier B targeted the high end of specification at 20μm. These Cu thickness differences would play a significant role in the BLR results.

Stress modeling results

Outputs of the finite elemental modeling are revealed in FIGURE 5 based on inputs from the aforementioned 3×3 factorial DoE illustrated in Fig. 1. Based on the combi- nation of various Cu and dielectric layer thicknesses evaluated, thicker dielectric and Cu layers yield higher macroscopic CTE values. This is an expected trend based on CTE material properties of Cu and dielectric layers in relation to the substrate core material. Simulation results confirmed CTE in ascending order is: dielectric layer > Cu layer > substrate core. Comparing Weibull analysis from supplier A and B (figures 3 and 4), DoE legs 4 and 6 match best, respectively, to the empirical BLR results. In addition, DoE legs 4 and 6 align with the bottommost substrate Cu layer thickness values from the aforemen- tioned package construction analysis measurements. It is noted that based on modeling results, an approximately 2 percent change in CTE can swing the cycles to failure at 63.2 percent by ~11 percent. DoE leg 4 focuses on nominal Cu thickness of 15μm; whereas leg 6 focuses on the high end of the Cu thickness tolerance at 20μm. Dielectric thickness is nominal value of 30μm in both DoE cases. Improved BLR performance from supplier B is attributed to the thicker Cu providing a better CTE match to the BLR test board.

FIGURE 5. Finite elemental modeling results.

FIGURE 5. Finite elemental modeling results.

Use of JMP for statistical perspective

As a supplemental tool for data interpretation, JMP statistical analysis was performed to illustrate how nominal and extreme values of the metal and dielectric layer thickness specification affect FCBGA BLR performance. Analyzing the strain energy data outputs, the model fit well to the predicted values as shown in FIGURE 6. Similarly, CTE correlated well with predicted values as illustrated in FIGURE 7. Use of the prediction profiler function, as illustrated in FIGURE 8, shows CTE is proportional to increase in metal and dielectric thickness, which correlates with the stress modeling results.

FIGURE 6. JMP model of SED predicted vs. actual.

FIGURE 6. JMP model of SED predicted vs. actual.

FIGURE 7. JMP model of CTE predicted vs. actual.

FIGURE 7. JMP model of CTE predicted vs. actual.

FIGURE 8. CTE prediction as a function of metal and dielectric thickness

FIGURE 8. CTE prediction as a function of metal and dielectric thickness

Summary

Subtleties in thicknesses between the alternating Cu metal and dielectric layers within a build-up substrate can impact BLR performance. Two identical daisy chain substrate designs manufactured by different suppliers were compared head to head. A detailed package construction analysis revealed differences in bottommost Cu thickness layer within the substrate. This Cu thickness delta between the two substrate designs caused a change in CTE with supplier B (higher value) than supplier A due to thicker copper. Finite element modeling demon- strated relatively small macroscopic changes in CTE on the order of less than 2 percent can affect cycles to failure by 11 percent.

The key takeaway found from the head to head evaluation was supplier A producing a more stable process as it was able to meet the center point of the Cu thickness specification as compared to supplier B, which was off target. However, in essence, supplier A lost the head to head BLR comparative study with supplier B as its accuracy in meeting the Cu thickness target caused reduced solder joint fatigue life. The typical corrective action would be to work with supplier B to establish better tolerance control in their Cu plating process to stabilize Cu thickness at the center or nominal value like supplier A. However, the lesson learned was to tailor and control the Cu thickness at the higher end of the specification to improve reliability performance. Typically, in any setting the criteria of success is to hit the bullseye or target, which supplier A achieved. Conversely, supplier B missed this mark with results that were skewed to the right. Ironically, because of the skewed results off-target reliability margin was obtained. In reflection of these findings, the adage “success is in the eyes of the beholder” has never been more poignant.

JAIMAL WILLIAMSON is a packaging engineer responsible for development and qualification of Embedding Processing FCBGA devices within Texas Instruments’ Worldwide Semiconductor Packaging group.

CEA-Leti today announced preliminary steps for demonstrating a quantum bit, or qubit, the building block of quantum information, in a process utilizing a silicon-on-insulator (SOI) CMOS platform.

While the leading solid-state-based approach today for treating quantum information uses superconducting qubits, there are several potential alternatives. These include semiconductor spin qubits, historically demonstrated in III-V materials, but with limited “lifetime” due to coupling between the electron spin and the nuclear spins of the III-V elements.

Only in recent years has the prospect of using nuclear spin-free, isotopically purified silicon-28, the most-common isotope, made silicon an especially attractive candidate for hosting electron spin qubits with a long quantum coherence time. The main challenge now is defining an elementary cell compatible with circuit upscaling to hundreds of qubits and more.

Leti and its long-time research partner Inac, a fundamental research division of CEA, are investigating a silicon-on-insulator (SOI) technology for quantum computing with proven scalability, since it was originally developed for CMOS VLSI circuits. In this approach, quantum dots are created beneath the gates of n-type (respectively p-type) field effect transistors, which are designed to operate in the “few-electron” (respectively “few-hole”) regime at cryogenic temperatures (below 0.1 K).

Leti and Inac have developed a process for mastering control of the operation of both types of devices using Leti’s SOI nanowire FET technology. Their teams have demonstrated the co-integration and successful operation of quantum objects with conventional CMOS control electronics (standard ring oscillators) on 300mm SOI substrates.

“This technology has acquired a certain degree of robustness, and we aim at using it with very minor modifications to demonstrate qubits co-integrated with their control electronics,” said Louis Hutin, scientific staff. “This co-integration success represents a critical asset for the eventual design of a quantum computer.”

CEA-Leti today announced it has signed an agreement with Keysight Technologies, a device-modeling software supplier, to adapt Leti’s UTSOI extraction flow methodology within Keysight’s device modeling solutions for high-volume SPICE model generation.

The simulation of the Leti-UTSOI compact model, which is the first complete compact model dedicated to Ultra-Thin Body and Box and Independent Double Gate MOSFETs, is currently available in Keysight’s modeling and simulation tools. This agreement expands the collaboration to include the extraction flow and will enable device-modeling engineers to efficiently create Leti-UTSOI model cards for use in Process Design Kits (PDKs).

“This collaboration between Leti and Keysight will strengthen the global FD-SOI ecosystem by providing an automatic extraction flow for building model cards associated with the Leti-UTSOI models, which are already available in all the major SPICE simulators,” said Marie Semeria, Leti’s CEO. “This professional, automatic extraction-flow solution will address designers’ needs as they weigh FD-SOI’s benefits over competing solutions for the 28nm technology node and below.”

“Keysight’s modeling solutions provide both automation and flexibility for device modeling,” said Todd Cutler, general manager of Keysight EEsof EDA. “The addition of a Leti-UTSOI modeling technology will further expand our offering in CMOS modeling. We have been collaborating with Leti on many projects, and we are pleased to extend our relationship to improve access to the Leti-UTSOI.”

The Semiconductor Industry Association (SIA) announced worldwide sales of semiconductors reached $29.0 billion for the month of October 2015, 1.9 percent higher than the previous month’s total of $28.4 billion and 2.5 percent lower than the October 2014 total of $29.7 billion. The Americas market posted 3.9 percent growth compared to last month, leading all regions. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average. Additionally, a new WSTS industry forecast projects slight market growth for the next three years.

“Global semiconductor sales have shown signs of stabilizing in recent months, with October marking the third straight month of month-to-month growth,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Year-to-date sales are narrowly ahead of where they were through the same time last year, and slight growth is projected for next year and beyond.”

Month-to-month sales increased across all regional markets: the Americas (3.9 percent), China (1.6 percent), Europe (1.2 percent), Japan (0.4 percent), and Asia Pacific/All Other (1.7 percent). Compared to October 2014, sales were up in China (5.7 percent), but down in the Americas (-5.6 percent), Europe (-9.4), Japan (-10.5 percent), and Asia Pacific/All Other (-2.4 percent).

Additionally, SIA endorsed the WSTS Autumn 2015 global semiconductor sales forecast, which projects the industry’s worldwide sales will reach $336.4 billion in 2015, a 0.2 percent increase from the 2014 sales total. WSTS projects year-to-year increases for 2015 in Asia Pacific (3.9 percent), with decreases projected for the Americas (-0.6 percent), Europe (-8.2 percent), and Japan (-10.3 percent).

Beyond 2015, the global market is expected to grow at a modest pace. WSTS forecasts 1.4 percent growth globally for 2016 ($341.0 billion in total sales) and 3.1 percent growth for 2017 ($351.6 billion). WSTS tabulates its semi-annual industry forecast by convening an extensive group of global semiconductor companies that provide accurate and timely indicators of semiconductor trends.

October 2015

Billions

Month-to-Month Sales                               

Market

Last Month

Current Month

% Change

Americas

5.82

6.05

3.9%

Europe

2.87

2.90

1.2%

Japan

2.69

2.70

0.4%

China

8.45

8.58

1.6%

Asia Pacific/All Other

8.58

8.72

1.7%

Total

28.41

28.96

1.9%

Year-to-Year Sales                          

Market

Last Year

Current Month

% Change

Americas

6.41

6.05

-5.6%

Europe

3.21

2.90

-9.4%

Japan

3.01

2.70

-10.5%

China

8.12

8.58

5.7%

Asia Pacific/All Other

8.94

8.72

-2.4%

Total

29.68

28.96

-2.5%

Three-Month-Moving Average Sales

Market

May/Jun/Jul

Aug/Sept/Oct

% Change

Americas

5.51

6.05

9.7%

Europe

2.83

2.90

2.5%

Japan

2.63

2.70

2.3%

China

8.18

8.58

5.0%

Asia Pacific/All Other

8.71

8.72

0.2%

Total

27.87

28.96

3.9%

“Advanced packaging will reach 44% of packaging services and a revenue of US$ 30 billion by 2020,” Yole Développement (Yole) announced. Overall, the main advanced packaging market is the mobile sector with end products such as smartphones and tablets. Other high volume applications include servers, PC, game stations, external HDD/USB and more.

According to Yole’s latest advanced packaging report entitled “Status of the Advanced Packaging Industry” (2015 Edition), emerging applications are coming from the IoT world, with wearables and home appliances (connected home) solutions already penetrating the market. Other early stage IoT investments have been also made in smart cities, connected cars, industrial devices, medical applications…

In parallel, the Chinese companies play an important role in the advanced packaging market growth: “At Yole, we see an increased activity of Chinese capital in the advanced packaging industry,” explains Andrej Ivankovic, Technology & Market Analyst, Advanced Packaging & Semiconductor Manufacturing at Yole. “The objective of the semiconductor transformation in China is to decrease external dependency and set up a complete internal supply chain that can serve domestic and international customers.”

In this context, what would be the evolution of the advanced packaging industry? What will be the status of the supply chain by 2020? Which packaging technologies will be the most critical tomorrow and after? With the emergence of IoT applications, the development of local Chinese industry and numerous M&A coming from the overall semiconductor industry and the direct impact on the advanced packaging supply chain. Yole’s advanced packaging analysts offer you insight into the new advanced packaging world.

“Status of the Advanced Packaging Industry” report (2015 edition) released by Yole, the “More than Moore” market research and strategy consulting company, provides an high added-value market overview of the industrial landscape; under this new report, Yole’s advanced packaging team proposes a comprehensive analysis of the technology trends and also assesses the future development of the advanced packaging market.

packaging industry graph

This analysis confirms the market positioning of Yole and highlights the knowledge and deep understanding of the company within this industrial field.

According to Yole’s estimates, advanced packaging services revenue will increase by US$9.8 billion from 2014 to 2020 at a CAGR of 7%, in majority due to high volume adoption of Fan-Out WLP, 2.5D/3D and evolution and growth of Fan-In WLP and flip-chip. Advanced packages currently account for 38% of all packaging services or US$ 20.2 billion and are expected to grow share to 44% and US$ 30 billion by 2020.

The mobile sector remains the main advanced packaging market with smartphones and tablets as end products. Other high volume applications include servers, PC, game stations, HDD/USB, WiFi hardware, base stations, TVs and set top boxes. The scent of IoT is spreading with first products already on the market in the form of wearables and smart home appliances. Further early stage investments are made in sectors such as smart cities, connected cars, various industrial devices and medical applications.

The flip-chip platform represents a large mature market and leads in packaging services revenue and wafer count. Fan-In WLP leads in unit count due to small size compared to demanded volume. Adoption of wafer level packages continues. Teardowns performed by Yole and its sister company, System Plus Consulting on 3 high end smartphones (more info on i-micronews.com, reports section or click here directly for iPhone 6+, Samsung Galaxy S6 as well as the Huawei Ascend Mate 7 analysis, that will be available soon) indicated a high penetration rate of WLP, 30% on average. Fan-Out WLP is expected to make a major breakthrough within the next year, likely led by TSMC inFO PoP and followed by other Fan-Out multi die solutions. Long term, a bright future lies ahead for wafer level packages with respect to IoT requirements as they are well position to answer related cost, form and functional integration demands. When it comes to advanced feature sizes, a competitive sub 10 µm / 10 µm arena is established where organic wafer level packages aggressively compete with advanced organic flip-chip substrates and 2.5D / 3D Si/glass interposers.

As WLP pin counts grow, thicknesses and overall cost decrease, the evolution of Fan-In WLP and in particular a breakthrough of Fan-Out WLP are expected to result in a takeover of a part of the flip-chip market. With the breakthrough of Fan-Out WLP, the packaging landscape might drastically change, with an IDM and foundry leading all packaging services by wafer count.

The full advanced packaging analysis is today available; in the report Yole’s analysts present revenue, wafer and unit forecasts per advanced packaging platform and production breakdown by device type such as analog/mixed signal, wireless/RF, logic and memory, CMOS image sensors, MEMS, LED and LCD display drivers.