Category Archives: Wafer Level Packaging

IC Insights will release its new 2016 McClean Report late next month.  The 2016 McClean Report will include a ranking of the top-50 semiconductor suppliers’ for 2015 as well as the top-50 fabless semiconductor suppliers.  The forecasted “post-merger” top-10 2015 IDM and fabless semiconductor suppliers are covered in this research bulletin.

Unlike the relatively close annual market growth relationship between fabless semiconductor suppliers and foundries, fabless semiconductor company sales growth versus IDM (integrated device manufacturers) semiconductor supplier growth has typically been very different (Figure 1).  In 2010, for the first and only time on record thus far, IDM semiconductor sales growth (35%) outpaced fabless semiconductor company sales growth (29%).  Since very few fabless semiconductor suppliers participate in the memory market, the fabless suppliers did not receive much of a boost from the surging DRAM and NAND flash memory markets in 2010, which grew 75% and 44%, respectively.

As shown in Figure 2, only three of the top-10 IDM semiconductor suppliers are forecast to register growth in 2015 and, in total, the top-10 IDMs are expected to display flat growth this year.  Although flat growth by the top-10 IDMs would typically be considered poor performance, it is still forecast to be a much better result than is expected from the top-10 fabless semiconductor suppliers (Figure 3).  In order to make direct comparisons for year-over-year growth, IC Insights combined the merged, or soon to be merged, companies’ 2014 and 2015 semiconductor sales regardless of when the merger occurred.

As shown, the top-10 fabless semiconductor suppliers are forecast to register a 5% decline in sales this year, five points worse than the top-10 IDMs.  It should be noted that essentially all of the decline expected for the top-10 fabless suppliers in 2015 could be attributed to the forecasted decline in Qualcomm/CSR’s sales this year.  Much of the sharp decline in Qualcomm/CSR’s sales this year is being driven by Samsung’s increasing use of its internally developed Exynos application processor in its smartphones instead of the application processors it had previously sourced from Qualcomm.

Fig 1

Fig 1

Fig 2

Fig 2

Fig 3

Fig 3

Application processor sales to fabless/system house Apple from pure-play foundry TSMC are included in the fabless company sales ranking under the “Apple/TSMC” moniker.  Application processor sales supplied to Apple from IDM-foundry Samsung are included as part of Samsung’s logic IC sales.

As mentioned in the title of this Research Bulletin, 2015 could end up being only the second year ever, after 2010, in which the IDM semiconductor suppliers outpace the fabless semiconductor suppliers with regard to year-over-year growth.  Whether this actually takes place will be revealed from IC Insights’ extended compilation of the IDM and fabless semiconductor company rankings for the 2016 McClean Report.

GaN Systems, a manufacturer of gallium nitride power transistors, announces that its foundry, Taiwan Semiconductor Manufacturing Corporation (TSMC), has expanded the high volume production of products based on GaN System’s proprietary Island Technology by 10X in response to surging global demand from consumer and enterprise customers. GaN Systems has the industry’s broadest and most comprehensive portfolio of GaN power transistors with both 100V and 650V GaN FETs shipping in volume.

Transistors based on GaN Systems’ Island Technology and using TSMC’s GaN fab process boast the best performance and Figure of Merit in the industry, easily outstripping the capabilities of the world’s highest performance silicon power semiconductors, the latest silicon carbide devices and competing gallium nitride products. The unique combination of TSMC’s gallium nitride process and GaN Systems’ proprietary Island Technology design is further enhanced by GaNPX packaging, which delivers high current handling, extremely low inductance and exceptional thermal performance. GaN Systems’ power switching transistors continue to lead the gallium nitride market, providing best-in-class 100V and 650V devices and driving product innovation ranging from thinner TVs to extended range electric vehicles.

Sajiv Dalal, VP Business Management at TSMC, comments, “We are delighted to confirm that our collaboration with GaN Systems has brought the promise of gallium nitride from concept through reliability testing and on to volume production.”

Adds Girvan Patterson, GaN Systems’ President, “GaN has emerged as the power semiconductor solution of choice. Smart mobile devices, slim TVs, games consoles, automotive systems and other mass volume items have been designed with GaN transistors as the enabling power technology, so it is imperative that devices are available in correspondingly large quantities. Using our patented Island Technology, we have designed and made available for widespread adoption GaN power solutions that greatly exceed the performance standards exhibited by silicon devices. That is why, after three years of working together, we are so excited to formally announce our collaboration with TSMC, the world’s leading third-party semiconductor manufacturing company and a byword for quality and service industry-wide.”

Delivering large volumes of highly reliable GaN transistors in near-chipscale packaging is the culmination of a journey GaN Systems began in 2008. The company was founded with the mission of creating a low cost, highly reliable GaN-on-Silicon product based on Island Technology, a method of creating small islands where electro-migration is mitigated, die size is minimized and very high current devices realized with high yield. Using Island Technology with TSMC’s GaN-on-Silicon manufacturing techniques enabled GaN Systems to deliver the most usable, high performance, normally-off transistor to the market in mid-2014. This has allowed global power system manufacturers in the energy storage, enterprise and consumer markets to design, develop, test and bring to market more powerful, lighter and far smaller new products in their quest to attain competitive edge. To meet customers’ increasing demand for high GaN volumes in 2016, TSMC’s commitment to volume production flow comes at the perfect time.

Intel and ASM look to TCB


November 17, 2015

BY PHIL GARROU, Contributing Editor

In the September column, we looked at some of the key thermo-compression bonding (TCB) papers at ECTC. Is there any question that TCB is real and will be the next big bonding technology? The focus this month is more on this very important new assembly process from Intel and ASM.

Intel introduced TCB into high volume manufacturing in 2014. As substrate and die become thinner and solder bump sizes and pitches get smaller, the thin organic substrate tends to warp at room temp and as the temp is increased during the reflow process. The thin die can also demonstrate temperature dependent warpage, which can come into play during the reflow process. The extent of warpage of the substrate and die at high temperatures can overcome the natural solder surface tension force leading to die misalignment with respect to the substrate, resulting in tilt, non-contact opens (NCO) and in some cases solder ball bridging (SBB). FIGURE 1 shows these various defects.

Phil Garrou

In the Intel TCB process, the substrate with pre-applied flux is held flat on the hot pedestal under vacuum. The die is picked up by the bond head, held securely and flat on the bond head with vacuum. After the die is aligned with the substrate, the bond head comes down and stops when the die touches the substrate. A constant force is then applied while the die is heated up quickly beyond the solidus temperature. As soon as the solder joint melts, the die is moved further down (solder chase) to ensure all solder joints are in contact. The die is held in position allowing the solder to reflow completely, and to wet the bump pads and copper pillars. While the solder is still in the molten state, the bond head retracts upwards controlling the solder joint height. The bond head then releases the vacuum holding the die and moves away as the solder joints have solidified. The major process parameters, i.e temperature, force and displacement are continuously monitored during the TCB bonding process.

Large differences in the CTE between the organic substrate and die results in different magnitude of expansions when heated which can lead to serious bump offset at corners. To minimize the thermal expansion mismatch, the substrate is processed at a lower temperature (e.g. 140°C) while the die and solder is rapidly heated up for reflow and cooled down for solidification using a pulse heater with heating ramp rate exceeding 100°C/s and cooling ramp rate exceeding 50°C/s. This reduces the heat transfer to the substrate. The bulk of the substrate can remain at low temperature and does not expand extensively.

In another ASM paper on TCB they examined what they call liquid phase contact (LPC) TCB. The goal is to increase the throughput of the TCB process. Process flow is shown below. Flux is printed or sprayed on the substrate. Then the bonding head picks up a die from the carrier at an elevated temperature, but below the solder melting point. Then the bonding head is heated up to a temperature higher than the solder melting point and the chip is aligned with the substrate. The chip is then contacted and wetted on the substrate at a predeter- mined bonding height. After a predetermined bonding time, the bonding head can move is cooled down to a temperature below the melting point of solder. They claim this results in attachment of 1200 units/hr vs 600 for the standard TCB flux process.

Worldwide silicon wafer area shipments decreased during the third quarter 2015 when compared to second quarter area shipments according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry.

Total silicon wafer area shipments were 2,591 million square inches during the most recent quarter, a 4.1 percent decrease from the record amount of 2,702 million square inches shipped during the previous quarter. New quarterly total area shipments were flat when compared to third quarter 2014 shipments.

“After two consecutive record breaking quarters, quarterly silicon shipment growth slightly declined,” said Ginji Yada, chairman of SEMI SMG and general manager, International Sales & Marketing Department of SUMCO Corporation. “Quarterly shipments for the most recent quarter are on par with the same quarter as last year, with total silicon shipment volumes for 2015 through the end of the third quarter higher relative to the same period last year.”

Quarterly Silicon* Area Shipment Trends

Million Square Inches

Q3-2014

Q2-2015

Q3-2015

9M-2014

9M-2015
Total

2,597

2,702

2,591

7,548

7,930

* Shipments are for semiconductor applications only and do not include solar applications

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers, as well as non-polished silicon wafers shipped by the wafer manufacturers to the end-users.

The Silicon Manufacturers Group acts as an independent special interest group within the SEMI structure and is open to SEMI members involved in manufacturing polycrystalline silicon, monocrystalline silicon or silicon wafers (e.g., as cut, polished, epi, etc.). The purpose of the group is to facilitate collective efforts on issues related to the silicon industry including the development of market information and statistics about the silicon industry and the semiconductor market.

Security by design


November 13, 2015

Chowdary_Yanamadala-150x150By Chowdary Yanamadala, Senior Vice President of Business Development, ChaoLogix

The advent of Internet-connected devices, the so-called Internet of Things (IoT), offers myriad opportunities and significant risks. The pervasive collection and sharing of data by IoT devices constitutes the core value proposition for most IoT applications. However, it is our collective responsibility, as an industry, to secure the transport and storage of the data. Failing to properly secure the data risks turning the digital threat into a physical threat.  

Properly securing IoT systems requires layering security solutions. Data must be secured at both the network and hardware level. As a hardware example, let’s concentrate, on the embedded security implemented by semiconductor chips.

Authentication and encryption are the two main crypto functions utilized to ensure data security. With the mathematical security of the standardized algorithms (such as AES, ECDSA, SHA512, etc.) is intact, hackers often exploit the implementation defects to compromise the inherent security provided by the algorithms.

One of the most dangerous and immediate threats to data security is a category of attacks called Side Chanel Analysis attacks (SCA). SCA attacks exploit the power consumption signature during the execution of the crypto algorithms. This type of attack is called Differential Power Analysis (DPA). Another potent attack form of SCA is exploiting the Electromagnetic emanations that are occurring during the execution of the crypto algorithm – or Differential Electromagnetic Analysis attacks (DEMA).

Both DPA and DEMA attacks rely on the fact that sensitive data, such as secret keys, leaks via the power signature (or EM signature) during execution of the crypto algorithm.

DPA and DEMA attacks are especially dangerous, not only because of their effectiveness in exploiting security vulnerabilities but also due the low cost of the equipment required for the attack. An attacker can carry out DPA attacks against most security chips using equipment costing less than $2,000.

There are two fundamental ways to solve the threat of DPA and DEMA. One approach is to address the symptoms of the problem. This involves adding significant noise to the power signature in order to obfuscate the sensitive data leakage. This is an effective technique.  However, it is an ad-hoc and temporary measure against a potent threat to data security. Chip manufacturers can also apply this technique as a security patch, or afterthought, once  and architecture work is completed.

Another way (and arguably a much better way) to solve the threat of DPA is to address the problem at the source. The source of the threat derives from the leakage of sensitive data the form of power signature variations. The power signature captured during the crypto execution is dependent on the secret key that is processed during the crypto execution. This makes the power signature indicative of the secret key.

What if we address the problem by minimizing the relation between the power signature and the secret key that is used for crypto computation? Wouldn’t this offer a superior security? Doesn’t addressing the problem at the source provide more fundamental security? And arguably a more permanent security solution?

Data security experts call this Security By Design. It is obvious that solving a problem at the source is a fundamentally better approach than providing symptomatic relief to the problems. This is true in the case of data security as well. In order to achieve the solution (against the threat of DPA and DEMA) at the source, chip designers and architects need to build the security into the architecture.

Security needs to be a deliberate design specification and needs to be worked into the fabric of the design. Encouragingly, more and more chip designers are moving away from addressing security as an afterthought and embracing security by design.

As an industry, we design chips for performance, power, yield and testability. Now it is time to start designing for security. This is especially true for chips used in IoT applications. These chips tend to be small, have limited computational power and under tight cost constraints. It is, therefore, difficult, and in some cases impossible, to apply security patches as an afterthought. The sound approach is to start weaving security into the building blocks of these chips.

In sum, designing security into a chip is as much about methodology as it is about acquiring various technology and tools. As IoT applications expand and the corresponding demand for inherently secure chips grows, getting this methodology right will be a key to successful deployment of secure IoT systems.

Related data security articles: 

Security should not be hard to implement

ChaoLogix introduces ChaoSecure technology to boost semiconductor chip security

From laptops and televisions to smartphones and tablets, semiconductors have made advanced electronics possible. These types of devices are so pervasive, in fact, that Northwestern Engineering’s Matthew Grayson says we are living in the “Semiconductor Age.”

“You have all these great applications like computer chips, lasers, and camera imagers,” said Grayson, associate professor of electrical engineering and computer science in Northwestern’s McCormick School of Engineering. “There are so many applications for semiconductor materials, so it’s important that we can characterize these materials carefully and accurately. Non-uniform semiconductors lead to computer chips that fail, lasers that burn out, and imagers with dark spots.”

Grayson’s research team has created a new mathematical method that has made semiconductor characterization more efficient, more precise, and simpler. By flipping the magnetic field and repeating one measurement, the method can quantify whether or not electrical conductivity is uniform across the entire material – a quality required for high-performance semiconductors.

“Up until now, everyone would take separate pieces of the material, measure each piece, and compare differences to quantify non-uniformity,” Grayson said. “That means you need more time to make several different measurements and extra material dedicated for diagnostics. We have figured out how to measure a single piece of material in a magnetic field while flipping the polarity to deduce the average variation in the density of electrons across the sample.”

Remarkably, the contacts at the edge of the sample reveal information about the variations happening throughout the body of the sample.

Supported by funding from the Air Force’s Office of Scientific Research, Grayson’s research was published on October 28 online in the journal Physical Review Letters. Graduate student Wang Zhou is first author of the paper.

One reason semiconductors have so many applications is because researchers and manufacturers can control their properties. By adding impurities to the material, researchers can modulate the semiconductor’s electrical properties. The trick is making sure that the material is uniformly modulated so that every part of the material performs equally well. Grayson’s technique allows researchers and manufacturers to directly quantify such non-uniformities.

“When people see non-uniform behavior, sometimes they just throw out the material to find a better piece,” Grayson said. “With our information, you can find a piece of the material that’s more uniform and can still be used. Or you can use the information to figure out how to balance out the next sample.”

Grayson’s method can be applied to samples as large as a 12-inch wafer or as small as an exfoliated 10-micron flake, allowing researchers to profile the subtleties in a wide range of semiconductor samples. The method is especially useful for 2-D materials, such as graphene, which are too small for researchers to make several measurements across the surface.

Grayson has filed a patent on the method, and he hopes the new technique will find use in academic laboratories and industry.

“There are companies that mass produce semiconductors and need to know if the material is uniform before they start making individual computer chips,” Grayson said. “Our method will give them better feedback during sample preparation. We believe this is a fundamental breakthrough with broad impact.”

Hillsboro, Ore. — November 2, 2015 — FEI today announced the new Helios™ G4 DualBeam series, which offers the highest throughput ultra-thin TEM lamella preparation for leading-edge semiconductor manufacturing and failure analysis applications. The new DualBeam series, which includes FX and HX models, takes a significant leap forward in both technological capability and ease-of-use.

The new Phoenix focused ion beam (FIB) makes finer cuts with higher precision and simplifies the creation of ultra-thin (sub 10nm) lamella for transmission electron microscopy (TEM) imaging. The FX is a flexible system that delivers dramatically improved STEM resolution – down to sub-three Ångströms – and significantly shortens the time to data for failure analysis. Images can now be obtained within minutes of completing the lamella, rather than the hours or days required previously to finalize the images on a stand-alone S/TEM system. The HX model is geared specifically for high-throughput TEM lamella production. It features an automated QuickFlip holder that reduces sample preparation times.

“FEI is the first to market with a TEM sample preparation solution capable of making 7nm thick lamella, addressing the needs of our customers who are developing next-generation devices,” states Rob Krueger, vice president and general manager of FEI’s semiconductor business. “In addition, by offering the ability to achieve sub-three Ångström image resolution in a DualBeam, failure analysis labs can now dramatically cut ‘time to data’ without compromising image quality. And, by combining high-resolution imaging and sample preparation on one system, we have reduced the amount of valuable lab real estate required.”

Today, in conjunction with the 41st International Symposium for Testing and Failure Analysis (ISTFA), DCG Systems® announced the release of EBIRCH™, a new, unique technology for localizing shorts and other low-resistance faults that may reside in the interconnect structures or the polysilicon base layer of integrated circuits. Named for Electron Beam Induced Resistance Change, EBIRCH offers fault analysis (FA) engineers and yield experts the ability to detect and isolate low-resistance electrical faults without resorting to brute-force binary search approaches that rely on successive FIB* cuts. Its unparalleled ability to quickly isolate low-resistance faults enables EBIRCH to boost the success rate of physical failure analysis (PFA) imaging techniques to well above 90%, accelerating time-to-results and establishing the FA lab as a critical partner organization in solving yield and reliability problems.

“At foundries and IDM* fabs, the process has become more difficult to control using traditional inline measures,” said Mike Berkmyre, business unit manager of the Nanoprobing Group at DCG Systems. “More yield issues are remaining undetected until they show up at final test — and land on the desk of the FA lab manager. The FA engineers must be equipped to localize the fault and supply images of the root cause to process or yield engineers in a timely manner. The ability to quickly and reliably localize low-resistance faults was missing before we developed EBIRCH. With the introduction of EBIRCH, we are helping to solve an FA problem that has been growing in prevalence and importance with each new device node.”

Available on DCG’s current SEM*- based nanoprobing systems, EBIRCH offers the following capabilities:

  • Detects and isolates electrical faults with resistances from < 10 ohm to > 50 Mohm;
  • Finds faults at surface and several levels below concurrently, significantly accelerating the existing work flow; and
  • Can scan areas as large as 1mm by 1mm, and zoom in to areas as small as 50nm by 50nm, providing accurate and actionable fault localization within minutes.

To collect an EBIRCH image, the operator lands two nanoprobes on surface metal layers, straddling the suspected defect site. A bias is applied, and the electron beam rasters across the region of interest. As the e-beam interrogates the defect site, localized heating from the e-beam changes the resistance of the defect, thereby changing the current sensed by the nanoprobe. The EBIRCH map displays the change in current as a function of the e-beam position—typically showing a bright spot at the site of the resistance change. The simultaneously acquired SEM image, together with knowledge of the circuit layout, allows the engineer to determine the exact defect location. The depth at which the defect lies can be explored by optimizing the landing energy as a function of the EBIRCH signal.

Available exclusively on the flexProber™, nProber™ and nProber II™ nanoprobers from DCG Systems, EBIRCH is part of an integrated electron beam current (EBC) module that offers seamless switching from EBAC to EBIRCH, with no re-cabling needed.

November 2, 2015 — Tsinghua Unigroup Ltd., a Chinese government-owned chipmaker will make a $600 million investment in Powertech Technology of Taiwan, according to multiple reports. Powertech Technology, which specializes in chip packaging and testing, will hand over 25% of the company in exchange, after new shares are issued.

According to the Wall Street Journal, Powertech will use the funds to “help it expand its assembly capacity in Taiwan, develop advanced production processes and recruit talent. It would also become Tsinghua Unigroup’s major chip assembly and testing partner.”

Tsinghua is the largest chip design company in China, and earlier this year attempted to acquire Micron Technology with a $23 billion bid. That bid ultimately failed, but it hasn’t stopped Tsinghua from investing in other US companies in the industry, including Western Digital ($3.78 billion for 15%) and Hewlett-Packard’s data-networking business (51%, $2.3 billion).

This continues the unprecedented consolidation that has come to the semiconductor industry in 2015. A trend that has shown no signs of slowing as we enter 2016.

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To help readers follow this constantly changing situation, Solid State Technology is keeping a running scorecard of all the significant transactions in the semiconductor market here: Historic era of consolidation for chipmakers.

 

 

San Jose, Calif., October 29, 2015 — Ziptronix, Inc., a wholly owned subsidiary of Tessera Technologies, Inc. and a leader in low temperature wafer bonding technology, today announced it has entered into a development agreement with Fraunhofer IZM-ASSID. The companies will work together to integrate Ziptronix Direct Bond Interconnect (DBI®) technology into Fraunhofer’s state of the art 300mm wafer production line and demonstrate DBI as the industry’s finest pitch, thinnest and lowest total cost-of-ownership 3D integration solution.

Increasingly, the industry is looking toward 2.5D and 3D-IC solutions as the most cost effective and efficient means of delivering the next generation of high performance computing and consumer electronic products. However, conventional approaches rely heavily on thru silicon vias (TSVs), micro-bumping and underfill, which can limit interconnect density, performance, form factor and cost-effectiveness. Ziptronix DBI technology can address these limitations and accelerate the adoption of game-changing 2.5D and 3D-IC architectures.

“Although great progress has been made, the industry continues to face challenges associated with the manufacturability, scalability and cost of current 2.5D and 3D-IC solutions. Ziptronix’s DBI technology is an enabling platform that can readily address many of these challenges,” said Juergen Wolf, Head of Fraunhofer IZM-ASSID. “We at Fraunhofer are very excited to work with Ziptronix to demonstrate the benefits of DBI technology to our customers on our 300mm wafer production line.”

“DBI is the industry’s highest density, highest performance, lowest profile and lowest cost-of-ownership 3D integration platform,” said Paul Enquist, Vice President of 3D R&D at Ziptronix. “It will revolutionize the world’s most challenging 3D-IC structures and devices, and we look forward to working closely with Fraunhofer to demonstrate this enabling capability to customers around the world.”

“The acquisition of Ziptronix, and the subsequent integration of its team and technology into Tessera, has allowed us to significantly expand the 2.5D and 3D value that we bring to our customers, and the response has been incredibly positive,” said Craig Mitchell, President of Invensas. “This development agreement with Fraunhofer is an important step in the continuing development of the DBI technology as we grow our 2.5D and 3D product offerings.”