Category Archives: Wafer Level Packaging

Entegris, Inc., a producer of yield-enhancing materials and solutions for highly advanced manufacturing environments, has expanded its wafer shipper family of products with the SmartStack (R) 300 mm Contactless Horizontal Wafer Shipper (HWS). The SmartStack 300 mm is the industry’s first contactless horizontal wafer shipper capable of holding a full lot of 25 wafers, almost twice the capacity of competitive wafer shippers. Entegris’ design departs from traditional interleaf inserts and foam cushions by using a perimeter support ring to contain wafers inside. The wafers are positioned so that they move in unison, preventing wafer-to-wafer contact and potential damage from impact.

“We designed an ideal solution for shipping and storing 25-lens bumped or thin wafers that offers improved safety over conventional wafer shippers,” said Entegris Product Marketing Manager, Doug Moser. “By placing the wafers on rings and removing the interleaf inserts and foam cushions, the wafers are protected from stains, imprints and scratches typically caused by these inserts. Additionally, the new design accommodates 25 wafers in one shipper, thereby increasing shipping density and lowering shipping cost 50% or more, compared with a conventional FOSB.”

The SmartStack 300 mm is designed to accommodate wafers of varied thickness (150 µm to 1100 µm), for a variety of applications including 3D, 2.5D, SoC, MEMS, LED and power semiconductors. The new design is also available in the 150 mm and 200 mm size. The automation-compatible features of the 300 mm HWS enable ease-of-use and limit manual intervention.

The 2015 market for dielectric precursors is expected to total $230M, of which over $45M is attributed to low-κ dielectrics, according to a new report from Techcet Group, “2015 Techcet Critical Materials Report on Advanced Insulating Dielectric Precursors.” The outlook is for 8.5% growth to ~$250M in 2016, continuing to almost $300M by 2020 for a 5-year CAGR of 5.1%.

With 3D structures displacing planar 2D transistors in leading edge nodes, the call for new dielectric materials and deposition processes has continued to fragment. Device films require extreme conformality, precision uniformity in atomic layer thicknesses, and aspect ratio fills of 70:1 or more at deposition temperatures below 200°C. Masking films and sacrificial layers have to meet exacting specifications for removal selectivity, edge definition and etch resistance.

DialectDataTechcet’s 2015 Dielectric Precursors Report provides strategic information on the dielectrics market including revenue by precursor type/application and market share ranking. It also includes critical information used to ensure business continuity and support category management of the CVD, ALD, and SOD dielectric markets and their supply chains. In addition to business and technology trends, supply chain and geopolitical issues that impact dielectric precursors are also discussed in this year’s report.

Altatech, a specialty equipment manufacturer for mature and advanced materials deposition and defect inspection, announced today the expansion of its Eclipse series with a new, high-speed inspection system dedicated to ultra-thin, transparent and bonded substrates inspection for 3D applications in power, MEMS, and mobile technologies. The Eclipse TS represents a unique high-reliability and easy-to-implement inspection system solution ready for mass production, in response to the demand for these advanced substrates being driven by the rapidly growing markets in automotive, industrial power and mobile electronics. The Eclipse TS has been qualified for volume manufacturing at a leading-edge semiconductor manufacturer.

“We have built a tool based on a strong IP portfolio with a unique capability to inspect the front side, back side and edge of very thin wafers. This is a cost-effective solution with very good throughput. It places Altatech in a leading position within a very large market opportunity,” said Jean-Luc Delcarri, general manager of Soitec’s Altatech Division.

The Eclipse TS is a high-speed inspection system for measuring very thin and stacked wafers down to 50 microns, Taiko rings, stacked substrates, and silicon-on-glass wafers. The system can conduct front-side, back-side and edge inspection in one pass with no back-side contact and accommodate very high bow and wrap wafers up to 6 mm. In today’s 3D technologies, substrates undergo grinding, stacking and gluing. The Eclipse system is able to monitor these processes. Inspection occurs without any contact on the active surface with a throughout of more than 90 wafers per hour for 300-mm substrates.

Compliant with the latest automation standards, the Eclipse TS offers comprehensive reporting for defects classification and yield maps.

The full Altatech Eclipse series of advanced metrology and holistic inspection systems ensure wafer-surface and edge quality by detecting, counting, and binning defects during the wafer manufacturing process as well as performing continuous outgoing wafer-quality inspection. Proprietary Eclipse sub-modules are designed to detect particles and defects of interest on the front surface and wafer edge of patterned or unpatterned wafers.

Showa Denko (SDK) has developed a new grade of silicon carbide (SiC) epitaxial wafers for power devices with very low defect density. SDK will this month start commercial shipments of the new grade, in two different sizes of four inches (100mm) and six inches (150mm) in diameter, under the trade name of “High-Grade Epi (“HGE”)”.

When compared with the mainstream silicon-based semiconductors, SiC-based power devices can operate under high-temperature, high-voltage, and high-current conditions, while substantially reducing energy loss. These features enable the production of smaller, lighter, and more energy-efficient next-generation power control modules. SiC power devices are already used as power sources of servers for data centers, distributed power supply systems for new energies, and in subway railcars. Demand is expected to grow further as plans have been announced to use SiC power devices in vehicles. Furthermore, efforts are under way to develop SiC-based ultra-high-voltage (10KV class) devices for use in power generation/transmission systems.

Power modules for high-voltage, high-current applications mainly contain devices with the structure of SBD (Schottky barrier diode) and transistors with the structure of MOSFET (metal-oxide-semiconductor field-effect transistor). While SiC is increasingly used in SBD, it is difficult to use SiC in MOSFET. As MOSFET’s oxide film, formed on the surface of an epitaxial wafer, is used in device operations, finer surface defect (SD) and various types of crystal defects, including basal plane dislocation (BPD), considerably affect the yield and product quality.

For automotive applications, meanwhile, large chips measuring around 10mm square are made out of epitaxial wafers. This is because one device needs to handle a current as high as 100A. To prevent deterioration in the production yield of such large chips, the defect density of epitaxial wafers should be controlled within 0.1/cm2.

In the new product, HGE, SDK has succeeded in controlling the number of SD within 0.1/cm2 (one-third the current level of SDK’s conventional product) and of BPD within 0.1/cm2 (one-hundredth or less compared with conventional product). As a result, it is now possible to almost eliminate device defects attributable to BPD (assuming the use of a 10mm square chip). SDK believes that the new product will greatly contribute to the commercialization and market expansion of “full SiC” power modules that combine SiC-SBD and SiC-MOSFET.

Using the HGE technology, SDK has also succeeded in producing SiC epitaxial wafers with film thickness of 100um or more, having low levels of defect density and good uniformity. SDK will start commercial shipments of these SiC epitaxial wafers for use in power generation/transmission systems. The size of the market for SiC epitaxial wafers for power devices is expected to reach 100 billion yen in 2025. SDK will continue its efforts to meet requirements for higher quality, contributing toward expansion of the market.

IEEE S3S 2015 could be the turning point for monolithic 3D. From October 4-7 we will have the option to get a short course, invited and selected presentations from a broad range of the industry representatives. They include major vendors such as Qualcomm, Global Foundries, and Applied Materials; leading research organization like CEA Leti, Taiwan National Applied Research Labs, German IMS Chips, and NASA; leading Universities like Berkeley and Stanford; and start-ups like SiGen and MonolithIC 3D.

In its tutorial session, Qualcomm will explain why it is investing in and promoting 3D VLSI (3DV) as an alternative scaling technology, as is illustrated by the following two slides:

GameChang2-0_Fig1GameChange2-0_Fig2

Yet many people still have doubts, as reflected by the title of the panel we were invited to participate in — “Monolithic 3D: Will it Happen and if so…” — at the IEEE 3D-Test Workshop on October 9, 2015.

The doubts likely relate to the technology challenge that is illustrated in the following slide:

GameChange2-0_Fig3

The question, in short, is how we can add more transistors monolithically interconnected to the underlying transistors without exceeding the thermal budget for the underlying transistors and interconnect.

The current paths to monolithic 3D involve major changes to the front line process flow and require the development of a new logic transistors. The big concern is that leading edge vendors are too busy with dimensional scaling and if anything else could be done it seems that FD-SOI would be it, while trailing edge fabs are, in most cases, avoiding any major transistor process development. The recent failure of Suvolta could be an indication of this reality.

Hence the importance of Game-Changing 2.0, a major technology innovation to be unveiled on Wednesday by MonolithIC 3D in a paper titled: “Modified ELTRAN (R) – A Game Changer for Monolithic 3D”. The paper will present a novel use of the ELTRAN process developed by Canon about 20 years ago, primarily for SOI applications. Using ELTRAN (Epi. Layer Transfer) techniques, a substrate could be prepared enabling any fab to simply integrate a monolithic 3D device without the need to change its current front-line fab process. This flow is further simplified and could be integrated with the monolithic 3D flow introduced last year that leverages the emerging precision bonders, such as EVG’s Gemini (R) XT FB. This flow provides a natural path for product innovation and an unparalleled competitive edge to its adopters. In addition, this game-changing breakthrough offers a very cost-competitive flow. The following chart illustrates the original use of ELTRAN process for the fabrication of SOI wafers:

GameChange2-0_Fig4

In the “Invited Talks on M3DI” at the conference we will have an opportunity to learn from the inventor of the ELTRAN process, Dr. Takao Yonehara, currently with Applied Materials, in his “Epitaxial Layer Transfer Technology and Application” talk. Prior to Applied Materials, Dr. Yonehara worked with Solexel, a Silicon Valley startup, to deploy the ELTRAN process for low cost solar cell fabrication. Yonehara’s talk will be followed by Prof. Joachin Burghartz of Institute for Microelectronics in Stuttgart, discussing “Ultra-thin Chips for Flexible Electronics and 3D ICs” that uses a variation of such flow in small scale production.

The semiconductor industry is bifurcating these days into a segment that follows aggressive scaling for few super-value applications supported by very few vendors, while the bulk of the industry is enhancing old fabs targeting mainstream applications and the emerging IoT opportunities. Further enhancing these older fabs with monolithic 3D offers a most effective return on investment. Game-Changing 2.0 means that without a need for major process R&D efforts or new equipment, the path for 3D scaling is now open with enormous advantages for IoT. Accordingly, my answer to the original question above is summarized by the title of our invited talk at the IEEE 3D-Test Workshop: “Monolithic 3D is Already Here — the 3D NAND — and Now it would be Easy to Adapt it for Logic.”

In addition the other division, SOI and SubVt provide good complementing technology updates for the power-performance objectives that are so important for these emerging markets.

So, come to the S3S and enjoy unique key technologies update with the great wine and country pleasures of Sonoma Valley.

Novati Technologies Inc., a global nanotechnology development center, today announced the availability of the industry’s most advanced Integrated Sensor Platform, placing a wide variety of sensors onto multi-layer stacks of wafers in order to consume less power and perform significantly faster while reducing overall footprint. Already proven for customer devices at Novati’s commercial development and manufacturing center, the platform paves the way for stacking single or multiple sensors with a broad selection of popular–as well as emerging–substrate materials, enabling new high-end applications for markets that include medical, semiconductors, photonics, security, and aerospace.

Demonstrating a version of this capability for high-performance computing, Novati last month jointly announced with Tezzaron Semiconductor the industry’s first eight-layer 3D IC wafer stack containing active logic, which controls the memory layers. The transistor and interconnect densities per cubic millimeter were far higher than achievable with 2D 14nm silicon fabrication, representing the densest 3D IC ever reported. Not limited to the high-end markets served by that achievement, Novati’s Integrated Sensor Platform also offers great promise as an enabler for the Internet of Things (IoT).

“Energy harvesting is one of the important capabilities needed for the broad set of markets that aim to utilize the integration of sensing and processing,” said Tony Massimini, Chief of Technology for Semico Research. “Novati’s platform offers technology for integrating this energy harvesting ecosystem that includes energy generator, converters, power management, MCUs, energy storage and connectivity for small, wireless autonomous devices, like those used in wearable electronics and wireless sensor networks.”

For the past three years, Novati has demonstrated wafer-to-wafer integration of up to eight wafers, as well as custom sensors integrated directly onto mainstream CMOS architectures. With 3D manufacturing options available on both 200mm and 300mm lines, Novati offers circuit designers an unprecedented degree of freedom to architect the smart sensors of the future.

“While the ability to create multi-chip devices has been around for decades, Novati’s innovative sensor platform can accelerate the Internet of Things by expanding the ways for devices to connect and interact with all types of environments,” said David Anderson, President and CEO of Novati. “Using this platform, the world can integrate novel sensor functionality to virtually any circuitry, including digital logic, analog, mixed signal and memory–and stacking multiple sensors will soon follow. This opens a new, unlimited landscape for designers to significantly improve functionality while reducing costs and time to market.”

As an example of Novati’s substrate integration, their nanomanufacturing site bonded Tezzaron’s wafers directly, wafer-to-wafer, producing devices that can be thinned and finished to the same thickness as conventional 2D dies. The result was excellent electrical, thermal and mechanical performance. Novati’s capability to integrate sensors with such a stacked platform already has led to novel, proprietary product development for several customers.

Building on its ability to provide the world’s most advanced Integrated Sensor Platform and other innovations for the microelectronics markets, Novati intends to open its next office in Europe, where site selection is underway. In order to jointly plan new devices using novel materials that enable micro- and nanoscale functions and analyses, the company will be meeting with companies from around the globe during its participation at SEMICON Europa electronics conference in Dresden for the week of October 6.

“Europe has always been an important market for us and we are excited to continue expansion in this area,” said Julian Searle, Director of Account Management for Novati. “As the innovation initiatives in Europe continue to progress, Novati’s commercialization services and solutions are often the first call for technical pioneers that need to transform great ideas into great products.”

D2S (R), a supplier of GPU-enabled software for semiconductor manufacturing, today announced that it has partnered with Advantest, the world’s largest supplier of semiconductor Automatic Test Equipment, to integrate D2S’ Wafer Plane Analysis engine into Advantest’s Mask MVM-SEM (Multi Vision Metrology Scanning Electron Microscope) systems. This new capability enables fast and highly repeatable CD metrology for complex photomask shapes, including those created by inverse lithography technology (ILT), which enables photomask manufacturers to quickly, accurately and cost-effectively identify mask-level CD uniformity (CDU) issues that will impact the wafer during subsequent lithography processing in the wafer fab.

“We’re pleased to be working with D2S on developing a joint solution to improve mask CDU analysis, which results in a better quality mask for our customers,” stated Takayuki Nakamura, Executive Officer, General Manager of Nanotechnology Business Division, Advantest. “Combining D2S’ expertise in GPU-accelerated simulation technologies with our leading-edge CD-SEM tools–such as our new E3640–allows us to provide a cost-effective platform for extremely fast lithography simulation.”

Advanced photomasks are increasingly adopting non-orthogonal patterns and complex shapes, such as curvilinear mask patterns, due to the need for aggressive optical proximity correction (OPC) and ILT to enable production of leading-edge semiconductor devices with ever-smaller feature sizes. As these mask patterns become more complex, conventional CD metrology that measures CDs on straight lines/spaces no longer works since most mask patterns do not have uniform CDs after OPC and ILT correction. In addition, the number of mask defect issues flagged during mask inspection increases. However, not all of these mask issues will actually result in yield problems on the wafer. As a result, this increases the need for photomask manufacturers to understand the wafer-level impact of mask-level issues.

Wafer plane (aerial) analysis has emerged as a solution for identifying mask-level CDU issues that will impact the wafer. However, optical-based wafer plane analysis solutions are expensive, can be slow to implement, and have difficulty providing repeatable results. Mask manufacturers need a new wafer plane analysis solution that is less expensive, faster, and highly repeatable without requiring new equipment or additions to the mask inspection process.

The D2S Wafer Plane Analysis Engine provides aerial simulation of mask contours extracted by the Advantest MVM-SEM for today’s complex mask patterns, including ILT shapes for memory and logic. It is fully integrated into the Advantest CD-SEM system, which enables mask shops to access the benefits of GPU-accelerated wafer plane analysis without adding costly iterations with a standalone optical system.

“GPU acceleration is a powerful tool for enabling fast and accurate aerial simulation of complex mask patterns. It is particularly advantageous on curvilinear mask contours, which are increasingly being populated in today’s leading-edge photomasks,” stated Dr. Linyong (Leo) Pang, chief product officer and executive vice president of D2S. “The new Wafer Plane Analysis Engine from D2S provides wafer plane analysis capability within seconds. Combining our capability with Advantest’s SEM solutions gives their customers a powerful solution for identifying which mask features truly have a CDU problem on the wafer in order to enable swift and cost-effective correction. It can also be used for mask post-inspection defect review to enable fast dispositioning of defects based on their simulated printability. “

Rudolph Technologies, Inc. announced today that it has purchased Stella Alliance, LLC, a Massachusetts-based semiconductor inspection technology intellectual property (IP) portfolio company. Stella Alliance’s patented illumination, auto-focus, and image acquisition technology significantly enhances the ability to identify certain critical defects not visible with current techniques. With this acquisition, Rudolph expects to add a next-generation, high-resolution inspection system to its portfolio of solutions in the second quarter of 2016. Additionally, the acquired technology is able to handle large rectangular substrates, extending Rudolph’s inspection portfolio footprint into growing unserved segments of microelectronic device manufacturing.

Paul McLaughlin, Rudolph’s chairman and chief executive officer, stated, “We expect the addition of this patented technology to bring a competitive advantage to our customers by addressing current inspection limitations, while helping Rudolph maintain the dominant market share in the back-end inspection arena.”

The technology was developed to overcome the challenges of detecting residue-related defects that traditional technologies can miss. These defects can have a significant impact on the interconnect quality, such as incomplete etch of bond or bump pads, faint copper bridging and stringers at the bottom of vias and high aspect ratio trenches in fan-out wafer level packaging (FOWLP), wafer-level chip scale packaging (WLCSP) and embedded die applications.

In addition, the technology provides the high resolution needed to inspect highly warped rectangular panels (larger than 500mm). This complements Rudolph’s JetStep (R) S line of steppers, which are panel-ready today. With this technology, Rudolph will offer a more comprehensive panel solution, which involves printing, inspecting and yield analysis, to quickly ramp lines and maintain high productivity.

“This new technology helps Rudolph provide configurable systems to meet current and future challenges faced by our customers,” said Mike Goodrich, vice president and general manager of Rudolph’s Inspection Business Unit. “As interconnect technology becomes increasingly important in back-end 3D and 2.5D applications, we anticipate this inspection technique to be a key component for our customers’ process control strategies.”

The company does not expect the transaction to have an impact on the results of operations for the 2015 third quarter. Terms of the transaction were not disclosed.

 

The official Call for Papers has been issued for the 2016 Symposia on VLSI Technology and Circuits, to be held at the Hilton Hawaiian Village June 13-16, 2016 (Technology) and June 15-17, 2016 (Circuits). The deadline for paper submissions to both conferences is January 25, 2016. The late-news paper submissions deadline for the Symposia on VLSI Technology is March 24, 2016; there is no late-news submission for the Symposium on VLSI Circuits. Complete details for paper submission can be found online at: http://www.vlsisymposium.org/authors/

For the past 28 years, the combined annual Symposia on VLSI Technology and Circuits has provided an opportunity for the world’s top device technologists, circuit and system designers to engage in an open exchange of leading edge ideas at the world’s premier mid-year conference for microelectronics technology. Held together since 1987, the Symposia on VLSI Technology and Circuits have alternated each year between sites in the US and Japan, enabling attendees to learn about new directions in the development of VLSI technology & circuit design through the industry’s leading research and development presentations.

The comprehensive technical programs at the two Symposia are augmented with short courses, invited speakers and several evening panel sessions. Since 2012, the Symposia have presented joint focus sessions that include invited and contributed papers on topics of mutual interest to both technology and circuit attendees.

The Symposium on VLSI Technology seeks technical innovation and advances in all aspects of IC technology, as well as the emerging IoT (Internet of Things) field, including:

  • IoT systems & technologies, including ultra-low power, heterogeneous integration, sensors, connectivity, power management, digital/analog, microcontrollers and application processors
  • Stand-alone & embedded memories, including DRAM, SRAM, non-volatile and emerging memory technologies
  • CMOS Technology, microprocessors & SoCs, including scaling, VLSI manufacturing concepts and yield optimization
  • RF / analog  /digital technologies for mixed-signal SoC, RF front end; analog, mixed-signal I/O, high voltage, imaging, MEMS, integrated sensors
  • Process & material technologies, including advanced transistor process and architecture, modeling and reliability; alternate channel; advanced lithography, high-density patterning; SOI and III-V technologies, photonics, local interconnects and Cu/optical interconnect scaling
  • Packaging technologies & System-in-Package (SiP)
  • Photonics Technology & “Beyond CMOS” devices 

The Symposium on VLSI Circuits seeks original papers showcasing technical innovations and advances in the following areas:

  • Digital circuits and processor techniques for standalone and embedded processors
  • Memory circuits, architectures & interfaces for volatile and non-volatile memories, including emerging memory technologies
  • Clock generation and distribution for high-frequency digital and mixed-signal applications
  • Analog and mixed-signal circuits, including amplifiers, filters and data converters
  • Wireline receivers & transmitters, including circuits for inter-chip and long-reach applications
  • Wireless receivers & transmitters, including circuits for WAN, LAN, PAN, BAN, inter-chip and mm-wave applications
  • Power management circuits, including battery management circuits, voltage regulators, energy harvesting circuits
  • Application-oriented circuits & VLSI systems, imagers, displays, and sensors for biomedical and healthcare applications

Joint technology and circuits focus sessions feature invited and contributed papers highlighting innovations and advances in materials, processes, devices, integration, reliability and modeling in the areas of advanced memories, 3D integration, and the impact of technology scaling on advanced circuit design. Submissions are strongly encouraged in the following areas of joint interest:

  • Design in scaled technologies: scaling of digital, memory, analog and mixed-signal circuits in advanced CMOS processes
  • Design enablement: design for manufacturing, process/design co-optimization, on-die monitoring of variability and reliability
  • Embedded memory technology & design: SRAM, DRAM, Flash, PCRAM, RRAM, MRAM and NVRAM memory technologies
  • 3D & heterogeneous integration: power and thermal management; inter-chip communications, SIP architectures and systems

Papers sought for “big integration”

Authors are encouraged to submit papers that showcase innovations that extend beyond single ICs and into the module, including focus areas in the Internet of Things (IoT), industrial electronics, “big data” management, biomedical applications, robotics and smart cars. These topics will be featured in focus sessions as part of the program.

Best Student Paper Award

Awards for best student paper at each Symposia will be chosen, based on the quality of the papers and presentations. The recipients will receive a financial award, travel cost support and a certificate at the opening session of the 2017 Symposium. For a paper to be reviewed for this award, the author must be enrolled as a full-time student at the time of submission, must be the lead author and presenter of the paper, and must indicate on the web submission form that the paper is a student paper.

The Full Service Foundry division of ams AG, a leading provider of high performance analog ICs and sensors, today announced a further expansion of its industry-leading 0.35µm High-Voltage CMOS specialty process platform. The advanced “H35” process provided by the High-Voltage process expert ams now includes a set of truly voltage scalable transistors offering significant area and performance improvements.

The new voltage scalable High-Voltage NMOS and PMOS transistor devices are optimized for various drain-source voltage levels (VDS) from 20V to 100V and provide significant lower on-resistance thus resulting in area savings. Using an optimized 30V NMOS transistor in power management applications instead of a fixed 50V transistor results in an area saving of approximately 50%. A 60V optimized NMOS device results in 22% less area when compared to a standard 120V NMOS transistor. Foundry customers developing complex High-Voltage analog/mixed-signal applications such as large driver and switching ICs instantly benefit from more dies per wafer.

The area optimized devices are ideally suited for a wide range of applications such as MEMS drivers, motor drivers, switches and power management ICs used in automotive, medical and industrial products. ams’ Full Service Foundry division is among first foundries worldwide offering true voltage scalable transistors to its foundry customers. Being fully automotive (ISO/TS 16949) and medical (ISO 13485) certified, ams supports highest quality requirements from its customers.

“Being among first foundries worldwide offering true voltage scalable devices, proofs ams’ expertise in developing specialty High-Voltage CMOS processes and providing excellent manufacturing services. ams’ foundry team is looking forward to teaming up with product developers who are creating advanced High-Voltage products”, said Markus Wuchse, general manager of ams’ Full Service Foundry division. “Our hitkit, the ams benchmark Process Design Kit as well as our High-Voltage process expertise enable our partners to optimize their HV integrated circuits towards area and on-resistance, which immediately results in more dies per wafer.”

This latest High-Voltage process extension is an add-on to the company’s ”More Than Silicon” portfolio, under which ams provides a package of technology modules, intellectual property, cell libraries, engineering consultancy and services to help customers successfully develop advanced analog and mixed-signal circuit designs based on its specialty technologies.