Category Archives: Wafer Level Packaging

Process Watch: Risky business


September 18, 2015

By Douglas G. Sutherland and David W. Price

Authors’ Note: This is the ninth in a series of 10 installments that explore certain fundamental truths about process control—defect inspection and metrology—for the semiconductor industry. Each article introduces one of the 10 fundamental truths and highlights its implications. Within this paper we will use the term inspection to imply either defect inspection or a parametric measurement such as film thickness or critical dimension (CD).

Previous installments have discussed many aspects of process control from general concepts to specific issues related to risk management (see below for links to previous Process Watch articles). In this article we will focus on strategies for managing risk associated with the most difficult steps in the process.

The ninth fundamental truth of process control for the semiconductor IC industry is:

High-Stakes Problems Require a Layered Process Control Strategy

In the IC manufacturing process there are a bewildering number of things that can go wrong and there is a tremendous amount of money at risk. As the margins of error steadily decrease with each new design node, the number of parameters that can wreak havoc on the process continues to rise. The increasing complexity of multiple patterning, pitch splitting and other advanced patterning techniques does nothing to mitigate this problem.

This increased process complexity drives the need for new process control strategies. For example, higher order overlay corrections that were largely unheard of above 45nm are now considered mandatory at 2Xnm and below. Similarly, wafer topography, something that historically was only measured during the manufacture of bare wafers, is now becoming a requirement in IC fabs to accommodate the shallower depth of focus in today’s scanners. For the same reasons, wafer backside and edge inspection are also becoming common practices. The difficulty of some process steps necessitates that they have more than just a single line of defense.

Figure 1 below shows the severity of a potential problem increasing in the horizontal direction and the probability of that problem actually occurring increasing in the vertical direction. In this figure the term “risk” can be thought of as the product of these two attributes – the amount of material impacted (severity) multiplied by the probability of it happening. The severity could increase for a number of reasons: the next inspection point could be many steps downstream from the current step, the process tools at the current step may have very high throughput so that by the time the problem is identified many lots have been exposed to it, or both.

Figure 1. Risk exposure chart with higher severity to the right and higher probability to the top. The problems that require a layered approach to risk management are those in the upper right hand corner where the probability of having a problem is high and the amount of material exposed to that problem is large.

Figure 1. Risk exposure chart with higher severity to the right and higher probability to the top. The problems that require a layered approach to risk management are those in the upper right hand corner where the probability of having a problem is high and the amount of material exposed to that problem is large.

Clearly the safest place to operate is in the lower left corner where both probability and severity are low. However, for process steps that are inherently closer to the upper right hand corner of the chart—high probability and high severity—it often makes sense to have a layered approach to process control in which there is a well thought out back-up plan if the problem is not immediately identified with the first inspection step. Sometimes there are aspects of the problem that are easier to detect later in the process than immediately after the problem step.

Consider the case of forming the first metal layer that wires together the individual transistors. This can be particularly difficult for a number of reasons. The CDs and pitches are aggressive—often at design rules similar to the gate layer. Also, the opportunity for built-in redundancy (multiple vias) is low because there is only one point of contact for each of the transistor connections (source, drain and gate), so every connection has to work.

In such a case it makes sense to have multiple layers of protection, each of which has unique capabilities. For instance, you might perform macro inspection after the photo step to discover any gross defects in the lithography process. There should also be inspection steps after oxide etch, barrier deposition and copper CMP. Having multiple inspection steps ensures the quality of the process throughout the formation of this layer and also helps ensure that you catch problems that originate at one step but may not become apparent until later in the process.

Simply waiting to do a final inspection at copper CMP is usually not sufficient. Doing so will pick up problems in the CMP process but may not allow for distinguishing these from issues that may have originated at an earlier step. Only by inspecting the same wafer at multiple steps are you able to subtract out previous-layer defects and isolate the problem.

Having multiple inspection points has several benefits. It helps identify problems early in the process flow, which significantly reduces the amount of material exposed. A device with 50,000 wafer starts per month has about 1,600 wafer starts per day. Identifying a problem one day sooner can save millions of dollars (depending on the yield loss and wafer cost). Multiple inspection points also help diagnose where the problem occurred and expedite the recovery procedure. Over time, they provide more information about the process allowing for continuous improvement plans that can help reduce not only the severity but also the frequency of problems.

Previous Process Watches:

About the authors:

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Drs. Price and Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

Global semiconductor capital equipment manufacturer OEM Group announced today that it has launched its new Cintillio-S (TM) automated batch wet chemical processing system. This automated batch system integrates industrial automation with the Cintillio platform, which continues to be the leading system for both Acid and Solvent processing since its introduction in 2009. This next evolution provides automated wafer handling technology and replaces the SEMITOOL Spectrum and Magnum platforms which were acquired last year from Applied Materials.

“The Cintillio-S incorporates all of the excellent features of Cintillio and adds the advantages of industrial automation,” said Graham Pye, CPT Product Manager at OEM Group. “Using Cintillio as the base processing module and incorporating industrial automation on the front-end allows us to move away from the custom-design philosophy used in the Spectrum and Magnum platforms. The use of common electro-mechanical components for both the process and automation modules ensures supply chain continuity for end-users. In addition, the use of Cintillio process module ensures existing Spectrum and Magnum users have a seamless process transfer from these older platforms.”

With global demand for semiconductor devices increasing and the constant pressure to deliver those products at minimal cost, today’s manufacturers increasingly seek to maximize tool utilization. These firms—particularly those utilizing wafers at 200mm and above, or seeking to invest in technology to produce at this level—universally view automation as an essential element for increasing efficiency and process throughput as a means of meeting this objective.

“The main drivers for automation at 200mm and above is to reduce manual operator intervention and dependency”, states Paul Inman, CPT Business Development at OEM Group. “This provides ergonomic relief to operators, fulfills the automation requirements of SMIF and FOUP operations, and has the added advantage of automated wafer control. The Cintillio-S handling solution is well-suited for those manufacturers who require an automated wet processing mini-environment in a compact footprint, including power semiconductor, CMOS IC, Advanced Packaging, MEMS, and LED applications.”

Through higher productivity, automation, and advanced process control, the Cintillio-S platform provides effective Acid, Solvent, and Ozone process solutions for FEOL and BEOL manufacturing, as well as wafer-scale packaging, with low cost-of-ownership. By leveraging the advantages of the Cintillio G2 system—including flexible chemical layout, modern controller design and diagnostics, and efficient exhaust design and facility requirements—the Cintillio-S gives manufacturers the tool it needs to meet its production demands today and in the future.

 

Marking an industry first for emerging electronics devices, Semiconductor Research Corporation (SRC) today announced a significant expansion of its benchmarking research — a unique program that evaluates the relative capabilities of new and emerging computing devices.

SRC, the world’s leading university-research consortium for semiconductor technologies, is managing the initiative through its Nanoelectronics Research Initiative (SRC-NRI) and STARnet Research programs. The research will be led by the Georgia Institute of Technology’s Azad Naeemi, associate professor, Georgia Tech School of Electrical and Computer Engineering.

“Benchmarking guides university research funded through SRC — enabling concise communication of research outcomes, focusing researchers’ attention on key technical challenges and sparking invention,” said Tom Theis, executive director of SRC-NRI. “Professor Naeemi’s research is expected to take benchmarking of emerging devices to a new level of sophistication.”

Evaluating the performance of devices in representative “benchmark” circuits is a well-established engineering practice in the semiconductor industry. However, this new program is the first to develop a comparable methodology for evaluating the relative capabilities of emerging devices.

These emerging devices include, for example, transistor-like “steep slope” devices that can operate at very low voltage and, therefore, very low power, and non-volatile magnetic devices that combine the functions of logic and memory. The new devices operate by a variety of principles fundamentally different from those governing the operation of established silicon field-effect transistor technology.

In recent years, benchmarking of these devices has steadily increased in rigor. The Georgia Tech team — selected by a group of SRC member companies supporting the initiative including IBM, Intel Corporation, Micron Technology and Texas Instruments — will build on this foundation.

“This research will also enable selection of the most promising emerging devices for technology transfer to SRC member companies and for continued development in future SRC research programs,” said Gilroy Vandentop, executive director of STARnet Research.

Besides maintaining and improving the established benchmarking methodology, the Georgia Tech team is tasked with developing and evaluating benchmark circuits to better understand the potential of new devices for memory arrays, to explore and quantify the value of non-volatility and to measure the impact of various ways of implementing device-to-device connections. Perhaps most challenging, Prof. Naeemi will lead the development of a rigorous benchmarking methodology for non-Boolean (analog) computational circuits being explored for future applications such as artificial neural networks.

“Our team is chartered with maintaining and improving the established benchmarking methodology for emerging devices, evaluating the potential performance of the various SRC-NRI and STARnet devices in the established benchmark circuits,” said Naeemi. “We will incorporate additional device concepts as they emerge through ongoing research, and we will develop additional benchmark circuits to better understand the capabilities of these devices.”

The SRC benchmark program is a two-and-a-half year effort that funds research from July 1, 2015 through the close of 2017.

In 2014, the automotive sector significantly outperformed the overall market average for semiconductors. In fact, the automotive market overtook data processing to become the third largest end market for power semiconductor applications, according to IHS Inc., a global source of critical information and insight.

Based on information from the IHS Power Management Market Share and Supplier Analysis report, demand for semiconductors by the automotive industry was particularly strong in advanced driver assistance systems (ADAS) and infotainment systems. In the power management semiconductor market, power integrated circuits (ICs) grew much faster than traditional power discrete solutions. The automotive power IC category in 2015 is forecast to grow 8 percent, year over year, while discrete revenue is projected to remain flat during the same time period.

Fig 1

Fig 1

“One strategy that automakers are undertaking to control research and development costs is to develop shared designs, components, engineering, and production platforms, and using the same electronic control units (ECUs)  for many different platforms with the same features,” said Jonathan Liao, senior analyst of power semiconductors for IHS. “While over time modern cars have increased in size, suppliers prefer small and interchangeable electronic control units that can fit on various platforms, which help lower overall development costs, and expand the universe of target customers, for an improved return on investment.”

As a result of this approach, automotive power ICs are growing faster than discrete solutions. For example, Texas Instruments – the market leader in voltage regulators — controlled 8 percent of voltage regulators used by the automotive industry in 2011 and increased its voltage regulator revenues by 150 percent by the end of 2014. By comparison, Infineon — the leading automotive-market supplier of discrete power solutions — increased their power management revenues, at roughly half of Texas Instruments’ growth rate, during the same time period.

Growing demand for luxury features in non-luxury vehicles

Increased consumer demand has caused many luxury car features to find their way into the non-luxury car market, which is causing an increase in overall demand for power ICs. Adaptive cruise control, blind-spot monitoring, connected traffic updates, sophisticated infotainment systems with voice command and other advanced features are being integrated, as both options and upgrades, into mass-produced mid-range vehicles, like the Ford Fusion, which has a suggested price of $22,000. “Features that were originally designed for Mercedes-Benz, BMW, Lexus and other luxury cars have very quickly found their way into the non-luxury market,” Liao said

There are several key features that will encourage further power IC adoption, including Internet-connected cars, vehicle-to-vehicle (V2V) communications, autonomous cars, Apple’s CarPlay and Android Auto. For all of these features, application processing speed and software are critical components.

“It is crucial for the ECUs to gather, process and respond to information in real time, for the safety and convenience of the driver,” Liao said. “Sophisticated power management solutions for power-intensive multi-core processors, baseband chipsets and sensor arrays can be implemented much more easily with power ICs.”

All of these advanced features are expected help power ICs to grow faster than discrete solutions.

The overall trend of power ICs outperforming power discrete solutions in the automotive semiconductor sector is expected to continue. Switch regulators, low-dropout (LDO) regulators and power management integrated circuits (PMICs) are examples of fast-growing power IC components with better integration, efficiency and smaller footprints –especially for low voltage applications in automotive electronics.

SEMICON Taiwan 2015 opened today starting a three-day event drawing over 43,000 attendees from electronics manufacturing. Held 2-4 September, SEMICON Taiwan represents the huge Taiwan business potential with Taiwanese chipmakers and Outsourced Semiconductor Assembly and Test (OSAT) firms spending over $20 billion in the next two years on equipment and materials.

2015 is the 20th anniversary of SEMICON Taiwan and now draws more than 700 exhibitors and more than 43,000 attendees.  Over 500 will attend the SEMICON Taiwan Leadership Gala Dinner, one of the most important executive events for the high-tech industry in Taiwan.

SEMICON Taiwan features co-located events and technology theme pavilions focusing on IC design, MEMS, 3D-ICs, advanced packaging/testing, sustainable manufacturing, and secondary equipment.

Highlights of this year’s show include:

  • Executive Summit: With the theme “Conversation between Nobel Prize Laureate and Distinguished Leaders in Taiwan,” executives from Executive Yuan, Etron Technology, ASE Group, and NCTU will share their unique perspectives with Prof. Shuji Nakamura, 2014 Nobel Prize winner.
  • Market Trends Forum: Forum features speakers from Beijing Gaohua Securities, IDC Asia/Pacific, UBS Investment Bank, Sanford C. Bernstein, TechSearch, and SEMI, with moderation by TSMC.
  • CFO and Investor Summit: With the theme, “An Exciting Period of Growth and Mergers in the Semiconductor Industry,” the event features speakers from TSMC, DBS, National Tsing Hua University, imec, and Taiwan M&A and Private Equity Council, with moderation by EQUVO.
  • Memory Executive Summit: The Summit includes presenters from Everspin, imec, Inotera Memories, and ITRI.
  • SiP Global Summit 2015: With a strong focus on heterogeneous integration through System-in-a-Package (SiP) technology, the event features more than 20 industry leaders who will share their insights and solutions on 3D-IC, Through Silicon Via (TSV), 2.5D-IC with silicon interposer, and embedded substrate technologies. More than 500 industry professionals from around the world are expected to attend.
  • Advanced Packaging Technology Symposium: Presenters will cover market trends, product applications, and packaging/assembly solutions to advanced equipment and material development, and testing and reliability – covering the most advanced technology development directions for 3D-IC.
  • Sustainable Manufacturing Forum: Experts will address a wide variety of environment, health, safety (EHS) and sustainability topics that affect high-tech manufacturing.
  • Semiconductor Materials Forum: This is the newest forum — features topics including front-end materials for advanced semiconductor devises, advanced materials solutions for 10nm and beyond, challenges for local material manufacturers, and novel materials, and activities for advanced packaging.

For more information and online registration, visit the SEMICON Taiwan website: www.semicontaiwan.org

At the 65th IEEE ECTC, several companies presented advances in thermos-compression bonding.

BY PHIL GARROU, Contributing Editor

Jie Fu of Qualcomm discussed “Thermal Compression Bonding for Fine Pitch Solder Interconnects.” Mass reflow-based interconnects, using either solder bump or Cu-column on bond on lead are the typical low-cost flip chip assembly approaches used by industry. These interconnects face challenges related to shorting and non-wets at sub 100μm pitches.

Transitioning below 100μm pitch requires a new approach, such as thermos- compression flip chip (TCFC). While TCFC provides higher accuracy bonding and allows for use of smaller solder cap which enables tighter FC pitch, it also presents new challenges. The major challenges for TCFC bonding include lower throughput and control of non-conductive paste (NCP) voids.

Overall, bond head ramp rate, temperature uniformity, peak temperature and dwell time must be fine-tuned in tandem to compensate for manufacturing tolerances and to get the desired end of line solder joint structure. In addition, controlling the temp exposure for the NCP material before NCP cure is critical to enable a robust TCFC solder joint. Too much thermal exposure and the NCP begins to cure prior to solder melting, which can leading to NCP entrapment and unreliable TCFC solder joints. Laminate surface finish is also an important variable.

In a similar study Cho and co-workers at GlobalFoundries presented “Chip Package Interaction Analysis for 20-nm Technology with Thermo-Compression Bonding with Non-Conductive Paste.” Strong market demand for finer pitch interconnects to enable higher I/O counts in a smaller form factor is driving another transition from conventional MR bonding process to thermo-compression bonding using non-conductive paste (TC-NCP). FEA simulation results for TC-NCP vs mass reflow show that TCNCP has significantly reduced thermomechanical stress at the ULK level and the bump level.

Horst Clauberg of K&S discussed “High Productivity Thermo- compression Flip Chip Bonding.” There is tremendous effort by IDMs, OSATs, materials suppliers and equipment suppliers to bring thermos-compression bonding to commercial reality. The most significant technical challenges have for the most part been solved and limited commercial production is taking place. However, relatively low throughput and high equipment cost create adoption resistance, especially in the all-important consumer market.

Thermocompression bonding can be segmented into two different processes. The first process differentiation is whether the underfill is pre-applied before the semiconductor chip is mounted or not. Pre-applied underfill comes either as a film applied to the die or as a paste applied to the substrate. In both cases the underfill must not only create a void-free bond, but also provide flux to remove oxide on the solder caps. The alternative process is thermocompression – capillary underfill (TC-CUF) where the die is underfilled in the same way as standard flip chip, except that the underfill process is much more challenging because of the more narrow bondline of a typical thermocompression bonded device. In TC-CUF, flux can be applied either by dipping the die into flux before bonding, or applying flux to the substrate.

Doug Hiner in a joint presentation between Qualcomm and Amkor presented “Multi-Die Chip on Wafer Thermo-Compression Bonding Using Non-Conductive Film.” Non-conductive films have been in development as a replacement to the liquid preap- plied underfill materials used in fine pitch copper pillar assembly.

Several assembly methods are available for chip on wafer assembly including: (1) traditional chip attach with mass reflow (MR) and capillary underfill (CUF), (2) thermo-compression bonding (TCB) of copper pillar interconnects using noncon- ductive paste (NCP) underfill (TCB+NCP), and thermocom- pression bonding of copper pillar with non-conductive film (NCF) underfill (TCB+NCF).

The TCB+NCP process carries concerns with the underfill time on stage which prevents the dispensing of the NCP material across the wafer prior to the chip bonding process. This constraint effects process costs significantly. The TCB+NCF process to date have not met the cost/benefit needs of the industry. NCF assembly provides significant improve- ments in the design rules associated with die to package edge, die to die, and fillet size. The NCF process also resolves the time on stage concerns associated with the NCP process by laminating the NCF material to the bonded die instead of to the interposer or receiving wafer surface.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that the company is experiencing strong demand for its automated 300mm polymer adhesive wafer bonding systems. Over the past 12 months, the company’s order intake has doubled for these systems, including the EVG 560, GEMINI and EVG 850 TB/DB series of wafer bonders. This includes multiple system orders from leading foundries and outsourced semiconductor assembly and test (OSAT) providers headquartered in Asia. Much of the increase in demand is being fueled by advanced packaging applications, where manufacturers are ramping up production of CMOS image sensors as well as vertically stacked semiconductors incorporating 2.5D and 3D-IC through silicon via (TSV) interconnect technology.

According to market research and strategy consulting firm Yole Developpement, the equipment market for 3D-IC and wafer-level packaging (WLP) applications is expected to grow significantly, from $933 million in 2014 to $2.6 billion in 2019 (total revenue), at a compound annual growth rate of 19 percent over the next five years*. Adhesive wafer bonding plays a critical role in supporting these applications.

Automated adhesive wafer bonding enables high yields on stacked devices
Adhesive wafer bonding is a technique that uses an intermediate layer (typically a polymer) for bonding two substrates, which is an important process technology for advanced packaging applications. The main advantages of using this approach are low temperature processing, surface planarization and tolerance to wafer topography. For CMOS image sensors, polymer adhesive bonding provides a protective barrier between the surface of the image sensor and the glass cover wafer. For 3D-IC TSV applications, polymer adhesive bonding plays an important role in temporary bonding and debonding applications, where product wafers are temporarily mounted on carriers with the aid of organic adhesives to enable reliable thinning and backside processing.

For both CMOS image sensor and stacked memory/logic applications, fully automated wafer bonding solutions are essential to support manufacturers’ migration to larger (300mm) wafer substrates to lower their overall cost of production. For example, minimizing total thickness variation (TTV) of the adhesive layer after bonding is crucial in defining the final product thickness tolerance. This ultimately has an impact on enabling thinner wafers and devices, which in turn enableshigher interconnect densities and lower TSV integration costs. EVG’s automated wafer bonding systems provide superior control of TTV and other parameters through repeatable wafer-to-wafer processing and integrated inline metrology to monitor TTV throughout the bonding process. As a result, manufacturers are increasingly turning to EVG to support their automated wafer bonding needs.

“We’ve truly entered the era of 3D-ICs, with demand for TSV wafers rising on a number of fronts—from CMOS image sensors for smart phone cameras and automotive surround view imaging, to 3D stacked memory and memory-on-logic to support high-performance, high-bandwidth applications such as networking, gaming, data centers and mobile computing,” stated Hermann Waltl, executive sales and customer support director at EV Group. “Automated wafer bonding is a critical process for supporting the volume manufacturing needs of CMOS image sensor and semiconductor device makers addressing these applications. EVG has invested years in the development of wafer bonding technology to make it a critical value-add solution for the advanced packaging market. Our breadth of knowledge in wafer bonding equipment and processes—along with our strong network of supply chain partners—has positioned us well to anticipate future industry trends and develop new solutions that meet our customers’ emerging production requirements.”

Tessera Technologies, Inc. today announced the acquisition of Ziptronix, Inc. for $39 million in cash. The acquisition expands on Tessera’s existing advanced packaging capabilities by adding a low-temperature wafer bonding technology platform that will accelerate delivery of 2.5D and 3D-IC solutions to semiconductor industry customers.

Ziptronix’s patented ZiBond direct bonding and DBI hybrid bonding technologies deliver scalable, low total cost-of-ownership manufacturing solutions for 3D stacking. Ziptronix’s intellectual property has been licensed to Sony Corporation for volume production of CMOS image sensors – an estimated $8.3 billion market according to Gartner. Ziptronix’s technology is also relevant to next-generation stacked memory, 2.5D FPGAs, RF Front-End and MEMS devices, among other semiconductor applications. Inclusive of CMOS image sensors, Tessera expects the annual market size to which this technology applies to exceed $15 billion by 2019.

“With this acquisition we’re gaining best-in-class technology, along with exceptional people, know-how in the 3D-IC market and a significant patent portfolio,” stated Tom Lacey, CEO of Tessera. “With the escalating cost for each node of semiconductor lithography, it remains very clear to us that our R&D spend on semiconductor packaging will only become more important and valuable to our customers. Ziptronix has commercially licensed the ZiBond and DBI technologies and they stack up very well alongside our extensive portfolio of 2.5D and 3D intellectual property. I’m confident that aligning our respective capabilities with our development expertise will help create a multi-hundred million dollar revenue opportunity for Tessera over the next decade as the industry continues to shift toward 3D-IC architectures.”

“ZiBond and DBI bonding are enabling technologies that provide significant cost and performance benefits,” said Craig Mitchell, President of Invensas, a Tessera subsidiary. “There is a great opportunity to further develop these platforms with our technology partners, and we’re very excited about their market potential.”

Founded in 2000 as a venture-backed spinoff of RTI International, privately held Ziptronix is a pioneer in the development of low-temperature direct bonding technology for 3D integration. Ziptronix is headquartered in Raleigh, North Carolina.

Dan Donabedian, President and CEO of Ziptronix added, “We’ve taken our technology from concept to commercialization in the backside illuminated image sensor and RF markets. Joining the Tessera family of companies combines our efforts with a proven leader in technology development and licensing in the semiconductor industry. This is a great alignment of companies that can address rapidly expanding 2.5D and 3D-IC markets.”

The addition of the Ziptronix team will not change Tessera’s target operating expense structure. Tessera is making no adjustments to third quarter 2015 revenue or earnings per share guidance.

North America-based manufacturers of semiconductor equipment posted $1.59 billion in orders worldwide in July 2015 (three-month average basis) and a book-to-bill ratio of 1.02, according to the July EMDS Book-to-Bill Report published today by SEMI.  A book-to-bill of 1.02 means that $102 worth of orders were received for every $100 of product billed for the month.

SEMI reports that the three-month average of worldwide bookings in July 2015 was $1.59 billion. The bookings figure is 5.1 percent higher than the final June 2015 level of $1.52 billion, and is 12.5 percent higher than the July 2014 order level of $1.42 billion.

The three-month average of worldwide billings in July 2015 was $1.56 billion. The billings figure is 0.3 percent higher than the final June 2015 level of $1.55 billion, and is 18.2 percent higher than the July 2014 billings level of $1.32 billion.

“Year-to-date, the bookings and billings reported in the SEMI North American equipment book-to-bill report indicate a solid year for the industry,” said SEMI president and CEO Denny McGuirk. “The outlook for the remainder of the year is somewhat clouded, but we see investments in 3D NAND and advanced packaging as drivers.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill
February 2015 

$1,280.1

$1,313.7

1.03
March 2015 

$1,265.6

$1,392.7

1.10
April 2015 

$1,515.3

$1,573.7

1.04
May 2015 

$1,557.3

$1,546.2

0.99
June 2015 (final)

$1,554.9

$1,517.4

0.98
July 2015 (prelim)

$1,559.3

$1,594.3

1.02

Source: SEMI (www.semi.org), August 2015

MagnaChip Semiconductor Corporation, a Korea-based designer and manufacturer of analog and mixed-signal semiconductor products, announced the appointment of Gary Tanner to its Board of Directors. Mr. Tanner’s appointment became effective on August 17, 2015. Mr. Tanner’s appointment fills a vacancy on MagnaChip’s Board of Directors created as a result of the Board increasing the number of directors on the Board to eight directors from seven directors.

Mr. Tanner served as Executive Vice President and Chief Operations Officer of International Rectifier Corporation from January 2013 to July 2015. Mr. Tanner also served as a Director of STATS ChipPac from September 2012 to July 2015. Mr. Tanner previously served as Director, Chief Executive Officer and President of Zarlink Semiconductor, Inc. until it was acquired by Microsemi Corporation in October 2011. Before joining Zarlink in 2007, Mr. Tanner was Vice President of Operations of Legerity, Inc. from 2002 to 2007. During his tenure with Intel Corporation from 1993 to 2002, Mr. Tanner held various management positions managing multiple domestic and international locations. Prior to joining Intel in 1993, Mr. Tanner held various management roles in fab operations at National Semiconductor, Texas Instruments and NCR Corporation.

“We are delighted to appoint Gary Tanner to MagnaChip’s Board of Directors,” said Doug Norby, MagnaChip’s non-executive chairman of the board. “Gary’s global experience and expertise in the semiconductor industry will be a great asset and will enable him to become a valuable contributor to MagnaChip.”