Category Archives: Wafer Level Packaging

By Taylor Sholler, SEMI

With trade policy dominating headlines in recent weeks, all eyes were on Maui in the waning days of August as trade ministers from twelve nations convened for perhaps the final time to finalize the Trans-Pacific Partnership (TPP).  Such a pact between Pacific Rim economies would account for 40 percent of the world’s GDP.  However, last-minute hurdles on dairy, autos, and drug provisions proved to be the negotiators’ undoing and ministers left Hawaii with the promise of at least one more round of exhaustive deliberations in the fall.

Such is the pathway for a multilateral agreement like the TPP.  By all accounts, significant progress has been made but getting 12 countries to concur on a high-standard agreement to reduce both tariffs and non-tariff barriers has been arduous to say the least.  The business community remains optimistic nonetheless and will continue to support TPP conclusion— key for the U.S. SEM industries which export 80% of their products— later this year.

Conversely, a sector-specific trade agreement is a bit more straightforward and industry welcomed news just a week earlier that an agreement-in-principle was reached on the expansion of the Information Technology Agreement (ITA).  Originally agreed to in 1996, the ITA fosters free trade in tech and has sorely needed an update to account for the vast progress made through industrial innovation.  While this effort was not without its own obstacles, World Trade Organization (WTO) members came to an agreement in Geneva on July 24th to cut tariffs on more than 200 ICT products after more than three years of negotiations.

This deal between more than 50 nations is seen a major victory for the global economy and the semiconductor equipment and materials industries in particular. SEM-related items account of more than a dozen of the products on the expansion list, including machines and apparatus to manufacture boules, wafers, semiconductor devices and flat panel displays among other products of interest to SEMI members.

WTO trade ministers will now take the list back to their respective capitals for domestic consultations.  By November 1st, participating members must submit a draft schedule detailing their plans for national implementation.  The process should culminate during the WTO’s 10th Ministerial Conference in Nairobi in December 2015, with tariff elimination slated to begin July 2016.

The expanded agreement represents 97 percent of world trade in information technology products—an estimated $1.3 billion annual market.  However, the deal also contains a commitment to work to tackle non-tariff barriers in the IT sector, and to keep the list of products covered under review to determine whether further expansion may be needed to reflect future technological developments.

In what was already been a successful year for trade liberalization, negotiators should soon celebrate implementation of the largest WTO-driven tariff elimination deal in 19 years.  The process has breathed fresh life into the promise of sectoral trade pacts driven by market demand and targeted negotiations.  SEMI has worked closely with ITA negotiators throughout the process to ensure the inclusion of SEM items in the expanded list and this is something we hope to replicate in other market opening accords like the Environmental Goods Agreement as well.

The semiconductor supply chain is comprised of the most innovation and technologically advanced products in the world and trade agreements like the ITA play an exceedingly helpful role in the advancement of our industry.  WTO Director-General Roberto Azevedo and trade negotiators around the world should be commended for their persistence on this important expansion effort. SEMI will continue to support the great work happening in Geneva and elsewhere to remove barriers to trade and improve business operations for our members.

For a complete list of items included in the expanded ITA, please visit:  https://ustr.gov/sites/default/files/ITA-expansion-product-list-2015.pdf

For those with trade-specific questions or concerns, SEMI maintains a dedicated international policy staff, led by Jonathan Davis, Global Vice President of Advocacy ([email protected]).

The Semiconductor Industry Association (SIA) announced former Defense Secretary Leon Panetta will deliver the keynote address at the upcoming SIA Award Dinner, taking place on Thursday, Dec. 3 in San Jose, Calif. Mr. Panetta, who has also served as CIA director, White House chief of staff, director of the Office of Management and Budget (OMB), and as a member of Congress, will offer insight on how the strength of U.S. technology, and a vibrant U.S. semiconductor industry in particular, are critical to our country’s standing in the world and to our economy and national security.

“Leon Panetta is one of America’s most respected leaders and experts on foreign policy,” said John Neuffer, president and CEO, Semiconductor Industry Association. “The semiconductor industry is a global industry with global challenges. We must ensure smart government policies are in place here at home so our industry can remain strong, and we must work closely with counterparts overseas to ensure we can play on a level playing field in the global markets. Given Mr. Panetta’s extensive and diverse experiences on the domestic and international stages, we very much look forward to his keen perspectives on these matters as we welcome him as the keynote presenter at this year’s SIA Award Dinner.”

Mr. Panetta has dedicated much of his life to public service. He served as the 23rd defense secretary from July 2011 to February 2013. Before joining the Department of Defense, Mr. Panetta served as the director of the CIA from February 2009 to June 2011. Previously, he spent 10 years co-directing with his wife, Sylvia, the Leon & Sylvia Panetta Institute for Public Policy, based at California State University, Monterey Bay. The Institute is a nonpartisan, not-for-profit center that seeks to instill the virtues and values of public service in young men and women.

From July 1994 to January 1997, Mr. Panetta served as chief of staff to President Bill Clinton. Prior to that, he was director of OMB, a position that built on his years of work on the House Budget Committee. Mr. Panetta represented California’s 16th (now 17th) congressional district from 1977 to 1993, rising to House Budget Committee chairman during his final four years in Congress. He holds a Bachelor of Arts degree in political science and a law degree, both from Santa Clara University.

The SIA Award Dinner also will feature the presentation of the semiconductor industry’s highest honor, the Robert N. Noyce Award.

By Jeongdong Choe, PhD., TechInsights

A few years ago, some of the semiconductor process and device analysts thought 2D planar NAND Flash would soon be coming to an end due to the scaling limits, especially around the 20nm or sub-20nm generation. Do we still think the 2D NAND Flash technologies have hit the scaling wall? According to TechInsights’ deep-dive analysis on current and future NAND Flash technologies, although 3D V-NAND architecture could help with the scaling limit, we believe the 2D MLC and TLC NAND Flash technologies remain strong and cost effective for 14nm, 12nm and even for single-digit nanometer node.

When it comes to 3D NAND technology, Samsung has been developing and mass-producing 32-tier V-NAND architecture (for technical analysis related to the Samsung 3D V-NAND click here) with MLC and TLC for their 850 PRO and 850 EVO since 2014, although, this is not the final goal for Samsung due to a relatively low yield, process complexity and bit-cost viewpoints. More 3D Flash products may appear at the end of this year, or early in 2016, as major NAND players such as Toshiba, SanDisk, Micron, Intel, and SK-Hynix bring out their 3D products with 24-tier, 32-tier or 48-tier FG (floating gate)/CTF (charge-trap-flash) architecture (Figure 1).

Figure 1. 2D and 3D NAND Technology Roadmap (Source: TechInsights Nand Roadmap, download here)

Figure 1. 2D and 3D NAND Technology Roadmap (Source: TechInsights Nand Roadmap, download here)

However, the ultimate target for 3D NAND is 128-tier or at least 64-tier structure from the bit-cost viewpoints. In that case, the aspect ratio of Si-channel and common source contacts would be over 80:1, which is a strong burden for process integration engineers. In addition, the uniformity of the 64-tier or 128-tier NAND cell characteristics in a NAND string and their endurance/retention/reliability properties during program/erase operation would be another big challenge for the vertical NAND string architecture.

The scaling limits for 10 nm-class and sub-10 nm 2D planar NAND structures include patterning technology including QPT (Quadruple Patterning Technology), cell-to-cell interference such as cross-talk, poly-Si gap-filling process for control gate (CG), self-aligned STI (SA-STI) for isolation patterning, self-aligned process (SAP) for CG/FG, interconnection methodology including pad layout/design, inter-poly dielectric (IPD) layer engineering, and cell transistor channel/source-drain (S/D) engineering. According to TechInsights’ detailed structural analysis and comparison of 15nm and 16nm NAND flash devices (so called 1Y NAND technology node) such as Samsung 16nm, Toshiba 15nm, Micron 16nm and SK-Hynix 16nm products, we may expect that at least two more next generation 2D planar NAND products having 12nm and less than 12 nm technology would be developed and released from major players near future. As for NAND memory density and die size, Toshiba/SanDisk 15nm TLC products have 1.28 Gb/mm2 which is double from other MLC products although Samsung 32-tier 3D V-NAND TLC products have 1.87 Gb/mm2 (Figure 2).

Fig 2

Figure 2. Comparison of NAND memory density for each product (Source: TechInsights)

For patterning the three finest lines of the NAND cell structure such as active/STI, gate/wordline (CG/FG) and bitline (usually, metal-2 lines), a quadruple patterning technology (QPT) seems to be very mature for each of the major NAND players. They use their own QPT integration on three critical layers with three or four masks, SOH etching and two-step self-align reverse patterning (SARP) process. Although the critical dimensions have a little skew on every four patterns, they have successfully developed QPT integration with less than 1nm CD (Critical Dimension) and it could be extended into 10nm and even single-digit nanometer NAND products. Fortunately and thanks to state-of-the-art anisotropic plasma etching and ALD/CVD technology, uniformly repeated 8nm patterns would be possible for NAND cell array. Figure 3 shows a comparison of DPT/QPT patterns for each product.

Figure 3. Comparison of DPT and QPT patterns for each product (Source: TechInsights)

Figure 3. Comparison of DPT and QPT patterns for each product (Source: TechInsights)

Micron uses a 3.3nm thin-FG poly-Si storage node to decrease cell-to-cell interference, while other manufacturers introduce an air-gap process for active, gate wordline (FG/CG) and bitline (metal-2) for thick-FG structure. Especially, the air-gap process has been developed and applied on the channel region of active patterns and FG/CG pillars help decrease the cross-talk.

For an IPD (Inter-Poly Dielectric) or a barrier layer between CG and FG, a multi-layer stacked with thin oxide (O) and nitride (N) layers such as ONO or NONON structure has been used for mid-10 nm class NAND devices, while Micron uses a high-k dielectrics such as HfO/SiO/HfO/Nitrided-SiO which is the same as their 20 nm NAND products. Micron successfully integrated IPD/FG/Tunnel-oxide and decreased FG thickness from 5 nm to 3.3 nm with high-k IPD. It might be further reduced to 10ish nm NAND products by optimizing IPD/FG quantum well structure for their unique thin-FG architecture. A 6 nm tunnel oxide (SiO) is used on Micron, Toshiba/SanDisk and SK-Hynix, while Samsung uses nitrogen-doped oxide in its top and bottom portion.

Triple-row staggered bitline contacts (BC) are used on Toshiba/SanDisk for the first time which is an excellent choice to make things smooth for cell layout and process integration although NAND string overhead is increased from 13% to 19%. Other players still use double-row staggered BC layouts on their 15nm/16nm NAND products (Figure 4).

Figure 4. Double- and triple-row staggered bitline contacts (Source: TechInsights)

Figure 4. Double- and triple-row staggered bitline contacts (Source: TechInsights)

Other barriers to extend 2D planar NAND to 10nm such as CG poly fill-ability, anisotropic etching for SA-FG/STI and CG/FG, cell transistor S/D engineering and leaning effect during the process integration are still there. Nevertheless, major players and their equipment vendors will successfully develop and integrate the 10 nm 2D NAND architecture in a few years.

I believe most of the major NAND players have their own matured process integration capability with assistance from ECC and circuit/layout optimization. 2D NAND technology will be further scaled down to 12nm, 10nm, or even 8ish nm which is more cost-effective than 3D V-NAND for near future NAND products.

HeadshotJeongdong Choe has more than 20 years of experience on semiconductor process and device integration including NAND Flash, DRAM, logic and advanced memory devices at Samsung and SK-Hynix. He works at TechInsights as a consulting engineer especially focusing on memory and logic process integration.

IC Insights will release its August Update to the 2015 McClean Report later this month.  The August Update will include an in-depth analysis of the IC foundry market and a look at the top 25 1H15 semiconductor suppliers’ sales results and their outlooks for 3Q15 (the top 20 1H15 semiconductor suppliers are covered in this research bulletin).

The top-20 worldwide semiconductor (IC and O S D—optoelectronic, sensor, and discrete) sales ranking for 1H15 is depicted in Figure 1.  As shown, it took just over $2.2 billion in sales just to make it into the 1H15 top-20 ranking and eight of the top 20 companies had 1H15 sales of at least $5.0 billion. The ranking includes seven suppliers headquartered in the U.S., four in Japan, three in Taiwan, three in Europe, two in South Korea, and one in Singapore.  The top-20 supplier list includes three pure-play foundries (TSMC, GlobalFoundries, and UMC) and four fabless companies.

IC Insights includes foundries in the top 20 semiconductor supplier ranking since it has always viewed the ranking as a top supplier list, not a marketshare ranking, and realizes that in some cases the semiconductor sales are double counted.

It should be noted that not all foundry sales should be excluded when attempting to create marketshare data. For example, although Samsung had a large amount of foundry sales in 1H15, some of its foundry sales were to Apple and other electronic system suppliers.  Since the electronic system suppliers do not resell these devices, counting these foundry sales as Samsung IC sales does not introduce double counting.  Overall, the top-20 list in Figure 1 is provided as a guideline to identify which companies are the leading semiconductor suppliers, whether they are IDMs, fabless companies, or foundries.

semi sales 2q15 fig 1

In total, the top 20 semiconductor companies’ sales increased by only 1% in 2Q15/1Q15, the same growth rate as the total worldwide semiconductor industry.  Although the top-20 semiconductor companies registered a 1% sequential increase in 2Q15, there was a 23-point spread between Samsung, the fastest growing company on the list (10 percent growth), and Qualcomm, the worst performing supplier (13 percent decline) in the ranking.  Moreover, given Qualcomm’s currently dismal guidance for 3Q15, the company is on pace to post a semiconductor sales decline of 20 percent in calendar year 2015.

Samsung’s excellent growth rate in 2Q15 put the company closer to catching Intel and becoming the world’s leading semiconductor supplier.  In 2014, Intel’s semiconductor sales were 36 percent greater than Samsung’s.  In 2Q15, the delta dropped by a whopping 20 percentage points to only 16 percent.  However, with Intel providing guidance for a 3Q15/2Q15 sales increase of 8 percent and Samsung facing a lackluster DRAM market (primarily due to pricing pressures), additional gains toward the number one position may be difficult for Samsung to achieve in the near future.

There were two new entrants into the top 20 ranking in 1H15—Japan-based Sharp and Taiwan-based pure-play foundry UMC, which replaced U.S.-based Nvidia and AMD.  AMD had a particularly rough 2Q15 and saw its sales drop 35 percent year-over-year.  In fact, in 2Q15, the company’s sales fell below $1.0 billion for the first time since 3Q03, almost 12 years ago.  It currently appears that AMD’s 2013 restructuring and new strategy programs to focus on non-PC end-use segments have yet to pay off (in addition to its sales decline, AMD lost $361 million in 1H15 after losing $403 million in 2014).

IC Insights has recently lowered its 2015 worldwide semiconductor market forecast from 5 percent to 2 percent.  As was shown in Figure 1, the top 20 semiconductor suppliers in total had $128.3 billion in sales in 1H15.  This figure was just under 50 percent of the top 20 companies’ full year 2014 sales of $259.1 billion.  With only modest growth expected in the second half of this year for the worldwide semiconductor market, the top 20 semiconductor suppliers’ combined sales in 2015 are expected to be only about 1-2 percent greater than in 2014.

Figure 2 shows how the 1H15 top 20 ranking would have looked if the Avago/Broadcom and NXP/Freescale mergers were in place.  As shown, Avago/Broadcom would have been ranked 7th and NXP/Freescale would have moved into the 10th spot.  IC Insights believes that additional acquisitions and mergers over the next few years are likely to continue to shake up the future top 20 semiconductor company rankings.

semi sales 2q15 fig 2

STATS ChipPAC Ltd., a provider of advanced semiconductor packaging and test services, announced today the promotion and appointment of Dr. Han Byung Joon  as Co-President and Chief Executive Officer for the Company, together with Mr Tan Lay Koon.

Mr. Tan Lay Koon and Dr. BJ Han will both report to the Board and be jointly responsible for the management, strategy and performance of the Company.

“I am pleased that Dr BJ Han will be serving as Co-President and Chief Executive Officer with Mr Tan Lay Koon. Dr BJ Han is an experienced and effective leader who has served as our Chief Technology Officer and Head of Global Sales and Advanced Technology Marketing. I look forward to his continued contribution and leadership with Mr Tan Lay Koon,” said Mr Wang XinChao, Chairman of the Board, STATS ChipPAC.

Dr. BJ Han has been the Company’s Chief Technology Officer since 1999. He is also responsible for Advanced Technology Marketing and is the Head of Global Sales for the Company. Prior to joining us, Dr. Han worked at Anam Semiconductor, AT&T Bell Labs and IBM. He received his Doctorate from Columbia University and attended Harvard Business School’s Executive Advanced Management Program.

Following the launch of the 12th Electronics Packaging Research Consortium (EPRC12) in 2013, A*STAR’s Institute of Microelectronics (IME) and 11 of its consortium partners across the semiconductor supply chain have developed novel solutions in integrated circuit (IC) packaging.

The consortium has achieved its objectives of developing novel solutions to overcome the reliability and performance issues and technical challenges in packaging solutions for compact sized consumer electronics and high power electronics. To achieve this, the consortium leveraged IME’s capabilities in wafer level packaging, assembly processes and thermo-mechanical modelling as well as the constant feedback from the industry players.

These solutions allow for high density packaging that enables greater system capabilities, such as increased memory and bandwidth and faster processing speed, paving the way for more powerful and efficient systems in consumer devices and high power electronics.

Improving reliability in packaging which utilizes Cu/low-k interconnects

The consortium successfully reduced the high thermo-mechanical stress that is generated in the assembly of IC packaging that adopts Cu pillars and low-k chips.

This was demonstrated through thermal compression bonding for large size chip (18x18mm chip) and package (25mm x 25mm FCBGA package).

The consortium reduced the pitch size of Cu pillars on a two-layer low cost organic substrate and bare Cu bond pads from 40μm to 30μm through thermal compression bonding. This process not only enables higher density interconnects but also enables the bonding of Cu pillar to bare Cu bond pads without traditional NiAu plating or organic solder preservative coating on Cu bond pads, leading to lower substrate costs.

A modeling methodology and a set of design guidelines were devised to help manufac turers c reate lo w-stress gene rating package designs. With these innovative advanced packaging solutions, packaging which utilises Cu/low-k interconnects becomes a viable option for further system scaling in the next generation computing and portable electronics such as smart phones and tablets.

Enabling smaller form factor in 3D Fan-out Package-on-Package (3D PoP)

The consortium reduced the existing package profile of the 3D Fan-out Package- on-Package to achieve higher power efficiency and cost-effectiveness across a wide range of consumer mobile applications including mobile devices, tablets, laptops and digital cameras.

This was achieved by removing the substrate on the Printed Circuit Board (PCB) that carries the passive components supporting electrical performance, and embedding these components within the package. The innovative technique which employs a Redistribution Layer (RDL) process flow and a Through Mold Via technology, reduces the package profile by approximately 25 per cent to achieve a higher density package, and also reduces the manufacturing cost by approximately 15 per cent.

Improving thermal management and power efficiency in high power electronic systems

The consortium has devised innovative packaging technologies to improve thermal management and power efficiency of high power electronic systems.

By applying a zinc-based high temperature soldering process and material optimisation, the consortium has managed to raise the maximum junction temperature of the TO-220, which is commonly used for high power switching device packaging, from 170 C to 245 C.

Thermal management capabilities were also demonstrated in a double-sided cooling power inverter module. The consortium utilised a flip-chip bonding and compression molding process to create a flat structure which serves as a thermally conductive path for both top and bottom surfaces of a power inverter module. This innovative process enables thermal resistance of up to 0.18 W/K, surpassing the conventional single-sided cooling modules by approximately 40 per cent.

The consortium achieved a 30 per cent height reduction in lead frame based Intelligent Power Modules (IPMs), enabling higher integration of power devices, control IC and passive components within a more compact package. This was achieved through a cost-effective technique of replacing the lead frame found in the IPMs with a thin and fine layer substrate and metal layer structure.

“These technology breakthroughs signify the consortium’s potential to keep pace with the rapid trends of advanced packaging. Through close collaboration with our industry partners, we have overcome technical hurdles to achieve smaller form factor and higher performance for next generation applications. IME will continue to contribute its research capabilities to develop timely solutions,” said Prof. Dim-Lee Kwong, Executive Director of IME.

“Heraeus have been working with IME through the different EPRC consortia for the past few years in developing new solutions to keep up with the emerging trends in the industry. The EPRC12 has helped Heraeus in understanding the challenges and requirements of high temperatures die attach materials and the processes, allowi ng us to address the industry’s unmet needs i n high temperature Pb free die attach materials for power device packaging,” said Dr. Zhang Xi, Head of Global R&D Bonding Wire, HET- Innovation, Heraeus Materials, Singapore Pte Ltd.

“Fan-Out Wafer Level Packaging (FOWLP) is a key technology for the semiconductor industry. By achieving the process development of dual side RDL on mold wafer and polymer filling on TMV (Through Mold Via) for FO PoP, the consortium helped us to understand the process requirement and overcome the material development challenges,” said Mr Takayoshi Suzuki, General Manager, Tokyo Ohka Kogyo, Singapore.

Qualcomm Incorporated today announced the appointment of Sunil Lalvani as vice president and president of Qualcomm India, and the departure of Avneesh Agrawal, senior vice president and president of Qualcomm India and South Asia. Lalvani’s appointment will be effective July 27 and he will report directly to Cristiano Amon, executive vice president and co-president, Qualcomm Technologies, Inc.

Lalvani has more than 20 years of experience in sales, business development, strategic planning and business operations across the IT and telecom sectors. He joins Qualcomm from BlackBerry, where he served most recently as managing director of India and SAARC (South Asian Association for Regional Cooperation). In this role, Lalvani was responsible for overseeing and driving BlackBerry’s overall business strategy and growth in India and was focused on driving differentiated solutions for consumers and enterprise customers. Lalvani was also instrumental in leading a strong engagement with Carrier partners and ISV’s in India, to drive uptake of BlackBerry’s services portfolio in the India region.

Prior to that, Lalvani held the position of Director of Enterprise Sales. Lalvani also has worked at EMC Corporation, Nokia Corporation, Cisco Systems and SITA Equant Network (now Orange Business Services).  Lalvani holds a bachelor’s degree in electronics engineering from Bombay University and a post graduate diploma in marketing management from Xavier’s Institute of Management, India.

“I am pleased to welcome Sunil Lalvani as vice president and president of Qualcomm India. His broad industry experience and extensive leadership experience will enable us to strengthen existing strategic relationships, identify new opportunities for business growth and build new relationships in India,” Amon said. “Under Avneesh’s leadership, Qualcomm led a number of successful efforts to nurture the local ecosystem in India, including accelerating 3G smartphone adoption and 4G LTE deployment, helping Indian brands build new revenue streams and establishing Qualcomm as the premier technology brand in India’s telecom and handset ecosystem. I’d like to thank Avneesh for all of his contributions to these successes.”

During his 21-year tenure, Agrawal has played a key role in many of the Company’s key technology initiatives including leading the development of Qualcomm’s first WCDMA and LTE chipsets, and has played a crucial role in driving Qualcomm’s business in India and South Asia.  In 2005 he assumed his role as senior vice president of engineering, where under his direction, the team has implemented a number of key initiatives to expand Qualcomm’s technology leadership and foster the mobile ecosystem in India. He has been granted 159 US patents. Avneesh is moving on to pursue his entrepreneurial ambitions.

By Jeff Dorsch, Contributing Editor

Semiconductor test equipment and inspection/metrology equipment are unglamorous yet critical segments of the equipment field.

Most people could name the top vendors in semiconductor manufacturing equipment, yet many would draw a blank after identifying KLA-Tencor as a leader in inspection/metrology equipment – maybe Applied Materials and Hitachi High-Technologies, if they’re on the ball.

Greg Smith, broadband and computing business unit manager for Teradyne, estimated the semiconductor test system market was worth $2.9 billion in 2014 and could come in at $2.6 billion this year.

“This year looks a little bit weaker than last year, last year being a strong year,” he says. 2014 saw a lot of capital spending on automatic test equipment, particularly in memory testing. The Apple iPhone 6 and Samsung Galaxy S6 boosted “the supply chain for those devices,” Smith observes. “This year, there’s not that kind of buzz.”

On the other hand, “automotive is very strong,” Smith says. “Microcontrollers are very strong.”

MCUs account for a total of $150 million to $200 million in sales per year, for all vendors, and testers for chips going into Internet of Things applications account for “probably only $10 million to $15 million of that total,” he adds.

Teradyne will be focusing on semiconductor test at SEMICON West, according to Smith. The company will feature its ETS-800 test system from the Eagle Test Systems line, which can handle radio frequency-enabled MCUs. The J750-LitePoint tester will also be highlighted, targeting chips for smart homes and wearable electronics.

On the inspection/metrology side of the market, Rudolph Technologies expects the second quarter will represent another quarter of growth, its fifth consecutive quarter of growth, according to Mike Plisinski, executive vice president and chief operating officer. Mobility is the main growth engine for the company and the industry, he says.

“Mobility drives a variety of devices and technologies including microprocessors, memory, RF communication devices, and MEMS sensors. The inspection and metrology requirements are increasing for many of these customers as their process complexity increases and at the same time they are under increasing pressure to react faster to consumer demand while improving long term reliability. More importantly, we see a trend towards more integrated solutions for customers,” Plisinski says.

The movement to wafer-level fan-out packaging at the back end is presenting “a lot of challenges in metrology for these types of packages,” Plisinski says.

When it comes to high-end devices using low-k and interlevel dielectrics, “we can predict where chipping and cracking could occur,” he adds. Rudolph has made significant investments in its software, which provides “more and deeper understanding,” he notes. “We go directly into the sensor data at the equipment to correlate it with what is happening at the wafer,” Plisinski says. “This is pushing the limits of our systems, requiring the use of ‘big data’ technologies and advances in data acquisition. That’s all been driven by the last 12 to 18 months of customer demand.”

“We see customers repurposing a lot of 200-millimeter equipment for some of smaller, lower-cost devices used in mobility and the Internet of Things,” Plisinski says. “We never stopped optimizing our 200-millimeter products.”

At the same time, he acknowledges that the Internet of Things is “not really driving Rudolph’s growth.”

FEI sees “momentum in the business that is favorable compared to last year, particularly in Asia,” says Rob Krueger, the company’s vice president and general manager for the semiconductor business. “Logic spending is a little lumpy, compared with memory,” he adds.

Krueger has witnessed research and development spending on 10-nanometer semiconductors in the past year, while R&D on 7nm chips is “definitely on,” he says. “We shipped our first (7nm) tools early this year to advanced laboratories.”

The large silicon foundries dominated FEI’s business in 2014, the executive says. “This year, it’s more regional foundries,” he notes. “We’re starting to see that trickle-down of advanced technology.”

One trend that Krueger sees is the transition from scanning electron microscope analysis to transmission electron microscope analysis. Analytics has evolved beyond “just pictures,” he says. While FEI’s life sciences business makes greater use of “big data” analytics technology than its electronics business, FEI’s customers are “processing larger data sets” when it comes to defect detection, Krueger says. “We’re handling data with standard computing.”

FEI is anticipating “the momentum to continue into the 2nd half of the year,” Krueger says.

FEI last month introduced a new Helios DualBeam plasma-focused ion beam system for electrical fault isolation, electrical failure analysis, and sample preparation for sub-20nm devices. The company has already made some customer shipments of the system, according to Krueger.

As the semiconductor industry progresses to 10nm, 7nm, and possibly 5nm devices, test and inspection/metrology equipment vendors stand ready to handle the challenges of new materials and other aspects of next-generation process nodes.

By Pete Singer, Editor-in-Chief

As packaging technology continues to advance to maintain the ever-increasing demand for faster, higher capacity, and lower power devices, wafer bumping plays an important role in enabling these capabilities. Bumps can be placed almost anywhere on the die, giving chip makers the ability to put more and more I/O points on an individual die compared to previous methods.

Inspecting bumps is becoming more challenging. The number of I/O points continues to increase. “As chip makers and OSATs need to put more bumps on an individual die, the geometries are being driven smaller and smaller just like transistor technology,” notes Mike Goodrich, vice president and general manager of Rudolph’s Inspection Business Unit.

Materials are also changing. The industry is experiencing a transition from solder bump to Cu pillar, just as it moved from an evaporated bump to a plated process, according to a new report from TechSearch International. While the transition to copper pillar is underway, SnAg remains the Pb-free solution of choice.

Laser triangulation technology in conjunction with specially designed optics and analytical algorithms is used on bump inspection systems to provide high-quality measurements of micro-bump critical dimensions at full production speeds.

“Manufacturers need to make sure all the bumps are at the same height. If you have one bump that’s too tall or too short, you start to run into connection issues that result in poor yield or a failed device,” says Goodrich. “Our systems measure bump height to make sure coplanarity is uniform across an individual die,” he added, referring to Rudolph Technologies’ Wafer Scanner Inspection Series. Combined with Discover Enterprise, Rudolph Technologies’ yield and defect management software, the tools provide yield management for 3D/2D bump and RDL metrology, bump and RDL defect detection, and macro defect inspection throughout post-fab processes.

The tools can be used in either a characterization mode, where the dimensions of every bump on every wafer is analyzed, or in a high volume manufacturing mode, where the norm is to do a sampling scenario to monitor for process excursions.

One of the biggest challenges is handling vast amounts of data. “An individual die can have several thousand bumps, which results in millions of bumps on a wafer,” Goodrich said. “The amount of data generated becomes pretty unwieldy, really fast. Being able to manage that data and turn it into information and make decisions is extremely important. We are working with customers to implement that into their process flow.”

Utilizing laser triangulation technology, the Wafer Scanner enables 3D inspection of bumps and RDL of different sizes at high speed. An optional ultra high resolution sensor enables inspection of micro bumps and RDL heights as low as 1µm. Film frame handling capability allows inspection of thin and diced wafers and features a quick-change wafer platform to switch between film frame and whole wafers.

Inspection Smooths a Bumpy Road photo

By Pete Singer, Editor-in-Chief

SEMICON West 2015 kicked off Tuesday morning with a keynote panel session that addressed the challenges of “Scaling the Walls of Sub-14nm Manufacturing.” The general consensus was that future progress is dependent on better coordination and collaboration between design, manufacturing and packaging companies and people.

The panel consisted of Jo de Boeck, Senior Vice President, Corporate Technology at imec, who acted as the moderator; Gary Patton, Chief Technology Officer and Head of Worldwide Research and Development at GLOBALFOUNDRIES; Michael Campbell, Senior VP Engineering at Qualcomm; Calvin Cheung, Vice President, Business Development and Engineering at ASE and Subhasish Mitra, Associate Professor, Dept. of EE and CD at Stanford University.

Tuesday panel

Patton said the end of scaling was nowhere in sight. “People have talked about the end of scaling. Scaling is not going to end. I am not worried about solving the physics challenges,” he said. “We have run into many barriers over the years and we always find a way to get around it.

Patton said what worries him is doing it in a way “that can deliver to our customers a real value proposition for going to that next technology node. The cost of doing design in these nodes is increasing at a pretty rapid rate and we have to provide them with a return on investment. It’s becoming more challenging,” he said.

He noted that in the past most breakthroughs, such as high-k metal gates, took over 10 years in the research stage before they were ready for manufacturing. That was one reason behind the merger between IBM and GLOBALFOUNDRIES: access to 16,000 some IBM patents. Patton also mentioned IBM’s expertise in a ASICs business, differentiated IP, RF technology – both silicon germanium as well as RFSOI – as well as 3D and 2.5D technologies.

Qualcomm’s Mike Campbell said the biggest threat to Moore’s Law is yield. “Yield is now an end-to-end question,” he said. “That doesn’t just mean semiconductor yield today. It’s the package yield on top of that and then the systems yield.”

Campbell said he’d like to see that end-to-end yield contained in a productivity model. “If you have a 10nm or 7nm silicon piece and it works to the spec at the silicon level, but then we change the stress characteristics because we have to saw and dice it up into a package. Then we put it into a 2.5D or 3D package and change the stress levels again. The yields change at every level,” he said.

Campbell believes that the whole system has to be interactive. “Until 28nm, you didn’t need to have that interactivity. But as we go deeper and deeper into submicron technology, the interactivity between the package, the system and the silicon itself—and the basic R&D for the silicon – all have to start to play together or else at the end we’ll end up with gaps in the system which will then add cost to the deliverables that we have to bring to the marketplace,” he said.

ASE’s Calvin Cheung said the company’s biggest concern was CPI (chip package interaction). “We are really pushing assembly and test technology capabilities,” he said. “In the case of 2.5D, we have connect a couple hundred thousand interconnects and put them on a very, very small space. With the scaling, the die is getting smaller but your I/O density continues to increase.”