Category Archives: Wafer Level Packaging

BY JIN YOU ZAO, STATS ChipPAC, Singapore, and JOHN THORNELL, Rudolph Technologies, Inc. Bloomington, MN, USA

The demand for 4-mask layer Cu-plated wafer-level chip scale packaging (WLCSP) is increasing rapidly, and the current capability for in-line Cu height measurements is not suitable for high volume manufacturing (HVM). Thus, metrology constrains production capacity and limits volume ramp. Furthermore, the bottleneck created by a backlog of Cu step height measurements risks the timely detection of process drift and control. For a 4-mask layer Cu-plated WLCSP, accurate Cu step height measurement is required for both the Redistribution Layer (RDL) and Under Bump Metal (UBM) to ensure consistent delivery of good electrical performance and package reliability. This is especially important as WLCSP is moving towards finer feature size and pitch to meet increasing demand for smaller form factor.

In this article, the current measurement methodology is reviewed and an alternative measurement solution is derived. Full automation capability is delivered, yet the solution is reliable and versatile enough for high-mix production volumes. For quick-turn and high-mix volume manufacturing, accurate and fast in-line monitoring is crucial for timely process drift detection and control.

WLCSP in-line process measurement challenges

Contact-based profilometers are commonly used in wafer bumping for measurement of metal feature (RDL, UBM) thicknesses due to their ease of use and their low cost of ownership. However, the method of measurement is largely semi-automatic, and the identification of exact features and measurement locations is challenging.

This becomes more acute in a high product-mix HVM environment, where measurement needs to be highly adaptive to different features on different products. As such, contact-based profilometers are limited to sampling measurements, and cannot perform 100% die inspection for process characterization.

It is thus desirable to have an automated feature measurement system capable of measuring features at precise locations on different topology on wafers in both sampling and full inspection modes.

Specifically, feature measurement for wafer bumping comprises the following configurations (FIGURE 1):

HVM Fig 1

a) Cu RDL feature height measurement after Cu electro-plating, where the sputtered metal seed layer to enable Cu plating remains on the first layer polyimide surface

b) Final Cu RDL feature thickness measurement on first layer polyimide surface (PI-1) after the Cu seed layer is etched away. Accurate final Cu RDL thickness measurement would require a good gauging of the PI-1 thickness underneath, especially if the topology is not flat.

c) Cu UBM feature height measurement after Cu electroplating

d) Final Cu UBM feature thickness measurement on second layer polyimide surface (PI-2)

The development for automated feature measurement proceeded in two phases: (Phase-1) Cu step height highlight measurement on reflective metal surfaces, and (Phase-2) Cu thickness and polyimide thickness measurement on non-reflective surfaces.

Phase-1: Auto Cu height measurement

In this phase, the 3D inspection (3DI) system commonly used for solder bump height (typically greater than 20μm) measurement is explored for auto Cu feature height measurement. Typical 3DI system such as Rudolph’s WaferScanner, is equipped with the 3D triangulation laser sensor (FIGURE 2). Laser triangulation, where a laser is directed at the wafer surface at an angle of 45° and focused to a spot size of 8μm, provides fast, precise measurements of bump height and coplanarity. Through a combination of laser-scanning and wafer movement, the beam scans the entire wafer surface. A lens collects the reflected/scattered laser light and focuses it on a position sensitive detector.

HVM Fig 2

To enable Cu feature height measurement (typically in the range of 2- 20μm), the Triangular laser sensor was redesigned with a spot size of 5μm, providing accuracy down to +/-0.2 μm. The laser scanning algorithm was also improved from an array to a stagger method to improve the repeatability of scanning signals. As Cu feature height measurement is influenced by the surrounding topology, the ability to select any datum for measurement is critical. This was achieved through the integration of camera-based 2D inspection to the improved triangular laser sensor system using the developed datum selection program. An automated height measurement report can be conveniently generated for further analysis through the program (FIGURE 3).

FIGURE 3. Selectable datum for Cu feature height measurement through camera-sensor integration.

FIGURE 3. Selectable datum for Cu feature height measurement through camera-sensor integration.

To verify the consistency of measurement performance, both the improved 3D triangulation laser sensor system and contact profilometer were used to measure feature Cu height on correlation device wafers. It confirmed that the automated 3D triangulation laser sensor system registers statistically similar Cu feature height mean compared to the manual contact profilometer, but required only one-fifth of the measurement time taken by the profilometer. Wafer bumping facilities which already have an existing pool of 3DI inspection tools can be modified to extend measurement application to Cu feature height without the need for excessive new investment.

Phase-2: Auto Cu/ PI thickness measurement

While a strong signal can be derived using the 3D triangular laser signal for Cu feature height measurement after electroplating (Fig. 1, a and c), it is more difficult to establish a stable signal for Cu feature height measurement after the reflective metal seed layer is etched away, and a reference datum needs to be established on the remaining transparent polyimide surface (Fig. 1, b and c). Several conventional methods exist for non-contact measurement of step heights, such as various confocal sensors, triangulation sensors, and scanning white light interferometry. These sensors typically have difficulty differentiating between reflections from the top and bottom surfaces of a layer, that is, layer thickness. This limitation comes from the depth of focus of the objective, which in turn depends on its numerical aperture (NA). Thus, for all these techniques, sensor performance is highly dependent on objective lens.

To overcome this technical constraint, it was necessary to develop a metrology system that can measure concurrently the transparent layer thickness as well as the metal feature step height above the surface of the transparent layer. This can be achieved through the integration of reflectometry and visible light interferometry principles [3]. In this method, the direct reflection from the transparent layer provides direct thickness measurement of the transparent material, while the interferometry captures topography (distance from the sensor), allowing the system to measure the thickness of the opaque metals by scanning over the edge of the feature. This technique is called the visible thickness and shape sensor (VT-SS) system.

In the following sections we provides further description of how the VT-SS system can be adapted for feature height/thickness measurement on varying topology and opaque materials. For this work, we used the Rudolph Technologies NSX System configured with the VT-SS sensor.

VT-SS system MSA study

Measurement system analysis (MSA) seeks to qualify a measurement system for use by quantifying its accuracy, precision and stability. VLSI standard wafers with 8μm, 24μm, and 48μm step heights were used to assess gauge repeatability and reproducibility (GR&R) and accuracy of the VT-SS system, as well as system correlation on two different NSX Systems (tool matching) that were retrofitted with the VT-SS system.

A. Gauge repeatability and reproducibility
For the GR&R study, a total of ten parts on VLSI wafers (4 parts from 8μm, 3 parts from 24μm and 48μm respectively) were measured three times each, including wafer loading and unloading. FIGURE 4 shows gauge R&R for VT-SS is 1.35% of tolerance and fully meeting AIAG standard of <10%.

HVM Fig 4

B. Accuracy
Step height measurement accuracy was evaluated by means of bias and linearity analysis using the VLSI step height wafers. For this study, one location on each standard wafer was measured ten times and compared to the VLSI specification for the wafer.

Based on the studies in FIGURE 5, measurement with VT-SS system shows an average bias of 0.95%, and linearity error of 0.0059%, meeting the AIAG standard of <5%.

FIGURE 5. Accuracy study on VT-SS with VLSI standard.

FIGURE 5. Accuracy study on VT-SS with VLSI standard.

C. Correlation of Multiple Systems
Having established VT-SS capability, the next evaluation is system correlation on multiple tools of the same configuration. The same VLSI wafers described above were measured on a second system with the same hardware and software configuration.

HVM Table 1

A summary of results are shown in TABLE 1, and a detailed example of the 24μm step height is shown in FIGURE 6. For each wafer, the two systems produce similar results, with an offset that ranges from approximately 10nm to 30nm. Considering that the measurement uncertainty is on the order of 5nm (1-), the small system offset is within expectations.

HVM Fig 6

VT-SS system application assessment

VT-SS system allows capturing of both the transparent polyimide thickness and opaque Cu feature height with a single scan from polyimide layer to Cu feature. From the part of the scan covering the polyimide, signals representing the direct measure of the polyimide thickness, the distance to the first surface of the polyimide, and the distance to a metal surface under the passivation stack are measured. The direct measure of the polyimide thickness is the measurement a standard spectroscopic reflectometer would produce. In that part of the scan where the sensor spot illuminates the Cu step height, the direct thickness peak and one of the distance peaks disappear. Only a distance peak to the surface of the Cu feature is present since the copper is opaque. The Cu step height above the first polyimide layer is then determined from the appro- priate distance measures from each part of the scan. Thus, all the desired thickness and Cu thickness measurements are reported.

To aid interpretation of measured signal peaks, a visualization program was developed for automated generation of feature thickness. FIGURE 7 shows an illustration of the program interface for visualization of measured thickness. Raw data can also be exported for further analysis.

HVM Fig 7

A. VT-SS Cu RDL Layer thickness measurement
To assess VT-SS system’s measurement performance on an actual device feature, it was used to measure the Cu feature RDL thickness layer above the first polyimide (PI) layer (refer to Fig. 1, for a pictorial illustration) on a correlation device wafer. The measured RDL thickness was then cross verified with the actual measured Cu feature step height from a contact profilometer and WaferScanner

B. VT-SS Polyimide cum RDL layer Thickness
Further evaluation of the VT-SS system accuracy was achieved through comparison with cross sectional scanning electron microscopy (X-SEM) measurements. X-SEM allows evaluation of both RDL step height and PI thickness (Fig. 1, b). As discussed above the measurement sensor has the unique capability to simultaneously measure step height, i.e. a distance measurement, and film thickness. Both types of measurements must be independently evaluated for accuracy.

Conclusion

We have reported the development of VT-SS-based system on a fully automated platform for in-line process measurement of wafer bumping processes. This new metrology integrates both reflectometry and visible light interferometry principles. Based on MSA studies, VT-SS on a fully automated platform is a precise, accurate and fast metrology system. Engineering validations have shown VT-SS is highly capable in measuring critical dimensions such as RDL/UBM metal thickness, transparent polyimide/ passivation thickness, and feature sizes in one single step. It relieves the current constraints imposed by existing measurement tools on in-line process control, especially in a high mix, high volume production environment. This allows WLCSP production to move to new milestones of quality, yield, cycle time and productivity.

Acknowledgment

The authors would like to thank Harry Kam of STATSChipPAC Singapore (SCS) for his sponsorship in this project, and other team members from SCS and Rudolph Technologies, Inc. for supporting the development work.

References
1. Yole Development, WLCSP Market & Industrial Trends: 2012, Jan2012
2. Robert F. Kunesh, “Wafer Level Chip-Scale Packaging: Evolving to Meet a Growing Application Space”, Adv. Microelectronics, Jan/Feb 2013, Vol. No.1, pp14-16.
3. J. Schwider and Liang Zhou, “Dispersive Interferometric Profilometer,” Opt. Lett., Vol. 19, p. 995, 1994.

JIN YOU ZAO is with STATS ChipPAC in Singapore, and JOHN THORNELL is with Rudolph Technologies, Inc., in Bloomington, MN.

By David W. Price and Douglas G. Sutherland

Author’s Note: This is the eighth in a series of 10 installments that explore certain fundamental truths about process control—defect inspection and metrology—for the semiconductor industry. Each article introduces one of the 10 fundamental truths and highlights its implications.

Moving to the next design rule can be stressful for the inspection and metrology engineer. Like everything else in the fab, process control generally doesn’t get any easier as design rules shrink and new processes are introduced.

The eighth fundamental truth of process control for the semiconductor IC industry is:

Process Control Requirements Increase with Each Design Rule

This statement has proven to be historically accurate, as evidenced by the increase in process control spending as a percentage of wafer front-end (WFE) total costs. This article, however, will focus on a few of the forward-looking observations that we believe will further accelerate the adoption of process control.

The historical increase in process control with shrinking design rules has been driven largely by the introduction of key technical inflections. Recent examples for logic/foundry include immersion lithography, high-k metal gates, gate-last integration, and FinFET transistor structures. These high profile process changes required enormous engineering focus and led to the implementation of new inspection and metrology steps to characterize the associated defectivity and drive yield learning.

While the industry will continue to face significant technical challenges (next-generation lithography being the most obvious example), there is another factor emerging which will play an equally large role in setting the inspection and metrology strategy for the 16/14nm design node and beyond.

Figure 1 shows the number of process steps as a function of design rule for a generic logic/foundry process. Up to the 20nm node, there has been a very modest increase in process steps with design rule shrinks due to, for example, more metal levels and the addition of hard mask steps. But starting at 16/14nm, there will be an unprecedented increase in the number of process steps. This jump in process steps will be driven by:

  • The shift from 2D to 3D transistor structures in both logic and memory
  • More complicated integration in both the front end and back end
  • The push-out of EUV lithography, leading to massive numbers of multi-patterning steps

Figure 1. The number of process steps will increase dramatically, starting at 16/14nm. [source: IC Knowledge Strategic Cost Model, KLA-Tencor internal data]

Figure 1. The number of process steps will increase dramatically, starting at 16/14nm. [source: IC Knowledge Strategic Cost Model, KLA-Tencor internal data]

Process Tool Defectivity

Because of this increase in process steps—and the accumulative nature of yield loss—fabs must reduce the defectivity at each individual step in order to achieve the same final yield. Figure 2 shows the total yield as a function of the number of process steps where the average per-step yield is held constant. Prior to 16/14nm, this effect was scarcely noticeable since the total increase in process steps was minimal.

Moving forward, fab defect reduction teams must continue to resolve the challenging new technical inflections. But they must also place more focus on driving down defectivity at all process steps:

  1. Line Yield: To maintain the same line yield (wafers out / wafers in), there must be fewer excursions and less scrap at each step
  2. Die Yield: Every operation in the fab must be held to a tighter specification for defect density (D0) and variation (Cpk)

To make matters worse, defect inspection and metrology operations will continue to become more difficult. The defect count must go down even as the number of yield-relevant defects increases and the detection task becomes harder. Similarly, the variability in metrology measurements must be reduced even as those measurements become more difficult to make.

Figure 2. The Cumulative (Final) Yield is the product of the per-step yield for each unit operation in the process flow. This chart shows that, for a given average per-step yield, the final yield will decrease as the number of process steps increases.

Figure 2. The Cumulative (Final) Yield is the product of the per-step yield for each unit operation in the process flow. This chart shows that, for a given average per-step yield, the final yield will decrease as the number of process steps increases.

Impact on Cycle Time

The increase in process steps has another downside: increased cycle time. If cycle time increases in proportion to the number of process steps then it follows from Figure 1 that the cycle time will roughly double from the 20nm to the 10nm node. One publication has even suggested that the cycle time may double from 20nm to an advanced 16nm process [2].

The fab’s ability to do yield learning via feedback from electrical test and physical failure analysis (PFA) is directly tied to the “hot lot” cycle time. Longer hot-lot cycle times mean fewer opportunities for these long-loop learning cycles as device manufacturers try to ramp yield and deliver products to market. More emphasis must therefore be placed on in-line yield learning methodologies.

Sampling Pressure

Finally, more process steps will increase the manufacturing cost per wafer. In the second article in this series, Sampling Matters, we showed that the ideal sampling rate (that which provides the lowest total cost to the fab) goes with the square root of the device manufacturing cost. In other words, if the manufacturing cost increases by 30 percent then the corresponding process control sampling rate needs to increase by 14 percent (everything else being constant) to stay at the lowest total cost. This sampling increase will put further pressure on the fab’s inspection and metrology teams.

Summary

In summary, each new design rule will introduce:

  • Technical inflections that require engineering focus and innovation, as well as the implementation of new process control methodologies
  • More process steps that must be directly monitored
  • Tighter controls and lower defect density at each individual step due to the compounding nature of yield loss
  • Longer cycle times, resulting in more reliance on in-line (vs. end-of-line) techniques for yield learning
  • Higher stakes (greater economic impact to the fab) in the event of an excursion due to the higher wafer manufacturing costs, which will put pressure on the fab to increase inspection and metrology sampling

The cascade of challenges that flows from the increase in process steps is sometimes referred to as the “Tyranny of Numbers.” For further exploration of how fabs are adapting their process control strategy for new design rules, please contact the authors of this article.

About the authors:

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Drs. Price and Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

References:

  1. Lipsky, “TSMC Outlines 16nm, 10nm Plans.” EE Times, 4/8/2015.
  2. Jones, Strategic Cost Model, IC Knowledge, LLC. http://www.icknowledge.com/

Read more Process Watch: 

Time is the enemy of profitability

Know your enemy

The most expensive defect

Process Watch: Fab managers don’t like surprises

Process Watch: The 10 fundamental truths of process control for the semiconductor IC industry

Process Watch: Exploring the dark side

“The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

GLOBALFOUNDRIES today announced that it has completed its acquisition of IBM’s Microelectronics business.

With the acquisition, GLOBALFOUNDRIES gains differentiated technologies to enhance its product offerings in key growth markets, from mobility and Internet of Things (IoT) to Big Data and high-performance computing. The deal strengthens the company’s workforce, adding decades of experience and expertise in semiconductor development, device expertise, design, and manufacturing. And the addition of more than 16,000 patents and applications makes GLOBALFOUNDRIES the holder of one of the largest semiconductor patent portfolios in the world.

“Today we have significantly enhanced our technology development capabilities and reinforce our long-term commitment to investing in R&D for technology leadership,” said Sanjay Jha, chief executive officer of GLOBALFOUNDRIES. “We have added world-class technologists and differentiated technologies, such as RF and ASIC, to meet our customers’ needs and accelerate our progress toward becoming a foundry powerhouse.”

Through the addition of some of the brightest and most innovative scientists and engineers in the semiconductor industry, GLOBALFOUNDRIES solidifies its path to advanced process technologies at 10nm, 7nm, and beyond.

In RF, GLOBALFOUNDRIES now has technology leadership in wireless front-end module solutions. IBM has developed world-class capabilities in both RF silicon-on-insulator (RFSOI) and high-performance silicon-germanium (SiGe) technologies, which are highly complementary to GLOBALFOUNDRIES’ existing mainstream technology offerings. The company will continue to invest to deliver the next generation of its RFSOI roadmap and looks to capture opportunities in the automotive and home markets.

In ASICs, GLOBALFOUNDRIES now has technology leadership in wired communications. This enables the company to provide the design capabilities and IP necessary to develop these high-performance customized products and solutions. With increased investments, the company plans to develop additional ASIC solutions in areas of storage, printers and networking. The most recent ASIC family, announced in January and built on GLOBALFOUNDRIES’ 14nm-LPP technology, has been well accepted in the marketplace with several design wins.

GLOBALFOUNDRIES increases its manufacturing scale with fabs in East Fishkill, NY and Essex Junction, VT. These facilities will operate as part of the company’s growing global operations, adding capacity and top-notch engineers to better meet the needs of its existing and new customers.

Moreover, the transaction builds on significant investments in the burgeoning Northeast Technology Corridor, which includes GLOBALFOUNDRIES’ leading-edge Fab 8 facility in Saratoga County, NY and joint R&D activities at SUNY Polytechnic Institute’s College of Nanoscale Science and Engineering in Albany, NY. The company’s presence in the northeast now exceeds 8,000 direct employees.

The acquisition includes an exclusive commitment to supply IBM with advanced semiconductor processor solutions for the next 10 years. GLOBALFOUNDRIES also gets direct access to IBM’s continued investment in semiconductor research, solidifying its path to advanced process geometries at 10nm and beyond.

Related news: 

IBM announces $3B research initiative

Research led by Michigan State University could someday lead to the development of new and improved semiconductors.

In a paper published in the journal Science Advances, the scientists detailed how they developed a method to change the electronic properties of materials in a way that will more easily allow an electrical current to pass through.

The electrical properties of semiconductors depend on the nature of trace impurities, known as dopants, which when added appropriately to the material will allow for the designing of more efficient solid-state electronics.

The MSU researchers found that by shooting an ultrafast laser pulse into the material, its properties would change as if it had been chemically “doped.” This process is known as “photo-doping.”

“The material we studied is an unconventional semiconductor made of alternating atomically thin layers of metals and insulators,” said Chong-Yu Ruan, an associate professor of physics and astronomy who led the research effort at MSU. “This combination allows many unusual properties, including highly resistive and also superconducting behaviors to emerge, especially when ‘doped.'”

An ultrafast electron-based imaging technique developed by Ruan and his team at MSU allowed the group to observe the changes in the materials. By varying the wavelengths and intensities of the laser pulses, the researchers were able to observe phases with different properties that are captured on the femtosecond timescale. A femtosecond is 1 quadrillionth, or 1 millionth of 1 billionth, of a second.

“The laser pulses act like dopants that temporarily weaken the glue that binds charges and ions together in the materials at a speed that is ultrafast and allow new electronic phases to spontaneously form to engineer new properties,” Ruan said. “Capturing these processes in the act allows us to understand the physical nature of transformations at the most fundamental level.”

Philip Duxbury, a team member and chairperson of the department of physics and astronomy, said ultrafast photo-doping “has potential applications that could lead to the development of next-generation electronic materials and possibly optically controlled switching devices employing undoped semiconductor materials.”

A semiconductor is a substance that conducts electricity under some conditions but not others, making it a good medium for the control of electrical current. They are used in any number of electronics, including computers.

Deca Technologies, an electronic interconnect solutions provider to the semiconductor industry, announced today that it has shipped more than half a billion units since the company’s launch. Deca attributes this achievement to the very positive response from the industry to Deca¹s value proposition of enabling reduced cycle times and lower overall costs for wafer-level chip scale packages (WLCSP), combined with the overall growth in the use of WLCSP. This increase in demand led Deca to expand its automated production line (Autoline) in its Laguna, Philippines factory, which doubles its capacity to accommodate growing market needs.

The handset, wearables and Internet-of-Things markets are driving demand for low-cost WLCSP devices with rapid turnaround from design to delivery. Meeting these demands has been problematic for the majority of the supply base. Time-to-ramp for new product introductions is critical, as is dynamic manufacturing capability from the WLCSP supply base. Deca’s Autoline has demonstrated that it significantly reduces cycle time, thereby giving customers an ability to respond to rapid market demand swings and the competitive edge to be first to market.

“We consistently set new industry records in supporting new product builds for our customers,” said Garry Pycroft, Vice President of Sales and Marketing at Deca Technologies. “Thanks to our Autoline, it’s now possible to get customers’ first parts out within 24 hours, while others are still awaiting delivery of mask sets to start the build. As such, Deca’s customers have a significant advantage in getting to market first.”

Deca’s Autoline further provides an advantage with the flexibility to support 200mm as well as 300mm wafers. “We’re seeing some reluctance from the supply base to invest in 200mm capacity, as the long-term ROI is being questioned,” said Chris Seams, CEO of Deca Technologies. “Our expansion provides additional capacity for 200mm and gives us the opportunity to capitalize on the growth in 300mm demand.”

“From Deca Technologies’ inception, our vision for the Autoline was to support the need for rapid cycle time and increased capacity,” Seams continued. “This vision has now been realized.”

Semiconductor Manufacturing International Corporation, China’s largest and most advanced semiconductor foundry; Huawei, a global information and communications technology (ICT) solutions provider; imec, a nanoelectronics research and development (R&D) centers; and Qualcomm Global Trading Pte. Ltd., an affiliate of Qualcomm Incorporated, one of the world’s largest fabless semiconductor vendors, held a signing ceremony at the Great Hall of the People, to announce the formation of SMIC Advanced Technology Research & Development (Shanghai) Corporation, an equity joint venture company. The joint venture company will focus on R&D towards next generation CMOS logic technology and build China’s most advanced integrated circuit (IC) development R&D platform.

His Majesty (H.M.) King Philippe of Belgium is visiting China in the framework of several cooperation agreements between China and Belgium related to cutting-edge technology. A Chinese leader and H.M. King Philippe of Belgium witnessed the signing ceremony of the joint investment.

SMIC Advanced Technology R&D (Shanghai) Corporation will be majority owned by SMIC, while Huawei, imec, and Qualcomm will be minority shareholders. The current focus will be on developing 14nm logic technology. Dr. Tzu-Yin Chiu, Chief Executive Officer and Executive Director of SMIC will be the legal representative, Dr. Yu Shaofeng, Vice President of SMIC will be the general manager.

This project is a major breakthrough in the cooperation model for IC manufacturers, international trade companies and research institutions. This project will facilitate closer cooperation between upstream and downstream companies, leading-edge R&D, and other synergies in the industry’s global eco-system. With the joint venture company oriented on innovation, it can target the demands of the industry more quickly and effectively through its R&D and manufacturing resources. Meanwhile, by enabling fabless semiconductor companies to join the development process as shareholders, the product development cycle can be shortened and the advanced process node tape out time can be accelerated.

In the first phase, the joint venture company will develop 14nm CMOS technology for mass production, which will be based on imec’s knowhow in advanced semiconductor processing technology. The new R&D project will be done at SMIC’s production line.

SMIC will have the rights to license the required intellectual property rights on the mass production technologies of advanced nodes developed by the joint venture company, enabling these technologies to be applied to SMIC’s current and future range of products and serve SMIC’s business with other companies. This can improve the overall level of China’s IC technologies, and is expected to facilitate the mass production of 16/14nm ICs in China by 2020, which is one of the goals set by the National IC Industry Development Outline. In the future, companies in China’s IC manufacturing industry, universities and colleges, and research institutions will continue working together on this platform to further enhance the core competitiveness of the industry.

Dr. Zhou Zixue, Chairman, of SMIC; Steve Chu, Vice President of Huawei; Ludo Deferm, Executive Vice President of Corporate Business and Public Affairs of imec; and Derek Aberle, President of Qualcomm Incorporated were all present at the signing ceremony.

“This is the most advanced work for China’s IC industry,” said Dr. Tzu-Yin Chiu, Chief Executive Officer and Executive Director, of SMIC, “With 15 years of experience in manufacturing and R&D, SMIC is China’s largest semiconductor enterprise and has the capabilities to bring 14nm technology into production. It is exciting to be working with the largest IC design company both in China and abroad, and the world’s top research institutes to tackle advanced IC process technology. This collaboration will play an important role in improving our technologies and products. The new company model has allowed us to explore a new path to open up R&D and manufacturing resources in this industry’s ecosystem, and develop our advanced technology and R&D capabilities. In addition, it actively promotes the collaboration across all parts of the eco-system in China. ”

Steve Chu, Vice President of Huawei said: “Huawei has always been open to win-win partnerships. With our 20 years of experience in the IC design field and collaboration from our global partners, we are keen to promote the development of research capabilities in IC technology, to create China’s most advanced IC R&D platform. We believe that this collaboration will consolidate the IC domain, increase its resources and capabilities, and thereby improving the overall level of China’s IC industry. The improvements will provide more benefits to operators, companies, customers and partners.”

Luc Van den hove, CEO and president of imec, added: “We see a growing potential in China, both as a market and as a source of innovative engineering. The expertise of the four partners is focused on the creation of an excellent platform to foster nanoelectronics R&D in China. And the joint development of a 14nm process facility will be a step stone to achieve this goal. A step stone that, I am convinced, will benefit the world’s IC manufacturing community.”

“We are pleased to collaborate with SMIC, Huawei and imec to establish this new technology R&D joint venture company,” said Derek Aberle, president of Qualcomm Incorporated. “This is a significant milestone for the Chinese and global IC industries, which reinforces Qualcomm’s commitment to the continued growth of the vibrant semiconductor ecosystem in China. We believe that this venture will serve to better meet the growing needs of local Chinese and global customers who demand high performance, low power mobile devices. The collaboration will also help bring even more advanced processing technology and wafer manufacturing capacity to China, thereby helping China to build capability in FinFET technology. “

United Microelectronics Corporation, a global semiconductor foundry, today announced it has collaborated with ARM to tape out a process qualification vehicle (PQV) test chip on UMC’s 14nm FinFET technology to help validate an ARM Cortex-A family core on the advanced foundry process node. The 14nm cooperation expands on the two companies’ successful effort to develop and offer ARM Artisan Physical IP on UMC’s volume production 28nm High-K/Metal Gate process.

The validation of the UMC 14nm FinFET process technology kickstarts the enablement process for the rest of IP ecosystem needed for UMC’s FinFET technology, including the need for foundation IP and ARM processor physical design.

“ARM and UMC share a long history of successful collaboration through multiple technology generations,” said Will Abbey, general manager, physical design group, ARM. “We are highly encouraged by the test chip tape-out of a Cortex-A family core using UMC’s 14nm FinFet process. ARM will continue its close partnership with UMC during the development of this advanced process node.”

“As UMC prepares to make available our 14nm FinFET process to customers, it is important that we build a strong design support foundation to enhance our overall 14nm platform offering,” said Steve Wang, vice president of UMC’s IP and Design Support division. “ARM is a world-leading provider of advanced IP for leading-edge processes and we are excited to expand upon our past successes with them to develop Artisan Physical IP and Cortex-based solutions for our 14nm technology.”

UMC’s 14nm FinFET process has already demonstrated favorable 128mb SRAM yields and is expected to be ready for customer tape-out by late 2015.

Fan-in WLP is experiencing continuous growth and attracting new applications, according to Yole Développement’s (Yole) latest report “Fan-in Wafer Level Packaging: Market & Technology Trends.” Indeed fan-in WLP technology confirms its presence on the semiconductor market with indisputable benefits linked to cost and form factor. Technology innovation continues and widens the sphere of possibilities of fan-in WLP solutions.
“Fan-in Wafer Level Packaging: Market & Technology Trends” report proposes a deep analysis of the fan-in WLP technology trends with a dedicated roadmap and an overview of latest technical innovations. Under this report, the “More than Moore” market research and strategy consulting company, Yole, also reviews the potential disruptions including new market drivers, infrastructure, expanding business models, new entries, competing packaging solutions, and analyzes the impact on the supply chain.

Although seemingly out of the spotlight, fan-in Wafer Level Packages (WLP) remain a highly important and constant presence with unmatchable advantages in cost and form factor. Fan-in WLP holds 16 percent of the total number of packages, while serving 4.4 percent of the wafer market at only 1.5 percent of the total semiconductor revenue.

“Fan-in WLP is forecasted to continue a stable growth, with a market of $5.3B in 2014 and a CAGR between 2014 and 2020 of 7 percent,” explained Andrej Ivankovic, Technology & Market Analyst, in the Advanced Packaging and Semiconductor Manufacturing team, at Yole. And he added: “The total wafer count in 300mm equivalent wafers is reaching 4 million with a projected CAGR of 8 percent while the unit number is found at 36 billion with a projected CAGR of 9 percent.”

Throughout the past few years, MEMS and CMOS image sensors have been increasing their share compared to analog, mixed signal and digital ICs and are now accounting for more than 50 percent of the total revenue.

The leading applications by wafer demand in the analog/mixed signal/digital domain are BT+WiFi+FM combos and RF transceivers followed by PMU, audio/video codecs, DC/DC converters, ESD/EMI IPD. MEMS devices are led by digital compasses, RF filters, accelerometers and gyroscopes. CMOS image sensors are strongly positioned in 2nd place by overall fan-in application rankings. In total 41 applications and their evolution are analyzed in more depth within Yole’s report. Yole’s data include breakdowns of MEMS, CMOS image sensors and analog, mixed signal and digital devices.

From a technology viewpoint, innovation continues in order to extend fan-in WLP capability, as summarized in Yole’s figure below.

fan in wlp fig 1

Click to view full size.

“Current bump pitch in high volume is mostly at 0.4mm with 0.35mm already present as well. Particular effort is being made to increase the die size and I/O count” says Santosh Kumar, Senior Technology & Market research analyst, Advanced Packaging and Semiconductor Manufacturing at Yole. Max I/O count in high volume is heading above 200 and announcements have been made for high volume production up to 800 I/Os. The die size sweet spot ranges up to 7mm x 7mm with 8mm x 8mm and 9mm x 9mm qualified and ready.

Yole’s technology & market analysis contains an in-depth analysis on the outlook for bump pitch, die size, I/O count, minimum line width/space, package thickness, RDL dielectric materials, who is developing which technology and the main challenges to be overcome for the evolution of fan-in technology. Fan-in WLP is still on track of technology innovation.

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North America-based manufacturers of semiconductor equipment posted $1.56 billion in orders worldwide in May 2015 (three-month average basis) and a book-to-bill ratio of 0.99, according to the May EMDS Book-to-Bill Report published today by SEMI.   A book-to-bill of 0.99 means that $99 worth of orders were received for every $100 of product billed for the month.

SEMI reports that the three-month average of worldwide bookings in May 2015 was $1.56 billion. The bookings figure is 0.8 percent lower than the final April 2015 level of $1.57 billion, and is 11.0 percent higher than the May 2014 order level of $1.41 billion.

The three-month average of worldwide billings in May 2015 was $1.57 billion. The billings figure is 3.7 percent higher than the final April 2015 level of $1.51 billion, and is 11.6 percent higher than the May 2014 billings level of $1.41 billion.

“The May book-to-bill ratio slipped below parity as billings improved and bookings dipped slightly from April’s values,” said Denny McGuirk, president and CEO of SEMI.  “Compared to one year ago, both bookings and billings continue to trend at higher levels.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill
December 2014 

$1,395.9

$1,381.5

0.99
January 2015 

$1,279.1

$1,325.6

1.04
February 2015 

$1,280.1

$1,313.7

1.03
March 2015 

$1,265.6

$1,392.7

1.10
April 2015 (final)

$1,515.3

$1,573.7

1.04
May 2015 (prelim)

$1,571.2

$1,561.4

0.99

Source: SEMI (www.semi.org), June 2015

SEMI today announced the update of its World Fab Forecast report for 2015 and 2016. The report projects that semiconductor fab equipment spending (new, used, for Front End facilities) is expected to increase 11 percent (US$38.7 billion) in 2015 and another 5 percent ($40.7 billion) in 2016. Since February 2015, SEMI has made 282 updates to its detailed World Fab Forecast report, which tracks fab spending for construction and equipment, as well as capacity changes, and technology nodes transitions and product type changes by fab.   

Capital expenditure (capex without fabless and backend) by device manufacturers is forecast to increase almost 6 percent in 2015 and over 2 percent in 2016. Fab equipment spending is forecast to depart from the typical historic trend over the past 15 years of two years of spending growth followed by one of decline.  For the first time, equipment spending could grow every year for three years in a row: 2014, 2015, and 2016.

The SEMI World Fab Forecast Report, a “bottoms up” company-by-company and fab-by-fab approach, lists over 48 facilities making DRAM products and 32 facilities making NAND products. The report also monitors 36 construction projects with investments totaling over $5.6 billion in 2015 and 20 construction projects with investments of over $7.5 billion in 2016.  

According to the SEMI report, fab equipment spending in 2015 will be driven by Memory and Foundry ─ with Taiwan and Korea projected to become the largest markets for fab equipment at $10.6 billion and $9.3 billion, respectively. The market in the Americas is forecast to reach $6.1 billion, with Japan and China following at $4.5 and $4.4 billion, respectively. Europe/Mideast is predicted to invest $2.6 billion. The fab equipment market in South East Asia is expected to total $1.2 billion in 2015.

Learn more about the SEMI World Fab Forecast and plan to attend the SEMI/Gartner Market Symposium at SEMICON West 2015 on Monday, July 13 for an update on the semiconductor supply chain market outlook. In addition to presentations from Gartner analysts, Christian Dieseldorff of SEMI will present on “Trends and Outlook for Fabs and Fab Capacity” and Lara Chamness will present on “Semiconductor Wafer Fab Materials Market and Year-to-Date Front-End Equipment Trends.”   

Fab Equipment Spending
(for Front-End Facilities, includes new, used, in-house)

 

2014

(US$B)

2015

(US$B)

Year-over-Year
Americas

7.8

6.1

-22%
China

4.1

4.4

10%
Europe and Mideast

2.2

2.6

18%
Japan

3.8

4.5

17%
Korea

7.4

9.3

27%
SE Asia

1.1

1.2

2%
Taiwan

8.5

10.6

25%
Total

34.9

38.7

11%
Source: SEMI World Fab Forecast Reports (May 2015)Totals may not add due to rounding