Category Archives: Wafer Level Packaging

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $117.9 billion during the second quarter of 2018, an increase of 6.0 percent over the previous quarter and 20.5 percent more than the second quarter of 2017. Global sales for the month of June 2018 reached $39.3 billion, an uptick of 1.5 percent over last month’s total of $38.7 billion, and a surge of 20.5 percent compared to the June 2017 total of $32.6 billion. Cumulatively, year-to-date sales during the first half of 2018 were 20.4 percent higher than they were at the same point in 2017. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Halfway through 2018, the global semiconductor industry continues to post impressive sales totals, notching its highest-ever quarterly sales in Q2 and record monthly sales in June,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Global sales have increased year-to-year by more than 20 percent for 15 consecutive months, and sales of every major product category increased year-to-year in June. Sales into the Americas market continue to be strong, with year-to-date totals more than 30 percent higher than at the same point last year.”

Regionally, sales increased compared to June 2017 in China (30.7 percent), the Americas (26.7 percent), Europe (15.9 percent), Japan (14.0 percent), and Asia Pacific/All Other (8.6 percent). Sales also were up compared to last month in China (3.2 percent), Japan (1.3 percent), the Americas (1.2 percent), and Asia Pacific/All Other (0.5 percent), but down slightly in Europe (-0.8 percent).

For comprehensive monthly semiconductor sales data and detailed WSTS Forecasts, consider purchasing the WSTS Subscription Package. For detailed data on the global and U.S. semiconductor industry and market, consider purchasing the 2018 SIA Databook.

By Iris Tsou

The march to greater precision, efficiency and safety – the lifeblood of high-technology manufacturing facilities – has taken on a new urgency as emerging applications such artificial intelligence (AI), the Internet of Things (IoT) and Industry 4.0 give new meaning to smart factories. Facing fiercer competition and ever more sophisticated fabrication processes, semiconductor fabs are under intense pressure to keep pace with new technologies as they work to upgrade. Nowhere are the stakes higher than in Taiwan, where high-tech manufacturing contributes mightily to the region’s GDP growth.

To help Taiwan fabs confront the challenges and opportunities of designing smarter factories, SEMI and its High-Tech Facility Committee hosted the High-Tech Facility Workshop in June. SEMICON Taiwan 2018 High-Tech Facility Pavilion exhibitors gathered to explore how they can build smarter factories by deploying smart surveillance and disaster prevention technologies along with smart communications systems that better use manufacturing data to drive new safety and product quality efficiencies.

During the workshop, SEMI High-Tech Facility Committee representatives shared strides it has made upgrading overseas facilities and developing standards to help establish smart factories in Taiwan.

SEMICON Taiwan – 5-7 September at Taipei’s Nangang Exhibition Center – is also an important event for advancing smart manufacturing in Taiwan. Nearly 30 leading global manufacturers will exhibit at the SEMICON Taiwan High-Tech Facility Pavilion. The venue covers operational aspects of semiconductor manufacturing vital to becoming smarter including energy savings, nano-contamination control, facility information modeling, precision instrumentation and control, fire protection, mechatronics, and automation control. The pavilion will also feature a series of theme events offering a comprehensive overview of topics including the latest practices for integrating smart facility capabilities from the perspective of an advanced fab designer.

At the TechXPOT stage, High-Tech Facility Pavilion exhibitors will also demonstrate the latest technology breakthroughs and cutting-edge smart factor solutions.

The September 6th High-Tech Facility International Forum at SEMICON Taiwan will again gather factory experts and thought leaders from industry and academia to examine “Effective Ways to Make a Facility Smart.“ Experts from industry heavyweights in the fields of wafer foundry, LCD, memory and semiconductor packaging including TSMC, UMC, Innolux, ASE, Micron Taiwan, Winbond and VIS will offer insights into key areas of high-tech facilities including facility electricity, machinery, water management, vaporization and automation systems. On the same day as the forum, the High-Tech Facility Get-Together and High-Tech Facility VIP Dinner will bring together industry elites, academic professionals, and government officials to explore partnership opportunities.

SEMI Taiwan and the High-Tech Facility Committee share HTF market trends information, technology updates and standards with SEMI members and exhibitors.

Founded in 2013, the High-Tech Facility Committee now has 85 corporate members. Dedicated to accelerating industry collaboration through the integration of Taiwan industrial, government and academic resources, the committee each year holds several group meetings focusing on topics including energy savings, earthquake and fire protection, nano-contamination control, and precision instrumentation and control to advance critical technologies and facilitate standardization. The committee also aims to help the industry become more competitive faster by promoting technology standards that boost productivity and reduce production costs.

Please visit www.semi.org and www.semicontaiwan.org for more information about SEMI’s high-tech facility initiatives.

Iris Tsou is a marketing specialist at SEMI Taiwan. 

Originally published on the SEMI blog.

Semiconductor Research Corporation (SRC), today announced the release of $26 million in added research funding for its New Science Team (NST) Joint University Microelectronics Program (JUMP). JUMP will fund 24 additional research projects spanning 14 unique U.S. universities. The new projects will be integrated into JUMP’s six existing research centers. NST will continue to distribute funds over its five-year plan, and industrial sponsors are welcome to join to further accentuate those plans.

The awards have been given to 27 faculty and will enhance the program’s expertise in technical areas such as atomic layer deposition (ALD), novel ferroelectric and spintronic materials and devices, 3D and heterogeneous integration, thermal management solutions, architectures for machine learning and statistical computing, memory abstractions, reconfigurable RF frontends, and mmWave to THz arrays and systems for communications and sensing.

“The goal of the NST project is not only to extend the viability of Moore’s Law economics through 2030, but to also change the research paradigm to one of co-optimization across the design hierarchy stack through multi-disciplinary teams,” said Ken Hansen, President and CEO of Semiconductor Research Corporation. “Our strategic partnerships with industry, academia, and government agencies foster the environment needed to realize the next wave of semiconductor technology innovations.”

“A new wave of fundamental research is required to unlock the ultimate potential of autonomous vehicles, smart cities, and Artificial Intelligence (AI),” said Dr. Michael Mayberry, Senior Vice President and Chief Technology Officer of Intel and the elected Chairman of the NST Governing Council. “Such advances will be fueled by novel and far-reaching improvements in the materials, devices, circuits, architectures, and systems used for computing and communications.”

The JUMP program, a consortium consisting of 11 industrial participants and the Defense Advanced Research Projects Agency (DARPA), is one of two complementary research programs for the NST project—a 5-year, greater than $300 million SRC initiative launched this January. JUMP and its six thematic centers will advance a new wave of fundamental research focused on the high-performance, energy-efficient microelectronics for communications, computing, and storage needs for 2025 and beyond.

North America-based manufacturers of semiconductor equipment posted $2.49 billion in billings worldwide in June 2018 (three-month average basis), according to the June Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI. The billings figure is 8.0 percent lower than the final May 2018 level of $2.70 billion, and is 8.1 percent higher than the June 2017 billings level of $2.30 billion.

“Global billings of North American equipment manufacturers declined for the current month by 8 percent from the historic high but is still 8 percent higher than billings for the same period last year,” said Ajit Manocha, president and CEO of SEMI. “Billings remain robust.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.
Billings
(3-mo. avg)
Year-Over-Year
January 2018
$2,370.1
27.5%
February 2018
$2,417.8
22.5%
March 2018
$2,431.8
16.9%
April 2018
$2,689.9
25.9%
May 2018 (final)
$2,702.3
19.0%
June 2018 (prelim)
$2,485.7
8.1%

Source: SEMI (www.semi.org), July 2018

SEMI publishes a monthly North American Billings report and issues the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) report in collaboration with the Semiconductor Equipment Association of Japan (SEAJ). The WWSEMS report currently reports billings by 24 equipment segments and by seven end market regions. SEMI also has a long history of tracking semiconductor industry fab investments in detail on a company-by-company and fab-by-fab basis in its World Fab Forecast and SEMI FabView databases. These powerful tools provide access to spending forecasts, capacity ramp, technology transitions, and other information for over 1,000 fabs worldwide. For an overview of available SEMI market data, please visit www.semi.org/en/MarketInfo.

Toshiba Memory Corporation today announced that it has developed a prototype sample of 96-layer BiCS FLASH, its proprietary 3D flash memory, with 4-bit-per-cell (quad level cell, QLC) technology that boosts single-chip memory capacity to the highest level yet achieved.

Toshiba Memory will start to deliver samples to SSD and SSD controller manufacturers for evaluation from the beginning of September, and expects to start mass production in 2019.

The advantage of QLC technology is pushing the bit count for data per memory cell from three to four and significantly expanding capacity. The new product achieves the industry’s maximum capacity [1] of 1.33 terabits for a single chip which was jointly developed with Western Digital Corporation.

This also realizes an unparalleled capacity of 2.66 terabytes with a 16-chip stacked architecture in one package. The huge volumes of data generated by mobile terminals and the like continue to increase with the spread of SNS and progress in IoT, and the need to analyze and utilize that data in real time is expected to increase dramatically. That will require even faster than HDD, larger capacity storage and QLC products using the 96-layer process will contribute a solution.

A packaged prototype of the new device will be exhibited at the 2018 Flash Memory Summit in Santa Clara, California, USA from August 6th to 9th.

Looking to the future, Toshiba Memory will continue to improve memory capacity and performance and to develop 3D flash memories that meet diverse market needs, including the fast expanding data center storage market.

Rahul Goyal of Intel has been elected to a one-year term as board chair of Silicon Integration Initiative, a research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. The election was held during Si2’s board meeting at the recent Design Automation Conference.

A member of the Si2 board since 2003, Goyal is vice president, Technology and Manufacturing Group and director, Research and Development Strategic Enabling for Intel. He has global responsibility for strategic sourcing, supply chain strategy, industry relations, ecosystem development, strategic collaborations, data analytics, and capacity management related to product development across Intel’s broad product portfolio. This includes software, system and semiconductor intellectual property, product development outsourcing services, electronic measurement solutions, electronic design automation software, prototyping and verification products used in all aspects of product design, validation and technology development.

Goyal joined Intel in 1989 and has held various technical and management positions in software engineering and technology development. His previous roles there include engineering director in the Design and Technology Solutions Group, director of the integrated silicon technology roadmap development in the Microprocessor Products Group, and senior engineering manager of mask operations.

Goyal holds a bachelor’s degree in electrical and electronics engineering from Birla Institute of Technology and Science, Pilani, India, and a master’s degree in computer engineering from Syracuse University, Syracuse, N.Y.

BY PAUL VAN DER HEIDE, director of materials and components analysis, imec, Leuven, Belgium

To keep up with Moore’s Law, the semiconductor industry continues to push the envelope in developing new device architectures containing novel materials. This in turn pushes the need for new solid-state analytical capabilities, whether for materials characterization or inline metrology. Aside from basic R&D, these capabilities are established at critical points of the semiconductor device manufacturing line, to measure, for example, the thickness and composition of a thin film, dopant profiles of transistor’s source/drain regions, the nature of defects on a wafer’s surface, etc. This approach is used to reduce “time to data”. We cannot wait until the end of the manufacturing line to know if a device will be functional or not. Every process step costs money and a fully functional device can take months to fabricate. Recent advances in instrumentation and computational power have opened the door to many new, exciting analytical possibilities.

One example that comes to mind concerns the development of coherent sources. So far, coherent photon sources have been used for probing the atomic and electronic structure of materials, but only within large, dedicated synchrotron radiation facilities. Through recent developments, table top coherent photon sources have been introduced that could soon see demand in the semiconductor lab/fab environment.

The increased computational power now at our finger tips is also allowing us to make the most of these and other sources through imaging techniques such as ptychography. Ptychog- raphy allows for the complex patterns resulting from coherent electron or photon interaction with a sample to be processed into recognizable images to a resolution close to the sources wavelength without the requirement of lenses (lenses tend to introduce aberrations). Potential application areas extend from non-destructive imaging of surface and subsurface structures, to probing chemical reactions at sub femto-second timescales.

Detector developments are also benefiting many analytical techniques presently used. As an example, transmission electron microscopy (TEM) and scanning transmission electron microscopy (STEM) can now image, with atomic resolution, heavy as well as light elements. Combining this with increased computational power, allows for further devel- opment of imaging approaches such as tomography, holography, ptychography, differential phase contrast imaging, etc. All of which allow TEM/STEM to not only look at atoms in e.g. 2D materials such as MoS2 in far greater detail, but also opens the possibility to map electric fields and magnetic domains to unprecedented resolution.

The semiconductor industry is evolving at a very rapid pace. Since the beginning of the 21st century, we have seen numerous disruptive technologies emerge; technologies that need to serve is an increasingly fragmented applications space. It’s no longer solely about ‘the central processing unit (CPU)’. Other applications ranging from the internet of things, autonomous vehicles, wearable human-electronics interface, etc., are being pursued, each coming with unique requirements and analytical needs.

Looking ten to fifteen years ahead, we will witness a different landscape. Although I’m sure that existing techniques such as TEM/STEM will still be heavily used – probably more so than we realize now (we are already seeing TEM/STEM being extended into the fab). We will also see developments that will push the boundaries of what is possible. This would range from the increased use of hybrid metrology (combining results from multiple different analytical techniques and process steps) to the development of new innovative approaches.

To illustrate the latter, I take the example of secondary ion mass spectrometry (SIMS). With SIMS, an energetic ion beam is directed at the solid sample of interest, causing atoms in the near surface region to leave this surface. A small percentage of them are ionized, and pass through a mass spectrometer which separates the ions from one another according to their mass to charge ratio. When this is done in the dynamic-SIMS mode, a depth profile of the sample’s composition can be derived. Today, with this technique, we can’t focus the incoming energetic ion beam into a confined volume, i.e. onto a spot that approaches the size of a transistor. But at imec, novel concepts were intro- duced, resulting in what are called 1.5D SIMS and self-focusing SIMS (SF-SIMS). These approaches are based on the detection of constituents within repeatable array structures, giving averaged and statistically significant information. This way, the spatial resolution limit of SIMS was overcome.

And there are exciting developments occurring here at imec in other analytical fields such as atom probe tomography (APT), photoelectron spectroscopy (PES), Raman spectroscopy, Rutherford back scattering (RBS), scanning probe microscopy (SPM), etc. One important milestone has been the development of Fast Fourier Transform-SSRM (FFT-SSRM) at imec. This allows one to measure carrier distributions in FinFETs to unparalleled sensitivity.

Yet, probably the biggest challenge materials characterization and inline metrology face over the next ten to fifteen years will be how to keep costs down. Today, we make use of highly specialized techniques developed on mutually exclusive and costly platforms. But why not make use of micro-electro-mechanical systems (MEMS) that could simultaneously perform analysis in a highly parallel fashion, and perhaps even in situ? One can imagine scenarios in which an army of such units could scan an entire wafer in the fraction of the time it takes now, or alternatively, the incorporation of such units into wafer test structure regions.

The development of a new class of materials with superior functionalities is essential to enable emerging process schemes for wafer- or panel-level FO packaging.

BY KIM YESS, Director of Technology Development, Wafer-Level Packaging Business Unit Brewer Science, Rolla, MO

Fan-out (FO) packaging is one of the most talked- about advanced packaging solutions for heterogeneous integration. Although it has been available for nearly a decade for the chips used in mobile devices, its popularity has spiked in the past two years, thanks to Apple’s adoption of TSMC’s integrated fan-out package-on-package (InFO PoP) for its A10 and A11 processors, and the Apple Watch. As a result, FO has quickly progressed to the mainstream, with outsourced semiconductor and test service providers (OSATs), foundries and integrated device manufacturers (IDMs) vying for market share.

What’s driving FO innovation?

According to Yole Développement, smartphone appli- cation processors are the main beneficiaries of high- density fan-out (HDFO)’s excellent performance and thin profile. As a result, as shown in FIGURE 1, the HDFO market was worth $500 million in 2017 and was predicted to exceed $1 billion if other players, namely Qualcomm, Samsung and Huawei switch to HDFO [1].

Jan Vardaman, TechSearch International, said Apple selected InFO PoP for its A10 processor because of power noise reduction and signal integrity improvement, in addition to being thin enough to enable a low-profile PoP solution as small as 15 x 15 mm.

In addition to HDFO, the market is growing for conventional FO, driven by new applications such as audio CODECs, power management ICs, radar modules and RF[2].

The automotive electronics market—particularly advanced driver assistance systems (ADAS) and autonomous vehicles—is also being explored as a viable application for FO because of the flexibility and fast time to market it provides, as well as the ability to adapt to new sensor system protocols.

Exploring new processes

In this race to provide the most reliable, highest-density solution, many manufacturing approaches have emerged. FO is not only becoming more versatile, it is also reaching high enough densities to offer a cost-effective alternative to 2.5D interposers. As the demand for FO increases, packaging processes are being explored in both the wafer and panel formats. This is driving a need for new and better-performing materials that address more stringent specifications to meet, for example, finer line and space requirements, as well as the improved elongation needed for advanced high-density FO.

Thanks to recent innovations in packaging materials, three new process approaches have been developed to bridge these gaps. One approach involves new carrier- assist release-layer materials for creation of the redistribution layer (RDL)-first/chip-last buildup processes. Another important development is an alternative to lithography dielectric patterning that uses laser-ablated dielectric materials. Lastly, an alternative to the molding process in the chip-first approach that uses a laminated die stencil and gap-fill materials is under development.

Carrier-assist release layer for chip-last FO

Low-density FO is built using a chip-first approach, which involves first placing the chips on a substrate wafer followed by over-mold to create a reconstituted wafer, with subsequent RDL and solder-ball placement. On the other hand, HDFO processes like TSMC’s InFO technology use a chip-last approach. Also known as RDL-first, this approach (with target features of ≤2 μm l/s) begins with a layer-by-layer buildup of the RDL on a carrier wafer, followed by die placement and over-mold.

Currently, manufacturers turn to permanent bonding, followed by backgrinding to remove the carrier wafer. This is because conventional temporary bond/debond materials cannot withstand the downstream RDL processes that subject the build-up layers to high temperatures and vacuum conditions, as well as harsh chemical environments. However, backgrinding is a destructive process, creating debris that can cause damage to the device itself.

The new approach uses neither a temporary nor a permanent bonding process. Instead, it utilizes a release layer on the carrier substrate to allow separation of the FO wafer from the carrier at the end of the process flow.

The challenge with this new method is designing a material that withstands high- temperature process steps as well as strong mechanical stresses without delaminating or distorting the reconstituted wafer. Additionally, the material must be adaptable to the new FO panel-level processes (FOPLP) along with existing round wafers, as the industry innovates in that direction.

Manufacturers are investigating the use of copper foil lamination, as an alternative to physical vapor deposition of the seed layer. The copper laminating process requires a material that is flexible enough to sufficiently laminate layers on top of the substrate, and that can be cured using UV radiation or heat to yield a structurally stable base that meets the thermomechanical and chemical resis- tance requirements of the build-up process.

Additionally, it must be releasable by ultraviolet(UV) laser ablation or other UV exposure. To meet these needs, a new class of so-called “triangle” polymeric materials has been conceived that have advantages over standard-application release layers because they are multi functional. Specifically, these “triangle” materials can be laminated, cured and debonded, adding flexibility to the carrier-assisted process (FIGURE 2).

Dielectric RDL patterning

Traditional RDL patterning uses a complicated, 24-step photolithography process that employs photosensitive dielectric materials and masks to create trace patterns, followed by Cu plating to route the signal from the chip out of the package to the solder balls. This process, developed with round wafers in mind, uses spin-coated dielectrics. Unfortunately, these lithography processes are too costly to utilize in innovative package designs that must meet the stringent requirements for most markets [3].

As the industry moves to HDFO and begins to investigate panel-level processes to reduce cost and improve yield, alternative patterning approaches are being developed that can achieve resolutions down to 5 μm with an ultimate goal of 2 μm l/s. Laser ablation is one alter- native to photolithography for creating finer-featured RDL patterns while achieving all these goals.

The combination of a high-power excimer laser source, large-field laser mask and precision projection optics enables the accurate replication and placement of fine resolution circuit patterns without the need for any wet processing. In addition, with excimer laser patterning technology, the industry gains a much wider choice of dielectric materials (photopatternable and non-photopatternable) to help achieve further reductions in manufacturing costs as well as enhancements in chip or package performance [4].

By using excimer laser ablation, many process steps and costly materials can be eliminated from the manufacturing flow, including resist coating, baking, developing and resist stripping and etching using harsh chemicals [5].

FIGURE 3 demonstrates the considerable cost savings of laser ablation over photolithography. Activity-based cost modeling was used to carry out the cost comparison between the two processes. With activity-based cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is calculated. The cost of each activity is determined by analyzing the following attributes: time, amount of labor and cost of material required (consumable and permanent), tooling cost, all capital costs, and yield loss associated with the activity.

Laser-ablated patterning is a room-temperature process that works by using a dielectric material to build up RDL fixtures, and excimer and solid-state lasers to ablate the material and direct-write a pattern. Laser ablation allows for depth and side-wall angle control, making it possible to create feature sizes <5 μm. It also reduces chemical waste streams. Additionally, fewer steps, fast removal rates and high throughput lead to a lower-cost solution in comparison with traditional photolithography (Fig. 3).

Photosensitive dielectric materials often fall short of meeting the required mechanical and thermal properties, and therefore need a variety of process “work-arounds” that add to the cost of ownership. Alter- natively, non-photopatternable dielectric materials can be designed using a vast selection of chemical platforms, which improves the possibility of meeting the thermal and mechanical property requirements.

As with all new approaches, laser ablation is not without some challenges. Post-laser-ablation cleaning and debris removal, along with surface roughness as a result of the ablation step, need to be addressed. Additionally, the laser system needs to achieve a high ablation rate for high throughput. While the process costs of laser ablation are lower than photolithography, there is still a significant equipment capacity investment required to add laser tools to the manufacturing line. This may delay overcoming the most critical challenge: convincing the industry to embrace laser ablation patterning over conventional approaches.

Development of the dielectric material is ongoing to further push the resolution of laser-ablated materials. In addition to spin and spray coating, other deposition methods being investigated include slot-die coating, ink-jet printing, Vermeer coating, spray coating and laminate film.

Laminated polymeric die-stencil fill concept

Chip-first is the standard approach for conventional FO packages, including embedded wafer level ball grid arrays (eWLBs), redistributed chip packages (RCPs), M-Series and others. It calls for placing die into the mold compound before the RDL processing steps. One of the challenges of this approach that impacts final yield is the die shift that can occur during the RDL processes. Additionally, in multi-die FOWLP configurations that combine disparate technologies to essen- tially form a system-in-package (SiP), the dies may be of different sizes and heights. Additionally, the mismatch in coefficient of thermal expansion (CTE) between all of the materials involved leads to severe warpage of the reconstituted wafer.

A new carrier-based approach developed to combat this problem replaces the over-mold structure around the dies with a laminated die stencil (FIGURE 4). A release layer is first applied to a carrier, followed by a curable adhesive backing layer. Next, the die stencil film is laminated to the curable adhesive backing layer. The dies are then placed in the stencil openings and attached to the adhesive backing layer during thermal curing. The gaps between the dies and stencil are then filled with a flexible yet curable polymeric material, yielding a stable reconstituted substrate. This is followed by construction of the RDLs while still supported on the carrier. Finally, the reconsti- tuted substrate is released from the carrier.

The stencil can be fabricated as a sheet from a variety of high-temperature-stable thermoplastics including, for example, carbon-fiber-filled polyetheretherketone (PEEK), which has an in-plane CTE of <10 ppm/K.

The pre-formed cavities can be configured for different die sizes and types to fabricate SiP components. The curable adhesive backing layer is comparatively soft and tacky before it is cured. This property allows the die-stencil film to be laminated to the structure at low temperatures.

This process not only addresses the die shift issue that plagues the chip-first approach, it also enables varying levels of die thickness. When placed in the stencil, the polymeric material allows the dies to sink and adjusts itself within the stencil. Once the dies are set, the material is cured, which locks them in place. Additionally, the process offers high-temperature stability, better CTE matching for warpage control, and high throughput.

Summary and conclusion

Fan-out packaging is on track to be a game-changing advanced packaging technology that will enable heterogeneous integration architectures. Applications have already expanded beyond smartphones, with HDFO targeting emerging applications.

Substrate handling and RDL strategies will be increasingly important, if not critical, for both conventional and HDFO technologies. To this end, the development of a new class of materials with superior functionalities is essential to enable emerging process schemes for wafer- or panel-level FO packaging.

The gamut of application needs for wafer support includes simple thinning processes during the backside processing of ultrathin, 300-mm silicon wafers, as well as reconstituted substrates for RDL fabrication. In addition to new materials, novel manufacturing approaches are also needed to further optimize the FO process flow.

KIM YESS is Director of Technology Development, Wafer-Level Packaging Business Unit Brewer Science, Rolla, MO

Acknowledgements

The author would like to thank Amy Lujan, SavanSys, for her contribution to this article regarding activity- based cost modeling.

References

1. Yole Developpement, “Fan-out Packaging Confirms its Success Story,” 3D InCites, September 14, 2017.
2. P. Garrou, “ITLE 356 SEMI Taiwan Part 1: Fan-out Packaging Players, Applications, and Market Growth,” Solid State Technology, October 2017.
3. H.Hichri,M.Arendt,andM.Gingerella,“Novel Process of RDL Formation for Advanced Packaging by Excimer Laser Ablation,” 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, 2016, pp. 1733-1739. doi: 10.1109/ECTC.2016.225
4. H. Hichri, Ibid.
5. R. Zoberbier, M. Souter, “Laser Ablation, Emerging Patterning Technology for Advanced Packaging,” SUSS MicroTec Lithography GmbH, January 2010

Optimized stepping, based on parallel analysis of die placement errors and prediction of overlay errors, can increase lithography throughput by more than an order of magnitude and deliver commensurate reductions in cost of ownership. The productivity benefits of optimized stepping are demonstrated using a test reticle with known die placement errors.

KEITH BEST, Director of Lithography Applications Engineering, Rudolph Technologies, Inc., Wilmington, Mass.

Fan out wafer and panel level packaging (FOWLP/ FOPLP) processes place individual known good die on reconstituted wafer (round) or panel (rectangular) substrates, providing more space between die than the original wafer. The additional space is used to expand (fanout) the die’s I/O connections in order to create a pad array large enough to accommodate solder balls that will connect the die to the end-use substrate.The processes used to create these redistribution layers (RDL) are similar to wafer fabrication processes, using patterns defined by photolithography, with feature sizes typically ranging from a few micrometers to tens of micrometers. The placement and reconstitution molding processes introduce significant die placement errors that must be corrected in the photolithography process to ensure accurate overlay registration among the multiple vias and distribution layers that are built up to form the RDL. The errors can be measured on the lithography tool, but this significantly impacts throughput as the measurement process for each die may take as much or more time than the exposure itself.

Current best-practice methods employ an external metrology system to measure the displacement of each die. This metrology data is converted into a stepper correction file that is sent to the lithography stepper tool, eliminating the need to measure displacement on the stepper and more than doubling stepper throughput. An important enhancement to this method, optimized stepping, varies the number of die per exposure based on a predictive yield analysis of the displacement measurements, potentially multiplying throughput 20X or more. Results obtained using a test reticle that includes intentionally displaced die pads, vias, and RDL features typical of an FOWLP/FOPLP process confirm the validity of the approach.

Introduction

Die placements on reconstituted wafer or panel substrates include translational and rotational placement errors. The pick and place process itself introduces initial error. Additional error is created in the mold process and by instability of the mold compound through repeated processing cycles. As a result, the position of the die must be measured before each exposure in the lithog- raphy system to ensure sufficient registration with the underlying layer.

Displacement errors can be measured in the lithography tool, but the measurements are slow, typically taking as much time as the exposure. Moving the measurement to a separate system and feeding corrections to the stepper can double throughput.

Optimized stepping adds predictive yield analysis to the external measurement and correction procedures and increases the number of die included in the exposure field up to a user-specified yield threshold. FIGURE 1 illustrates the exposure/measurement loop. The measurement and analysis are repeated after each layer is exposed, calculating a new set of corrections. In addition to corrections, the software engine analyzes the displacement errors to predict yield (based on a user desig- nated limit for acceptable registration error) for multiple die exposure fields of varying sizes. The method requires tight integration of the stepper and measurement system with the controlling software.

With RDL features currently reaching sizes as small as 2μm, die placement measurements and pattern overlay registration requirements are also continuing to tighten. The speed of the measurement/correction/prediction calculation for each wafer/panel is also an important consideration. It must be faster than the exposure time to avoid becoming the throughput limiting step. Note that this requirement refers to the total exposure for multiple die per field which can be much less than the time needed to expose each die individually. The metrology system used in this work (Firefly system, Rudolph Technologies) can meet these challenges and measure placement errors for >5,000 die on a 510mm x 515mm panel in less than 10 minutes.

The stepper must be able to accept externally generated corrections for translation, rotation, and magnification.

It must also have a large exposure field and the ability to automatically select different images from the reticle (masking blades), changing the size of the field for each exposure. The stepper used in this work was the JetStep system from Rudolph Technologies.

The third critical piece of the optimized stepping loop is the software engine (Discover software, Rudolph Technol- ogies) which calculates displacement corrections and predicts yield for various multi-die exposure configura- tions. It also enables statistical process control (SPC) and controls genealogy.

Balancing yield and throughput

Optimized stepping uses a reticle that includes multiple exposure fields each comprising die arrays of different sizes. In FIGURE 2 the arrays range from a single die to an 8 X 8 array of 64 die. On a wafer containing random displacement errors, the smallest overlay error will be achieved by aligning the exposure pattern for each die individually. However, this accuracy comes at a high cost of reduced throughput. Optimized stepping analyzes the measured displacement errors and calculates the number of die that will meet a designated overlay error limit for various field sizes. It then selects the combination of fields that maximizes throughput. In operation, the stepper automatically selects the correct reticle image and adjusts the field size to expose the selected array.

The yield prediction algorithm (FIGURE 3) uses a recursive splitting procedure that initially predicts yield for the largest available field. If the prediction does not meet user-defined yield requirements, it splits the field and re-evaluates the prediction, repeating this cycle for decreasing field sizes until all exposures yield satisfactory results. The user designates an aggressiveness factor (larger values mean more aggressive splits) and specifies yield requirements in an exposure shot pyramid that determines the number of failures allowed for each available field size.

Results

Optimized stepping was evaluated using a test reticle with multiple field sizes containing die that included pads, vias and RDL structures typical of FOWLP/FOPLP. The patterns included predefined offsets in some of the structures for feed forward measurement testing. Application of the corrections calculated from the die placement error measurements yielded overlay errors of < +/-3μm (FIGURE 4).

Productivity vs. yield

FIGURE 5 illustrates the potential benefits of optimized stepping applied to a panel process. In the example the panel contains approximately 4,500 die. A conventional serial process, with placement errors measured on the stepper, takes a little over six hours, including three hours for measurement and three hours for exposure. Making the measurements outside the stepper in parallel with the exposure halves the cycle time per panel to three hours, and the exposure time becomes the throughput limiting step. The third case is optimized for productivity, using larger field sizes and more relaxed yield requirements. It reduces cycle time to less than 10 minutes. The final case balances throughput against more stringent yield require- ments and results slightly higher cycle times that are still nearly an order of magnitude shorter than the conventional serial process of the first case.

Conclusion

Optimized stepping can increase lithography throughput by more than an order of magnitude and deliver commensurate reductions in cost of ownership. The method also provides a means to balance productivity (throughput) against yield, adding an extra dimension of flexibility for optimizing profitability. Optimized stepping requires a stepper that can use externally calculated corrections and automatically change field size and reticle position. The metrology system must have sufficient accuracy and speed (faster than the accelerated exposure time). The control software must be able to predict yields based on measured displacement errors and control the stepper. Using a test reticle with known displacement errors, we have verified the accuracy of the metrology system and correction procedures and demonstrated the productivity benefits of optimized stepping.

KEITH BEST is Director of Lithography Applications Engineering, Rudolph Technologies, Inc., Wilmington, Mass.

Market shares of semiconductor equipment manufacturers shifted significantly in Q1 2018 as Applied Materials, the top supplier dropped, according to the report “Global Semiconductor Equipment: Markets, Market Shares, Market Forecasts,” recently published by The Information Network, a New Tripoli-based market research company.

The chart below shows shares for the first quarter (Q1) of calendar year 2017 and 2018. Market shares are for equipment only, excluding service and spare parts, and have been converted for revenues of foreign companies to U.S. dollars on a quarterly exchange rate.

Applied Materials lost significant market share YoY, from 18.4% of the $13.1 billion Q1 2017 market to 17.7% of the $17.0 billion Q1 2018 market. This drop follows a 1.8 share-point loss by Applied Materials for CY 2017 compared to 2016. The company competes with Lam Research and TEL in the deposition and etch market, and both gained share at the expense of Applied Materials.

At the other end of the spectrum, smaller semiconductor companies making up the “other” category lost 2.4 share points as a whole.

Much of the equipment revenue growth was attributed to strong growth in the DRAM and NAND sectors, as equipment was installed in memory manufacturers Intel, Micron Technology, Samsung Electronics, SK Hynix, Toshiba, and Western Digital. The memory sector, which grew grown 61.5% in 2017, is forecast to add another 28.5% in 2018 according to industry consortium WSTS (World Semiconductor Trade Statistics).

TEL recorded growth of 120.3% YoY in Korea, much of it on NAND and DRAM sales to Samsung Electronics and SK Hynix, and 69.5% YoY in Japan, much of it on NAND sales to Toshiba at its Fab 6 in Kitakami, Japan. Lam Research gained 42.2% and 70.5% YoY, respectively, in Korea and Japan.

Following the strong growth in the semiconductor equipment market, The Information Network projects another 11.5% growth in 2018 for semiconductor equipment.