Category Archives: Wafer Level Packaging

Semiconductor Research Corporation (SRC) announced today that Ken Hansen has been appointed SRC’s new President and Chief Executive Officer (CEO), effective June 1.

Hansen’s professional experience includes serving as Vice President and Chief Technology Officer (CTO) at Freescale Semiconductor since 2009. Hansen replaces retiring SRC President and CEO Larry Sumney who guided the organization for more than 30 years since its inception in 1982. SRC’s many accolades over the years include being the recipient of the National Medal of Technology in 2007.

“SRC under Larry Sumney’s leadership has made an indelible impact on the advancement of technology during the past three decades, and we congratulate Larry on his retirement and salute him for his contributions to the semiconductor industry,” said Mike Mayberry, Intel Corporate Vice President and Director of Components Research who is SRC Board Chairman. “We also welcome Ken Hansen to his new role guiding SRC, and we look forward to Ken’s leadership helping SRC reach new heights in an era where basic research and development is as critical as ever.”

Prior to his CTO role at Freescale, Hansen led research and development teams for more than 30 years in multiple senior technology and management positions at Freescale and Motorola. Hansen holds Bachelor and Master of Science degrees in Electrical Engineering from the University of Illinois where he has been recognized as an ECE (Department of Electrical and Computer Engineering) Distinguished Alumni.

In his new role at SRC, Hansen intends to build on the consortium’s mission of driving focused industry research to both advance state-of-the-art technology and continue to create a pipeline of qualified professionals who will serve as next-generation leaders for the industry.

“SRC also has an opportunity to strengthen its core by recruiting new members to gain more leverage to fund industry wide solutions for some of the challenging technology roadblocks that are ahead of us,” said Hansen.

“The model that SRC has developed is unmatched in the industry and has proven to be extremely significant. The industry would not be where it is today without the contributions of SRC under the leadership and vision of Larry Sumney,” Hansen continued.

Meanwhile, Sumney’s decorated career began in 1962 at the Naval Research Laboratory. He later directed various other research programs at Naval Electronics Systems Command and the Office of the Undersecretary of Defense — including the Department of Defense’s major technology initiative, Very High Speed ICs (VHSIC) —before agreeing to lead SRC following its formation by the Semiconductor Industry Association.

Under his leadership, SRC has also formed wholly owned subsidiaries managing the Nanoelectronics Research Initiative (NRI), the Semiconductor Technology Advanced Research network (STARnet) and the SRC Education Alliance, among other programs. Sumney received a Bachelor of Physics from Washington and Jefferson (W&J) College, which recognized him with the 2012 Alumni Achievement Award, and a Master of Engineering Administration from George Washington University.

“I have enjoyed a front row seat in the development of today’s technology-based economy and advancement of humanity through the semiconductor industry,” said Sumney. “I am completely confident that SRC is well positioned and will continue to flourish, to seed breakthrough innovation and help provide the people and ideas to keep the U.S. semiconductor industry competitive and prosperous in years to come.”

Additional industry leaders with strong ties to SRC commended Sumney for his service over the years while supporting Hansen’s appointment.

“Over more than 30 years, Larry Sumney’s visionary leadership of SRC has steered one of the world’s most transformative industries through times of tremendous growth and innovation,” said John Kelly, Senior Vice President, Solutions Portfolio and Research for IBM.  “I’ll personally miss working with Larry, but also have tremendous respect for and confidence in Ken Hansen, and we look forward to collaborating with him to drive the next generation of research in this vital industry.”

“Larry’s leadership and vision are key reasons why SRC’s research has played a fundamental role behind many of the most significant semiconductor innovations of the last three decades,” said Lisa Su, AMD president and CEO and a former SRC student. “Ken’s broad industry experience makes him ideally suited to lead the next phase of the SRC, as the organization continues to expand its capabilities and provide the basic research and development foundation needed to further accelerate innovation across the industry.”

IBM today announced a significant milestone in the development of silicon photonics technology, which enables silicon chips to use pulses of light instead of electrical signals over wires to move data at rapid speeds and longer distances in future computing systems.

For the first time, IBM engineers have designed and tested a fully integrated wavelength multiplexed silicon photonics chip, which will soon enable manufacturing of 100 Gb/s optical transceivers. This will allow datacenters to offer greater data rates and bandwidth for cloud computing and Big Data applications.

“Making silicon photonics technology ready for widespread commercial use will help the semiconductor industry keep pace with ever-growing demands in computing power driven by Big Data and cloud services,” said Arvind Krishna, senior vice president and director of IBM Research. “Just as fiber optics revolutionized the telecommunications industry by speeding up the flow of data — bringing enormous benefits to consumers — we’re excited about the potential of replacing electric signals with pulses of light. This technology is designed to make future computing systems faster and more energy efficient, while enabling customers to capture insights from Big Data in real time.”

Silicon photonics uses tiny optical components to send light pulses to transfer large volumes of data at very high speed between computer chips in servers, large datacenters, and supercomputers, overcoming the limitations of congested data traffic and high-cost traditional interconnects. IBM’s breakthrough enables the integration of different optical components side-by-side with electrical circuits on a single silicon chip using sub-100nm semiconductor technology.

IBM’s silicon photonics chips uses four distinct colors of light travelling within an optical fiber, rather than traditional copper wiring, to transmit data in and around a computing system. In just one second, this new transceiver is estimated to be capable of digitally sharing 63 million tweets or six million images, or downloading an entire high-definition digital movie in just two seconds.

The technology industry is entering a new era of computing that requires IT systems and cloud computing services to process and analyze huge volumes of Big Data in real time, both within datacenters and particularly between cloud computing services. This requires that data be rapidly moved between system components without congestion. Silicon photonics greatly reduces data bottlenecks inside of systems and between computing components, improving response times and delivering faster insights from Big Data.

IBM’s new CMOS Integrated Nano-Photonics Technology will provide a cost-effective silicon photonics solution by combining the vital optical and electrical components, as well as structures enabling fiber packaging, on a single silicon chip. Manufacturing makes use of standard fabrication processes at a silicon chip foundry, making this technology ready for commercialization.

Silicon photonics technology leverages the unique properties of optical communications, which include transmission of high-speed data over kilometer-scale distances, and the ability to overlay multiple colors of light within a single optical fiber to multiply the data volume carried, all while maintaining low power consumption. These characteristics combine to enable rapid movement of data between computer chips and racks within servers, supercomputers, and large datacenters, in order to alleviate the limitations of congested data traffic produced by contemporary interconnect technologies.

Silicon photonics will transform future datacenters

By moving information via pulses of light through optical fibers, optical interconnects are an integral part of contemporary computing systems and next generation datacenters. Computer hardware components, whether a few centimeters or a few kilometers apart, can seamlessly and efficiently communicate with each other at high speeds using such interconnects. This disaggregated and flexible design of datacenters will help reduce the cost of space and energy, while increasing performance and analysis capabilities for users ranging from social media companies to financial services to universities.

Most of the optical interconnect solutions employed within datacenters as of today are based upon vertical cavity surface emitting laser (VCSEL) technology, where the optical signals are transported via multimode optical fiber. Demands for increased distance and data rate between ports, due to cloud services for example, are driving the development of cost-effective single-mode optical interconnect technologies, which can overcome the bandwidth-distance limitations inherent to multimode VCSEL links.

IBM’s CMOS Integrated Nano-Photonics Technology provides an economical solution to extend the reach and data rates of optical links. The essential parts of an optical transceiver, both electrical and optical, can be combined monolithically on one silicon chip, and are designed to work with with standard silicon chip manufacturing processes.

IBM engineers in New York and Zurich, Switzerland and IBM Systems Unit have demonstrated a reference design targeting datacenter interconnects with a range up to two kilometers. This chip demonstrates transmission and reception of high-speed data using four laser “colors,” each operating as an independent 25 Gb/s optical channel. Within a full transceiver design, these four channels can be wavelength multiplexed on-chip to provide 100 Gb/s aggregate bandwidth over a duplex single-mode fiber, thus minimizing the cost of the installed fiber plant within the datacenter.

Further details will be presented by IBM at the 2015 Conference on Lasers and Electro Optics (May 10-15) in San Jose, California, during the invited presentation entitled “Demonstration of Error Free Operation Up To 32 Gb/s From a CMOS Integrated Monolithic Nano-Photonic Transmitter,” by Douglas M. Gill, Chi Xiong, Jonathan E. Proesel, Jessie C. Rosenberg, Jason Orcutt, Marwan Khater, John Ellis-Monaghan, Doris Viens, Yurii Vlasov, Wilfried Haensch, and William M. J. Green.

IBM Research has been leading the development of silicon photonics for more than a decade, announcing a series of technology milestones beginning in 2006. Silicon photonics is among the efforts of IBM’s $3 billion investment to push the limits of chip technology to meet the emerging demands of cloud and Big Data systems.

Interconnecting transistors and other components in the IC, in the package, on the printed circuit board and at the system and global network level, are where the future limitations in performance, power, latency and cost reside.

BY BILL CHEN, ASE US, Sunnyvale, CA; BILL BOTTOMS, 3MT Solutions, Santa Clara, CA, DAVE ARMSTRONG, Advantest, Fort Collins, CO; and ATSUNOBU ISOBAYASHI, Toshiba Kangawa, Japan.

Heterogeneous Integration refers to the integration of separately manufactured components into a higher level assembly that in the aggregate provides enhanced functionality and improved operating characteristics.

In this definition components should be taken to mean any unit whether individual die, MEMS device, passive component and assembled package or sub‐system that are integrated into a single package. The operating characteristics should also be taken in its broadest meaning including characteristics such as system level cost-of-ownership.

The mission of the ITRS Heterogeneous Integration Focus Team is to provide guidance to industry, academia and government to identify key technical challenges with sufficient lead time that they do not become roadblocks preventing the continued progress in electronics that is essential to the future growth of the industry and the realization of the promise of continued positive impact on mankind. The approach is to identify the require- ments for heterogeneous integration in the electronics industry through 2030, determine the difficult challenges that must be overcome to meet these requirements and, where possible, identify potential solutions.

Background

The environment is rapidly changing and will require revolutionary changes after 50 years where the change was largely evolutionary. The major factors driving the need for change are:

  • We are approaching the end of Moore’s Law scaling.
  • The emergence of 2.5D and 3D integration techniques
  • The emerging world of Internet of Everything will cause explosive growth in the need for connectivity.
  • Mobile devices such as smartphones and tablets are growing rapidly in number and in data communications requirements, driving explosive growth in capacity of the global communications network.
  • Migration of data, logic and applications to the cloud drives demand for reduction in latency while accommodating this network capacity growth.

Satisfying these emerging demands cannot be accomplished with the current electronics technology and these demands are driving a new and different integration approach. The requirements for power, latency, bandwidth/bandwidth density and cost can only be accomplished by a revolutionary change in the global communications network, with all the components in that network and everything attached to it. Ensuring the reliability of this “future network” in an environment where transistors wear out, will also require innovation in how we design and test the network and its components.

The transistors ‘power consumption in today’s network account for less than 10 percent of total power, total latency and total cost. It is the interconnection of these transistors and other components in the IC, in the package, on the printed circuit board and at the system and global network level, where the future limitations in performance, power, latency and cost reside. Overcoming these limitations will require heterogeneous integration of different materials, different devices (logic, memory, sensors, RF, analog, etc.) and different technologies (electronics, photonics, plasmonics, MEMS and sensors). New materials, manufacturing equipment and processes will be required to accomplish this integration and overcome these limitations.

Difficult challenges

The top‐level difficult challenges will be the reduction of power per function, cost per function and latency while continuing the improvements in performance, physical density and reliability. Historically, scaling of transistors has been the primary contributor to meeting required system level improvements. Heterogeneous integration must provide solutions to the non‐transistor infrastructure that replace the shortfall from the historical pace of progress we have enjoyed from scaling CMOS. Packaging and test have found it difficult to scale their performance or cost per function to keep pace with transistors and many difficult challenges must be met to maintain the historical pace of progress.

In order to identify the difficult challenges we have selected seven application areas that will drive critical future requirements to focus our work. These areas are:

  • Mobile products
  • Big data systems and interconnect
  • The cloud
  • Biomedical products
  • Green technology
  • Internet of Things
  • Automotive components and systems

An initial list of difficult challenges for Heterogeneous Integration for these application areas is presented in three categories; (1) on‐chip interconnect, (2) assembly and packaging and (3) test. These are analyzed in line with the roadmapping process and will be used to define the top 10 challenges that have the potential to be “show stoppers” for the seven application areas identified above.

On-chip interconnect difficult challenges

The continued decrease in feature size, increase in transistor count and expansion into 3D structures are presenting many difficult challenges. While challenges in continuous scaling are discussed in the “More Moore” section, the difficult challenges of interconnect technology in devices with 3D structures are listed here. Note that this assumes a 3D structure with TSV, optical interconnects and passive devices in interposer substrates.

ESD (Electrostatic Discharge): Plasma damage on transistors by TSV etching especially on via last scheme. Low damage TSV etch process and the layout of protection diodes are the key factors.

CPI (Chip Package Interaction) Reliability [Process]: Low fracture toughness of ULK (Ultra Low‐k) dielectrics cause failures such as delamination. Material development of ULK with higher modulus and hardness are the key factors.

CPI (Chip Package Interaction) Reliability [Design]: A layout optimization is a key for the device using Cu/ULK structure.

Stress management in TSV [Via Last]: Yield and reliability in Mx layers where TSV land is a concern.

Stress management in TSV [Via Middle]: Stress deformation by copper extrusion in TSV and a KOZ (Keep Out Zone) in transistor layout are the issues.

Thermal management [Hot Spot]: Heat dissipation in TSV is an issue. An effective homogenization of hot spot heat either by material or layout optimization are the key factors.

Thermal management [Warpage]: Thermal expansion management of each interconnect layer is necessary in thinner Si substrate with TSV.

Passive Device Integration [Performance]: Higher Q, in other words, thicker metal lines and lower tan dielectrics is a key for achieving lower power and lower noise circuits.

Passive Device Integration [Cost]: Higher film and higher are required for higher density and lower footprint layout.

Implementation of Optical Interconnects: Optical interconnects for signaling, clock distribution, and I/O requires development of a number of optical components such as light sources, photo detectors, modulators, filters and waveguides. On‐chip optical interconnects replacing global inter- connects requires the breakthrough to overcome the cost issue.

Assembly and packaging difficult challenges

Today assembly and packaging are often the limiting factors in performance, size, latency, power and cost. Although much progress has been made with the introduction of new packaging architectures and processes, with innovations in wafer level packaging and system in package for example, a significantly higher rate of progress is required. The complexity of the challenge is increasing due to unique demands of heterogeneous integration. This includes integration of diverse materials and diverse circuit fabric types into a single SiP architecture and the use of the 3rd dimension.

Difficult packaging challenges by circuit fabric

  • Logic: Unpredictable hot spot locations, high thermal density, high frequency, unpredictable work load, limited by data bandwidth and data bottle‐necks. High bandwidth data access will require new solutions to physical density of bandwidth.
  • Memory: Thermal density depends on memory type and thermal density differences drive changes in package architecture and materials, thinned device fault models, test & redundancy repair techniques. Packaging must support low latency, high bandwidth large (>1Tb) memory in a hierar- chical architecture in a single package and/or SiP).
  • MEMS: There is a virtually unlimited set of requirements. Issues to be addressed include hermetic vs. non‐hermetic, variable functional density, plumbing, stress control, and cost effective test solutions.
  • Photonics: Extreme sensitivity to thermal changes, O to E and E to O, optical signal connections, new materials, new assembly techniques, new alignment and test techniques.
  • Plasmonics: Requirements are yet to be determined, but they will be different from other circuit type. Issues to be addressed include acousto‐ magneto effects and nonlinear plasmonics.
  • Microfluidics: Sealing, thermal management and flow control must be incorporated into the package.

Most if not all of these will require new materials and new equipment for assembly and test to meet the 15 year Roadmap requirements.

Difficult packaging challenges by material

Semiconductors: Today the vast majority of semiconductor components are silicon based. In the future both organic and compound semiconductors will be used with a variety of thermal, mechanical and electrical properties; each with unique mechanical, thermal and electrical requirements.

Conductors: Cu has replaced Au and Al in many applications but this is not good enough for future needs. Metal matrix composites and ballistic conductors will be required. Inserting some of these new materials will require new assembly, contacting and joining techniques.

Dielectrics: New high k dielectrics and low k dielectrics will be required. Fracture toughness and interfacial adhesion will be the key parameters. Packaging must provide protection for these fragile materials.

Molding compound: Improved thermal conductivity, thinner layers and lower CTE are key requirements.

Adhesives: Die attach materials, flexible conductors, residue free materials needed o not exist today.

Biocompatible materials: For applications in the healthcare and medical domain (e.g. body patches, implants, smart catheters, electroceuticals), semiconductor‐based devices have to be biocompatible. This involves the integration of new (flexible) materials to comply with specific packaging (form factor) requirements.

Difficult challenges for the testing of heterogeneous devices

The difficulties in testing heterogeneous devices can be broadly separated into three categories: Test Quality Assurance, Test Infrastructure, and Test Design Collaboration.

Test quality assurance needs to comprehend and place achievable quality and reliability metrics for each individual component prior to integration, in order to meet the heterogeneous system quality and reliability targets. Assembly and test flows will become inter- twined and interdependent. They need to be constructed in a manner that maintains a cost effective yield loss versus component cost balance and proper component fault isolation and quantification. The industry will be required to integrate components that cannot guarantee KGD without insurmountable cost penalties and this will require integrator visible and accessible repair mechanisms.

Test infrastructure hardware needs to comprehend multiple configurations of the same device to enable test point insertion at partially assembled and fully assembled states. This includes but is not limited to different component heights, asymmetric component locations, and exposed metal contacts (including ESD challenges). Test infrastructure software needs to enable storing and using volume test data for multiple components that may or may not have been generated within the final integrators data domains but are critical for the final heterogeneous system functionality and quality. It also needs to enable methods for highly granular component tracking for subsequent joint supplier and integrator failure analysis and debug.

Test design collaboration is one of the biggest challenges that the industry will need to overcome. It will be a requirement for heterogeneous highly integrated highly functional systems to have test features co‐designed across component boundaries that have more test coverage and debug capability than simple boundary scans. The challenge
of breaking up what was once the responsibility of a wholly contained design for test team across multiple independent entities each trying to protect IP, is only magnified by the additional requirement that the jointly developed test solutions will need to be standardized across multiple competing heterogeneous integrators. Industry wide collaboration on and adherence to test standards will be required in order to maintain cost and time effective design cycles for highly desired components that traditionally has only been required for cross component boundary communication protocols.

The roadmapping process

The objective of ITRS 2.0 for heterogeneous integration is to focus on a limited number of key challenges (10) that have the greatest potential to be “show stoppers,” while leaving other challenges identified and listed but without focus on detailed technical challenges and potential solutions. In this process collaboration with other Focus Teams and Technical Working Groups will be a critical resource. While we will need collaboration with other groups both inside and outside the ITRS some of the collaborations are critical for HI to address its mission. FIGURE 1 shows the major internal collaborations in three categories.

FIGURE 1. Collaboration priorities.

FIGURE 1. Collaboration priorities.

We expect to review these key challenges and our list of other challenges on a yearly basis and make changes so that our focus keeps up with changes in the key challenges. This will ensure that our efforts remain focused on the pre‐competitive technologies that have the greatest future value to our audience. There are four phases in the process detailed below.

1. Identify challenges for application areas: The process would involve collaboration with other focus teams, technical TWGs and other roadmapping groups casting a wide net to identify all gaps and challenges associated with the seven selected application areas as modified from time to time. This list of challenges will be large (perhaps hundreds) and they will be scored by the HI team by difficulty and criticality.

2. Define potential solutions: Using the scoring in phase (1) a number (30‐40) will be selected to identify potential solutions. The remainder will be archived for the next cycle of this process. This work will be coordinated with the same collabo- ration process defined above. These potential solutions will be scored by probable success and cost.

3. Down select to only the 10 most critical challenges: The potential solutions with the lowest probability of success and highest cost will have the potential to be “show stopping” roadblocks. These will be selected using the scoring above and the focus issues for the HI roadmap. The results of this selection process will be commu- nicated to the relevant collaboration partners for their comments.

4. Develop a roadmap of potential solutions for “show stoppers”: The roadmap developed for the “show stopping” roadblocks shall include analysis of the blocking issue and identification of a number of potential solutions. The collaboration shall include detail work with other units of the ITRS, other roadmapping activity such as the Jisso Roadmap, iNEMI Roadmap, Communications Technology Roadmap from MIT. We are continuing to work with the global technical community: industry, research institutes and academia, including the IEEE CPMT Society.

The blocking issues will be specifically investigated by the leading experts within the ITRS structure, academia, industry, government and research organizations to ensure a broad based understanding. Potential solutions will be identified through a similar collaboration process and evaluated through a series of focused workshops similar to the process used by the ERD iTWG. This process is a workshop where there is one proponents and one critic presenting to the group. This is followed by a discussion and a voting process which may have several iterations to reach a consensus.

The cross Focus Team/TWG collaboration will use a procedure of iteration to converge on an understanding of the challenges and potential solutions that is self‐ consistent across the ITRS structure. An example is illustrated in FIGURE 2.

FIGURE 2. Iterative collaboration process

FIGURE 2. Iterative collaboration process

It is critically important that our time horizon include the full 15 years of the ITRS. The work to anticipate the true roadblocks for heterogeneous integration, define potential solutions and implement a successful solution may require the full 15 years. Among the tables we will include 5 year check points of the major challenges for the key issues of cost, power, latency and bandwidth. In order for this table to be useful we will face the challenge of identifying the specific metric or metrics to be used for each application driver as we prepare the Heterogeneous Integration roadmap chapter for 2015 and beyond.

BILL CHEN is a senior technical advisor for ASE US, Sunnyvale, CA; BILL BOTTOMS is President and CEO of 3MT Solutions, Santa Clara, CA, DAVE ARMSTRONG is director of business development at Advantest, Fort Collins, CO; and ATSUNOBU ISOBAYASHI works in the Toshiba’s Center for Semiconductor Research & Development, Kangawa, Japan.

Entegris, Inc., a provider of yield-enhancing materials and solutions for advanced manufacturing processes, announced the election of James P. Lederer as an independent director at the Company’s Annual Meeting of Shareholders held today. Mr. Lederer’s career spanned more than 32 years, with the last 18 in the semiconductor industry, including six years as an executive officer at Qualcomm.

“I am delighted to have Jim on our board,” said Bertrand Loy, president and CEO of Entegris. “Jim’s experience at Qualcomm brings an important customer and industry perspective. I look forward to his contributions and his insight as a member of our board.”

Paul Olson, chairman of the board of Entegris, added: “Through his career Jim has demonstrated a keen understanding of what it takes to succeed in a fast-paced technology industry, having played a key role in driving Qualcomm to be a technology powerhouse. I think his perspective on the industry will be an invaluable addition to the board.”

“Entegris is increasingly viewed as an indispensable partner by the semiconductor industry’s technology leaders.” says Lederer. “I look forward to working with Bertrand and his leadership team to continue to drive growth and success at Entegris.”

Mr. Lederer most recently served as Executive Vice President of Qualcomm Technologies, Inc. and General Manager of Qualcomm CDMA Technologies (QCT, semiconductor division). He retired from Qualcomm in January 2014. During his 18-year career at Qualcomm, Mr. Lederer also served in a number of senior management and finance roles. Prior to joining Qualcomm, Mr. Lederer held a variety of management positions at Motorola, General Motors and Scott Aviation. Mr. Lederer holds a B.S. degree in Business Administration (Finance/MIS) and an M.B.A. from the State University of New York at Buffalo, where he also serves on the Dean’s Advisory Council for the School of Management.

Applied Materials, Inc. and Tokyo Electron Limited today announced that they have agreed to terminate their Business Combination Agreement (BCA). No termination fees will be payable by either party.

The decision came after the U.S. Department of Justice (DoJ) advised the parties that the coordinated remedy proposal submitted to all regulators would not be sufficient to replace the competition lost from the merger. Based on the DoJ’s position, Applied Materials and Tokyo Electron have determined that there is no realistic prospect for the completion of the merger.

“We viewed the merger as an opportunity to accelerate our strategy and worked hard to make it happen,” said Gary Dickerson, president and chief executive officer of Applied Materials. “While we are disappointed that we are not able to pursue this path, our existing growth strategy is compelling. We have been relentlessly driving this strategy forward and we have made significant progress towards our goals. We are delivering results and gaining share in the semiconductor and display equipment markets, while making meaningful advances in areas that represent the biggest and best growth opportunities for us.

“I would like to thank our employees for their focus on delivering results throughout this process. As we move forward, Applied Materials has tremendous opportunities to leverage our differentiated capabilities and technology in precision materials engineering and drive a significant increase in the value we create for our customers and investors.”

North America-based manufacturers of semiconductor equipment posted $1.37 billion in orders worldwide in March 2015 (three-month average basis) and a book-to-bill ratio of 1.10, according to the March EMDS Book-to-Bill Report published today by SEMI.   A book-to-bill of 1.10 means that $110 worth of orders were received for every $100 of product billed for the month.

The three-month average of worldwide bookings in March 2015 was $1.37 billion. The bookings figure is 4.6 percent higher than the final February 2015 level of $1.31 billion, and is 5.9 percent higher than the March 2014 order level of $1.30 billion.

The three-month average of worldwide billings in March 2015 was $1.25 billion. The billings figure is 2.4 percent lower than the final February 2015 level of $1.28 billion, and is 1.9 percent higher than the March 2014 billings level of $1.23 billion.

““Three-month average bookings reported by North American-based semiconductor manufacturing equipment providers reflected sequential and year-over-year momentum in the first quarter of 2015,”” said SEMI president and CEO Denny McGuirk. “This marks the third consecutive month that bookings exceeded billing and the ratio remained above parity.””

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill
October 2014 

$1,184.2

$1,102.3

0.93
November 2014 

$1,189.4

$1,216.8

1.02
December 2014 

$1,395.9

$1,381.5

0.99
January 2015 

$1,279.1

$1,325.6

1.04
February 2015 (final)

$1,280.1

$1,313.7

1.03
March 2015 (prelim)

$1,249.1

$1,374.4

1.10

Source: SEMI, April 2015

IC Insights will release its April Update to the 2015 McClean Report later this month. The Update includes the final 2014 company sales rankings for the top 50 semiconductor and top 50 IC companies, and the leading IC foundries. Also included are 2014 IC company sales rankings for various IC product segments (e.g., DRAM, MPU, etc.).

In 2014, there were only two Japanese companies—Toshiba and Renesas—that were among the top 10 semiconductor suppliers (Figure 1). Assuming the NXP/Freescale merger is completed later this year, IC Insights forecasts that Toshiba will be the lone Japanese company left in the top 10 ranking. Anyone who has been involved in the semiconductor industry for a reasonable amount of time realizes this is a major shift and a big departure for a country that once was feared and revered when it came to its semiconductor sales presence in the global market.

Fig 1

Fig 1

Figure 1 traces the top 10 semiconductor companies dating back to 1990, when Japanese semiconductor manufacturers wielded their greatest influence on the global stage and held six of the top 10 positions.  The six Japanese companies that were counted among the top 10 semiconductor suppliers in 1990 is a number that has not been matched by any country or region since (although the U.S. had five suppliers in the top 10 in 2014). The number of Japanese companies ranked in the top 10 in semiconductor sales slipped to four in 1995, fell to three companies in 2000 and 2006, and then to only two companies in 2014.

Figure 1 also shows that, in total, the top 10 semiconductor sales leaders are making a marketshare comeback. After reaching a marketshare low of 45 percent in 2006, the top 10 semiconductor sales leaders held a 53 percent share of the total semiconductor market in 2014.  Although the top 10 share in 2014 was eight points higher than in 2006, it was still six points below the 59 percent share they held in 1990.  As fewer suppliers are able to achieve the economies of scale needed to successfully invest and compete in the semiconductor industry, it is expected that the top 10 share of the worldwide semiconductor market will continue to slowly increase over the next few years.

Today, KLA-Tencor Corporation announced two new systems that support advanced semiconductor packaging technologies: CIRCL-AP and ICOS T830. Designed for characterization and monitoring of the diverse processes used in wafer-level packaging, CIRCL-AP enables all-surface wafer defect inspection, review and metrology at high throughput. The ICOS T830 provides fully automated optical inspection of integrated circuit (IC) packages, leveraging high sensitivity with 2D and 3D measurements to determine final package quality for a wide range of device types and sizes. Both systems help IC manufacturers and outsourced semiconductor assembly and test (OSAT) facilities address challenges, such as finer feature sizes and tighter pitch requirements, as they adopt innovative packaging techniques.

“Consumer mobile electronics continue to drive production of smaller, faster and more powerful devices,” stated Brian Trafas, chief marketing officer of KLA-Tencor. “Advanced packaging technologies offer device performance advantages, such as increased bandwidth and improved energy efficiency. The packaging production methods, however, are more complex—involving the implementation of typical front-end IC manufacturing processes, such as chemical mechanical planarization and high aspect ratio etch, and unique processes, such as temporary bonding and wafer reconstitution. By combining our expertise in front-end semiconductor manufacturing process control with experience gained through collaborations at key R&D sites and industry consortia, we have developed flexible and efficient inspection solutions that can help address packaging challenges from wafer-level to final component.”

The CIRCL-AP includes multiple modules that utilize parallel data collection for fast, cost-efficient process control of advanced wafer-level packaging processes. It supports a range of packaging technologies, including wafer-level chip scale packaging, fan-out wafer-level packaging and 2.5D/3D IC integration using through silicon vias (TSVs). The industry-proven 8-Series serves as the CIRCL-AP’s front side defect inspection and metrology module, which couples LED scanning technology with automated defect binning to reduce nuisance and speed detection of critical packaging defects, such as TSV cracks and redistribution layer shorts. The CV350i module, based on KLA-Tencor’s VisEdge technology, enables leading detection, binning and automated review of wafer edge defects and metrology for critical edge trim and bonding steps in the TSV process flow. With multiple imaging and illumination modes, the Micro300 module can produce high precision 2D and 3D metrology for bump, redistribution and TSV processes. Utilizing a flexible architecture, the CIRCL-AP can be configured with one or more modules to address the requirements of specific packaging applications, while the handler supports bonded, thinned and warped substrates.

The ICOS T830 extends the industry-leading ICOS component inspection series to address yield challenges associated with advanced packaging types, including lead frame, fan-out wafer-level, flip-chip and stacked packages. Enhanced package visual inspection capability, xPVI, enables high sensitivity detection of top and bottom component surface defects, such as voids, scratches, pits, chips and exposed wires. To ensure quality standards are being met for leading-edge memory and logic packaged devices, the ICOS T830 offers high speed 3D ball, lead and capacitor metrology, package z-height measurement and component side inspection. The xCrack+ inspection station enables accurate detection of micro-crack defects—a key failure mechanism of thinner components used in mobile applications. The ICOS T830 incorporates high-throughput operation of four independent inspection stations and high-speed sorting of the inspected packaged components to achieve cost-effective component quality control.

Multiple CIRCL-AP systems in various configurations have been installed worldwide for use in development and production of TSV, fan-out wafer-level packaging and other wafer-level packaging technologies. ICOS T830 systems are in use at many worldwide IC packaging facilities, providing accurate feedback on package quality across a range of device types and sizes. To maintain the high performance and productivity demanded by semiconductor packaging providers, the CIRCL-AP and ICOS T830 systems are backed by KLA-Tencor’s global, comprehensive service network.

A*STAR’s Institute of Microelectronics (IME), together with Amkor Technologies, NANIUM, STATS ChipPAC, NXP Semiconductors, GLOBALFOUNDRIES, Kulicke & Soffa, Applied Materials, Inc., Dipsol Chemicals, JSR Corporation, KLA-Tencor, Kingyoup Optronics, Orbotech and Tokyo Ohka Kogyo have formed a High-Density Fan-Out Wafer Level Packaging (FOWLP) consortium to extend FOWLP capabilities for applications in devices such as smart phones, tablets, navigation tools and gaming consoles.

These devices call for application processors with greater system capabilities such as increased memory and bandwidth, as well as faster processing speed to support myriad demanding applications and functions, while consuming low power. At the same time, the sheer market volume1 for such devices necessitates system cost reduction.

FOWLP is a low-cost packaging technology for system scaling which enables multiple chips to be integrated in a small form factor on a single package. However, the adoption of conventional FOWLP technology for high performance, multi-functional devices is being challenged by pin-count density of a few hundreds of I/Os per device package. These limitations have a direct impact on its capability to support increased system requirements and performance.

The consortium aims to provide solutions to overcome these limitations. It will develop a High-Density FOWLP test vehicle capable of supporting thousands of I/Os and characterising the package for die shift, die protrusion and wafer warpage analysis that will enable system scaling for smartphones and mobile tablets. Concurrently, tight wiring to accommodate increased pin counts using fine pitch multi-layer redistribution layer technology will be demonstrated for large area FOWLP while maintaining its signal/power integrity and reliability.

“System integration is necessary to enable diverse functionalities with high performance in future applications across a wide spectrum of industries including computing and networking, healthcare, consumer electronics, transport and automotive. With the High-Density Fan-Out Wafer Level Packaging consortium, IME continues to add to its portfolio of advanced packaging platforms so as to provide wide-ranging solutions for the continued evolution and different needs of complex and demanding devices,” said Prof. Dim-Lee Kwong, Executive Director of IME.

“Amkor is pleased to participate in the High-Density FOWLP consortium to help accelerate the adoption of this next-generation package platform technology. As a leader in the space, working to drive packaging and test technologies forward is one of our core objectives. We expect advanced platforms like High-Density FOWLP to become the prevailing packaging format for much of the advanced integration market, including mobile and high performance products,” said Mr. Ron Huemoeller, Senior Vice President, Advanced Product & Technology Development, IP of Amkor Technology, Inc.

“Market applications will always be our industry’s main drivers,” commented Mr. Armando Tavares, President of the Executive Board at NANIUM. “In times of More-than-Moore, I/Os requirements have been increasing steadily, as they translate into higher integration, improved performance, minimal form-factor and cost-effectiveness. The development of High-Density Fan-Out Wafer-Level Packaging technology represents a step towards fine-pitch multi-layer redistribution, which in turn will allow us to build higher-density structures. These will significantly increase the amount of interconnects enabled by FOWLP, turning this technology into an IC packaging platform for chip-to-chip interconnect with a higher I/O and at a competitive cost.

NANIUM regards IME’s initiative of creating a consortium as a very insightful one. Through the combination of our know-how and manufacturing capabilities with IME’s technology development expertise, we will surely contribute to the development of our FOWLP technology roadmap, to the benefit of our customers.”

“High-Density Wafer-Level Fan-Out Packaging technology enables advanced system scaling for form factor limited and cost challenged applications,” said Mr. Ramakanth Alapati, Director of Package Architecture and Customer Technology at GLOBALFOUNDRIES. “GLOBALFOUNDRIES appreciates IME’s effort to identify robust solutions needed for a cost-effective high volume manufacturing approach to wafer level packaging.”

“The strong collection of companies who have joined the consortium and our shared commitment to expanding the capabilities of FOWLP reflects the promising value of this technology for a wide range of high performance applications. This collaboration will accelerate the important development activities we have been focusing on such as ultra thin package profiles, finer line/space widths down to 2μm/2μm and multi-layer redistribution in order to achieve smart system integration at a lower cost for our customers,” said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer, STATS ChipPAC.

“This consortium has members from the entire supply chain, and with the combined experience and knowledge of all the members, the solution developed will be industry leading and targeted for high volume manufacturing benefiting the industry as a whole,” said Mr. Cheam Tong Liang, Vice President, Advanced Packaging Business Line & Corporate Strategy of Kulicke & Soffa.

Semiconductor equipment manufacturer ClassOne Technology announced today that it has signed a joint electrochemical deposition (ECD) applications lab agreement with Shanghai Sinyang Semiconductor Materials Co., Ltd.  Sinyang, China’s premier supplier of ECD chemicals, is purchasing ClassOne electroplating equipment and will be providing a site for demonstrating ClassOne’s tools in the Chinese marketplace. SPM International Ltd., ClassOne’s representative in China will also be providing product support and process assistance.

“This collaborative lab will be the first of its kind in the region,” said Byron Exarcos, President of ClassOne Technology. “Now, in a single location, users will be able to see the advanced performance of ClassOne’s electroplating tools and Sinyang’s electroplating chemicals and also be able to evaluate processes. It allows us to provide a complete solution — and a significant convenience — to users throughout the region.”

“We are looking forward to working with customers on the Solstice LT plating system because it is a high-performance tool and will provide an excellent real-world laboratory for ongoing enhancement of our chemicals,” said Dr. Wang Su, Vice President of Sinyang. “The new working arrangement will also enable us to provide direct input to ClassOne as they develop future generations of wet processing equipment.”

Shanghai Sinyang is purchasing ClassOne’s Solstice LT Electroplating System and Trident Spin Rinse Dryer (SRD). The Solstice LT is a two-chamber plating development tool designed for <200mm wafers. In Sinyang’s applications, one chamber will be dedicated to copper plating and the second to nickel plating, with the Trident SRD servicing both process streams. This will provide significant flexibility while substantially reducing cycle time and streamlining process development. The new equipment will be installed at the Sinyang lab facility in Shanghai, which is scheduled to begin live demonstrations in late May. The lab will be able to plate virtually all metals except gold, and it can also cross-reference with all chemicals for comparison benchmarks.

In addition to the LT development tool, ClassOne also offers the Solstice S8, an 8-chamber, fully-automated electroplating system for high-volume production needs. These tools are particularly well suited to wafer level packaging (WLP), through silicon via (TSV) and other applications that are important for MEMS, Sensors, LEDs, RF, Power and many other devices.

ClassOne Technology products have been described as “Advanced Wet Processing Tools for the Rest of Us” because they address the needs of many cost-conscious users. The company’s stated aim is to provide advanced yet affordable alternatives to the large systems from the large manufacturers. ClassOne supplies a range of innovative new wet processing tools, including its Solstice Electroplating Systems, Trident Spin Rinse Dryers and Trident Spray Solvent Tools (SSTs).