Category Archives: Wafer Level Packaging

On June 18, the SEMI Packaging Tech Seminar will take place in Vila do Conde, Portugal. Organized by SEMI Europe (www.semi.org/eu/), the event will be hosted by NANIUM S.A., Europe’s leading Outsourced Semiconductor Assembly and Test (OSAT). More than 100 industry professionals are expected at the event, which is dedicated to packaging, assembly, and test, with a focus on large format Fan-Out Packaging. In addition, European back-end organizations with manufacturing in Europe will have an opportunity to present corporate capabilities.

The morning session will showcase the European packaging, assembly and test industry.  Rozalia Beica of Yole Développement will present a market overview of the sector in Europe. Twelve SEMI members with manufacturing centers in Europe or European Equipment and Manufacturing companies with activities in packaging, assembly and test, will present.

The afternoon session will highlight large format Fan-Out Packaging, going beyond mainstream 200 and 300mm round wafer level packaging. Fan-Out Packaging technologies have gained momentum in recent years, with major OSATs, and even the largest wafer foundries, proposing Fan-Out Packaging solutions as part of their technology portfolio. Jan Vardaman (TechSearch International) will deliver the keynote presentation “The Movement to Large Array Packaging: Opportunities and Options.” The session will also feature presentations from research and technology organizations and equipment and materials companies, who will share viewpoints and recent achievements regarding the production of round rebuilt panels greater than 300mm and rectangular rebuilt panels. Speakers will include representatives from Fraunhofer IZM, Rudolph Technologies, SPTS, and SUSS MicroTec.

The presentations will be followed by several networking opportunities, including a Fab Tour of the   NANIUM S.A. Wafer-Level Packaging (WLP) manufacturing floor, plus a guided tour and networking dinner in the ancient downtown of Porto. Throughout the day, event sponsors will promote their packaging activities at a dedicated tabletop exhibition area.

“Europe is the home of a full back-end supply chain, including internationally renowned equipment and materials companies, research institutes, service providers and numerous packaging, assembly and test manufacturing companies,” stated Heinz Kundert, president of SEMI Europe. “By inviting our members to this Packaging Tech Seminar, we are aiming to enhance the growth of the European Packaging industry by proposing a platform for the development of business and collaborative opportunities.”

Armando Tavares, president of NANIUM’s Executive Board commented, “We have been a member of SEMI for many years, and are very pleased that we were selected as event hosts for the second time. Our industry ensures the competitiveness of sectors that are crucial for Europe, such as Automotive, Aerospace and Banking.  The EU’s 10/100/20 vision would greatly benefit from investing across the whole semiconductor supply chain, where Packaging, Assembly and Test is playing a more crucial and value-adding role than ever before.”

On June 19, attendees will have the additional opportunity to participate in the ESPAT (European Semiconductor Packaging Assembly and Test) Industry Interest Group meeting. SEMI will participate in this meeting, dedicated to advancing the interests of the European Packaging Industry and with the eventual goal of creating a SEMI-SIG (Special Interest Group).

SEMI Tech Seminars are open to everyone and free of charge for SEMI members.

Registration is now open; please visit www.semi.org/eu/node/8971 to learn more and to register. For additional information, contact Yann Guillou, SEMI Europe Grenoble Office ([email protected]).  For information about sponsoring the event, please contact Jérôme Boutant: [email protected].

STATS ChipPAC Ltd., a provider of advanced semiconductor packaging and test services, today announced that Cavendish Kinetics, a provider of high performance RF MEMS tuning solutions for LTE smartphones and wearable devices, has adopted its advanced wafer level packaging technology to deliver Cavendish’s SmarTune RF MEMS tuners in the smallest possible form factor, as a 2mm2 chip scale package.

LTE smartphone original equipment manufacturers (OEMs) are rapidly adopting antenna tuning solutions to be able to provide the required signal strength across the large number of LTE spectrum bands used globally. Cavendish’s SmarTune RF MEMS tuners outperform traditional RF silicon-on-insulator (SOI) switch-based antenna tuning solutions by 2-3dB, resulting in much higher data rates (up to 2x) and improved battery life (up to 40 percent). Cavendish RF MEMS tuner shipments are ramping aggressively and can now be found in six different smartphone models across China, Europe and North America, with many additional designs in development.

“Our RF MEMS tuners present demanding packaging requirements, including the need to deliver the smallest possible form factor in a process that protects the integrity of our hermetically sealed MEMS structure,” said Atul Shingal, Executive Vice President of Operations, Cavendish Kinetics. “STATS ChipPAC’s wafer level packaging platform provided advantages in package size, performance and scalability, and a proven, cost effective manufacturing process that supports our accelerating volume production.”

STATS ChipPAC provides a comprehensive platform of wafer level technology from Fan-in Wafer Level Packaging (FIWLP) to highly integrated Fan-out Wafer Level Packaging (FOWLP) solutions known as embedded Wafer Level Ball Grid Array (eWLB). Cavendish Kinetics and STATS ChipPAC are jointly working to utilize the inherent benefits of wafer level packaging technology to drive further RF antenna tuning innovations for the smartphone market.

“Through our successful partnership, Cavendish Kinetics has been able to implement their current generation industry leading MEMS-based antenna tuning solution. In future products, we will be able to provide Cavendish Kinetics with options for greater functional integration and silicon partitioning capabilities that are only feasible with our industry leading fan-out eWLB technology,” said Dr. Rajendra Pendse, Vice President and Chief Marketing Officer, STATS ChipPAC.

BY JOE CESTARI, Total Facility Solutions, Plano, Texas

When the commercial semiconductor manufacturing industry decides to move to the next wafer size of 450mm, it will be time to re-consider equipment and facilities strategies. Arguably, there is reason to implement new strategies for any new fab to be built regardless of the substrate size. In the case of 450mm, if we merely scale up today’s 300mm layouts and operating modes, the costs of construction would more than double. Our models show that up to 25 percent of the cost of new fab construction could be saved through modular design and point-of-use (POU) facilities, and an additional 5-10 percent could be saved by designing for “lean” manufacturing.

In addition to cost-savings, these approaches will likely be needed to meet the requirements for much greater flexibility in fab process capabilities. New materials will be processed to form new devices, and changes in needed process-flows and OEM tools will have to be accommodated by facilities. In fact, tighter physical and data integration between OEM tools and the fab may result in substantially reduced time to first silicon, ongoing operating costs and overall site footprint.

POU utilities with controls close to the process chambers, rather than in the sub-fab, have been modeled as providing a 25-30 percent savings on instrumentation and control systems throughout the fab. Also, with OEM process chamber specifications for vacuum-control and fluid-purity levels expected to increase, POU utilities provide a flexible way to meet future requirements.

Reduction of fluid purity specifications on central supply systems in harmony with increases in localized purification systems for OEM tools can also help control costs, improve flexibility, and enhance operating reliability. There are two main reasons why our future fabs will need much greater flexibility and intelligence in facilities: high-mix production, and 1-12 wafer lots.

High-mix production

Though microprocessors and memory chips will continue to increase in value and manufacturing volumes, major portions of future demand for ICs will be SoCs for mobile applications. The recently announced “ITRS 2.0”—the next roadmap for the semicon- ductor fab industry after the “2013” edition published early in 2014—will be based on applications solutions and less on simple shrinks of technology. Quoting Gartner Dataquest”s assessment:

System-on-chip (SoC) is the most important trend to hit the semiconductor industry since the invention of microprocessors. SoC is the key technology driving smaller, faster, cheaper electronic systems, and is highly valued by users of semiconductors as they strive to add value to their products.”

1-12 Wafer Lots

The 24-wafer lot may remain the most cost-effective batch size for low-mix fabs, but for high-mix lines 12-wafer lots are now anticipated even for 300mm wafers. For 450mm wafers, the industry needs to re-consider “the wafer is the batch” as a manufacturing strategy. The 2013 ITRS chapter on Factory mentions in Table 5 that by the year 2019 “Single Wafer Lot Manufacturing System as an option” will likely be needed by some fabs. Perhaps a 1-5 wafer carrier and interface would be a way for an Automated Material Handling System (AMHS) to link discrete OEM tools as an evolution of current 300mm FOUP designs.

However, a true single-wafer fab line would be the realization of a revolution started over twenty years ago when the MMST Program was a $100M+ 5-year R&D effort funded by DARPA, the U.S. Air Force, and Texas Instruments, which developed a 0.35μm double-level-metal CMOS fab technology (with a three-day cycle time). In the last decade BlueShift Technologies was started and stopped to provide such revolutionary technology for vacuum-robot-lines to connect single-wafer chambers all with a common physical interface.

Lean manufacturing approaches should work well with high-mix product fabs, in addition to providing more efficient consumption of consumables in general. In specific, when lean manufacturing is combined with small batch sizes—minimally the single wafer—there is tremendous improvement in cycle-time.

Semiconductor equipment manufacturer ClassOne Technology announced the sale and delivery of its Solstice S8 Plating System to Advanced Wireless Semiconductor Company (AWSC) of Taiwan. The fully automated Solstice S8 will be installed at the AWSC facility in the Tainan Industrial Park in Taiwan where it will be used for volume manufacturing processes such as lead-free wafer level packaging (WLP) and through wafer vias (TWV) used in the manufacture of RF and other microdevices.

“Foundries often need to weigh performance and price carefully, and we believe the S8 strikes the right balance,” said Kevin Witt, ClassOne’s V.P. of Technology. “For example, the Solstice can enable a customer to move Copper Pillar, Nickel, Tin Bump, and Cu Backside Via production from several wet benches onto a single automated tool that gives a better process result and higher productivity. In addition, ClassOne supports customers with process development and deployment every step of the way.”

“Solstice fills a void in the market between wet benches on the low end and the large, expensive 300mm plating systems on the high end,” said Win Carpenter, ClassOne’s V.P. of Global Sales. “The Solstice S8 was designed to provide advanced plating performance at a reasonable cost for everyone who manufactures on 200mm and smaller substrates. Those users include many emerging markets such as MEMS, LEDs, RF, power, and sensors.”

The Solstice electroplating systems were introduced in 2014 and are available in fully automated, 4- and 8-chamber configurations that deliver up to 75 wph of capacity. The Solstice family handles substrates up to and including 200mm, whether transparent or opaque, and performs key processes such as electroplating of various metals and alloys. Solstice pricing is less than half that of similarly configured 300mm plating systems outfitted for 200mm from the large manufacturers.

IC Insights recently released its March Update to the 2015 McClean Report.  The Update includes a review of IC company sales by headquarters location.  In this example, Samsung’s sales from its fabrication facility in Austin, Texas, are counted as sales from South Korean companies.  Intel’s sales from its fabs in China, Ireland, and Israel are included among U.S. companies, etc.  As shown, U.S. companies held a 55 percent share of the total worldwide IC market in 2014, which includes sales from IDMs and fabless IC companies. The total does not include foundry sales.  South Korean companies captured an 18 percent share and Japanese companies placed third with a 9 percent share. Chinese companies accounted for only 3 percent of total IC sales in 2014 (Figure 1).

IDM fab sales Fig 1

 

Among IDMs (companies with wafer fabs that manufacture their own ICs), U.S.-headquartered companies accounted for slightly over half of worldwide sales followed by companies based in South Korea, Japan, and Europe. Taiwan companies (not including foundries) held only a 2 percent share.

Over the next couple of years, NXP’s purchase of Freescale (expected to close later this year) and Infineon’s purchase of IR will likely boost the European share of worldwide IDM IC sales by a few percentage points at the expense of U.S. share.  In contrast, Europe is expected to lose fabless IC company marketshare in the next few years due to Qualcomm’s acquisition of CSR, Europe’s second-largest fabless IC supplier, and Intel’s purchase of Lantiq, Europe’s third-largest fabless IC supplier (Figure 2).

IDM fab sales Fig 2

 

U.S. companies held the dominant share of fabless IC sales last year, although its share was down from 69 percent in 2010.  The largest increase in fabless IC marketshare came from Chinese companies, which held a 9 percent share in 2014 compared to only 5 percent in 2010.

Further details on IC sales by region and by company, including IC Insights’ final sales ranking of the top 50 IDMs and top 50 fabless IC companies for 2014, are included in the March Update to The McClean Report—A Complete Analysis and Forecast of the Integrated Circuit Industry.

Packages are changing. Acoustic methods provide a way to image and analyze them.

BY TOM ADAMS, SONOSCAN, INC., Elk Grove Village, IL

By the year 2020, the design, dimensions and materials of various electronic component packages will have changed in varying degrees from their current forms. PEMs (plastic-encap-sulated microcircuits) will still be in production, but likely with shrinking sizes and better (or less expensive) encapsulants. Stacking of die connected by non-wire methods such as through-silicon vias (TSVs) will be in production. These and other package types, along with components such as ceramic chip capacitors, will need to be inspected for internal anomalies, typically by non-destructive acoustic micro imaging. This article takes a forward look at some of the challenges and changes that may take place in various packages and the possible advances in acoustic methods for imaging and analyzing them.

In electronic components, the business of acoustic micro imaging is to make visible and and analyze internal structural features. Acoustic micro imaging tools such as Sonoscan’s C-SAM series are used to image anomalies and defects, or to verify their absence. The defects are typically gaps – delaminations, voids, cracks, non-bonds and the like – but an acoustic micro imaging tool will also reveal surprises such as the out-of-place or missing die sometimes noted in counterfeit components.

New acoustic imaging methods

Today, the prevalent imaging mode for acoustic micro imaging tools is what is commonly called the Time Domain Amplitude Mode. The scanning transducer sends a pulse of VHF (5 to 100 MHz) or UHF (above 100 MHz) ultrasound into an x-y location. A few micro-seconds later, the transducer receives a number of echoes from the depth of interest. The amplitude of the highest-amplitude echo within a gate (time window) is used to assign a pixel value to that x-y location. The other echoes are ignored.

At the moment, there are about a dozen other imaging modes which collect data in different ways and which yield different information and images about a sample. One example: it is important in imaging IGBT modules to measure and map the thickness of the solder bonding the heat sink to the ceramic raft above. Irregular solder thickness often means that the raft is tilted or warped (and thus may restrict heat dissipation). The Time Difference mode will map the interface. This mode ignores echo amplitude altogether and uses the arrival time of the echoes to measure and map the thickness of the solder. Irregular solder thickness means that the raft is tilted or warped (and thus may restrict heat dissipation). Other acoustic imaging modes use other techniques to detect thickness variations.

The Frequency Domain mode produces multiple images of the target depth in a sample. Each image is made using echoes within a very narrow frequency range (e.g., 102.0-103.5 MHz). This mode is useful in samples having subtle anomalies or defects that may be hard to discern with, say, Amplitude Mode.

A new mode is typically developed when the user of an acoustic micro imaging tool expresses the need to push acoustic imaging beyond its current capabilities in order to solve a specific inspection problem. In some instances an existing mode that was previously developed for research purposes is found to be useful for emerging sample types. It is very likely that new acoustic imaging modes will developed as electronic components and assemblies continue to evolve.

A recently developed mode is the Echo Integral Mode. It gives a view similar to, but more informative than, the Amplitude Mode. While Amplitude Mode picks the highest single amplitude to assign a pixel value, The Echo Integral Mode uses the sum of the amplitude of all the echoes at a given x-y coordinate to determine the pixel color for that coordinate. This approach makes it easier to see subtle local differences in, say, the quality of a bond between two materials.

FIGURE 1 is the Thru-Scan mode image of a plastic BGA package. Thru-Scan pulses ultrasound into the top of the package and uses a sensor beneath the package to read the amplitude of the arriving ultrasound at each x-y location. Gap-type defects block ultrasound and thus appear in a Thru-Scan image as black acoustic shadows.

FIGURE 1. Thru-Scan image shows acoustic shadows of anomalies in a BGA package, but gives no depth information.

FIGURE 1. Thru-Scan image shows acoustic shadows of anomalies in a BGA package, but gives no depth information.

In Figure 1, the black features within the die at center are surely significant anomalies, but an engineer cannot tell from this Thru-Scan image what depth they lie at: are they in the die attach material or in the substrate below?

At left in FIGURE 2 is the Amplitude Mode image of the die area. This image is gated on (reads echoes only from) the die attach depth, and ignores echoes from other depths. The black dots are not features in the gated depth, but are the acoustic shadows of voids in the mold compound above the die. The die area itself is rather uniformly pale gray, with no features of note. The image at right used the Echo Integral Mode, also gated on the die attach material. Using the average amplitude of all the echoes at of millions of x-y coordinates gave a different result: there are significant differences in brightness. The large bright area marked by arrows is a gap-type defect in the die attach, and there are other, smaller defects of the same type. The defects imaged as black shadows by Thru-Scan are imaged here as near-white defects by the Echo Integral Mode. They are clearly in the die attach, and not in the substrate. The roughly spherical feature in the upper right of the Thru-Scan image, however, is the shadow of the void in the mold compound above the die.

FIGURE 2. Amplitude mode (left) shows no defects, but Echo Integral Mode (right) shows locations of defects in the die attach.

FIGURE 2. Amplitude mode (left) shows no defects, but Echo Integral Mode (right) shows locations of defects in the die attach.

Components will continue to shrink

Sonoscan’s laboratories have for some time been imaging PEMs that are only 200 microns thick and 3mm x 3mm in area. The die is typically less than 100 microns thick. In some ways, the small dimensions are an advantage in acoustic imaging: the plastic encapsulant scatters and absorbs ultrasound, so the less encapsulant the pulse and the resulting echo need to travel through, the better the resolution in the acoustic image. Such a component may be imaged with the very high frequency of 230 MHz, rather than the 15 MHz to 100 MHz of larger plastic packages. Higher frequency means better spatial resolution in the acoustic image.

One of the most commonly imaged non-PEM components is the ceramic chip capacitor, where the goal is to image delaminations and cracks that can lead to leakage between electrode layers. The very smallest ceramic chip capacitors currently being manufactured measure 0.010 inch by 0.005 inch. They can be imaged acoustically, but extremely small dimensions make imaging time-consuming.

Mid-end components

So named because they involve both front-end and back-end processes, mid-end components are typically assembled by mounting flip chips onto a wafer and then encapsulating the flip chips with plastic before dicing the wafer. They have been described as non-wired QFNs.

What has evolved is that some mid-end components can be imaged well enough to see details of the solder bump bonds, while others cannot. Sonoscan has developed transducers having an acoustic frequency that is low enough to get through the plastic encapsulant, and high enough to give good details about the bump bonds.

But many mid-end components have an encap- sulant that is only partly transparent to ultrasound. Gross features and defects will be visible, but not the details of the bump bonds, which will probably become even smaller in the future. The alternative is to use the Thru-Scan imaging mode. Any gap in between, such as a break in a solder bump, will block the arriving ultrasound and be visible as a black feature. These acoustic shadows contain no information about the depth of a feature, but the relatively simple design along with experience with a given mid-end component are helpful.

The evolution of package design may in time alleviate the encapsulant problem. The trend is toward more chip-on-wafer type designs, and toward ever-smaller dimensions. The encapsulants may perhaps become unnecessary; their departure would enhance acoustic inspection.

Stacked die

Individual components typically have industry standards that can be used to judge the risk posed by a void in the die attach material or a delamination along a lead finger. Stacked die have no industry standards; presumably each maker of stacked die uses their own guidelines to reduce field failures.

Die stacks can be imaged acoustically before encapsulation, and in the future some may be imaged after encapsulation, particularly if ultrasound-friendly encapsulants are used. In both situations, the same problem occurs: each pulse encountering a material interface is partly reflected and partly transmitted across the interface. Unencapsulated stacks are typically imaged during development in order to refine assembly processes. Even a four-die stack (that has at least eight interfaces) can generate so many echoes that it becomes very difficult to identify the echo being sent by the delamination of the adhesive on the top of die #3.

For unencapsulated stacks, this problem has largely been solved by software developed jointly by Sonoscan and the Technical University of Dresden. The software uses material properties and dimensions to create a virtual stack as much like the physical stack as possible, and works out the imaging techniques, which are then further refined on the physical stack. The goal is to identify the echoes that were returned from specific depths of interest – e.g., the interface between the bottom surface of die #6 and the adhesive beneath it. By repeatedly moving between the virtual sample and the physical sample, the imaging parameters are defined that will show the echoes at this depth.

Nearly all memory devices are stacked, and the die are wire-bonded to each other. But there are stacks have many different configurations; one common configuration puts a small memory chip on top of a larger processing chip.

It’s hard to tell where the architecture of die stacks may go from here. In some stacks, through-silicon vias (TSVs) will replace wires. Defects such as delamina- tions will be visible acoustically, but whether the TSVs will be visible acoustically is difficult to judge at this point. What manufacturers want to see is that each TSV is filled. Their diameters are already extremely small. Whether acoustic methods will be devised to make them nondestructively visible is not known yet.

A long-standing problem in imaging typical PEMs is that a delamination on the back side of the die paddle cannot be imaged when scanning the top side of the PEM. Before the PEM is surface-mounted, it can simply be flipped over and imaged from the back side. After mounting, only the top surface is available for scanning. The problem is that there are too many interfaces: the pulsed ultrasound must cross the top surface of the plastic, the plastic-to-die interface, the die-to-die attach interface, and the die attach-to-die paddle interface. This is essentially the same problem encountered in the imaging of stacked die. In theory, a delamination between the die paddle and the plastic below it can be located and imaged by the software developed for die stacks.

Package-on-package

Package-on-package assemblies, such as a package containing one or more memory die on top of a package containing one or more logic die, are beginning to appear in Sonoscan’s testing laboratories. These package designs have some advantages over the stacking of die; for example, if one of the two packages is found to be defective before assembly, it can be replaced, while the logic package is retained. It seems likely that the popularity of these assemblies will increase in the next few years.

After the two packages are bonded together, the chief structural reliability concern is the adhesive between the two packages. This is where gap-type defects, primarily voids, may be found. If present, voids put stress on the solder joints for the BGA balls.

How acoustic imaging is performed depends on the structure of the assembly. Normal reflection-mode pulse-echo imaging can sometimes be used, but the assembly is likely to have numerous material interfaces that could limit the effectiveness of this method. Because internal structural defects in this assembly are largely limited to voids at a specific known depth, it often makes more sense to use the Thru-Scan mode to reveal the voids.

Interposers

The term “interposer” is used rather loosely to describe a redistribution layer between a top die and a lower die or printed circuit board. chip and the solder balls that make connection with a substrate. In terms of acoustic imaging, interposers behave much like flip chips, in that the depth of interest is between two structures.

The common defects are delaminations, signif- icant because they are capable of attracting contaminants (and thus causing corrosion) and of expanding through thermal cycling. The growth of chips having advanced processing capabilities will likely make the acoustic imaging of interposers more frequent.

Summary

The advantage of acoustic micro imaging tools is their ability to image nondestructively gap-type anomalies and certain other anomalies (tilting, warping) in electronic materials. In recent years, the original Amplitude Mode has been joined by roughly a dozen other modes that push imaging capabilities into new areas.

It can be expected that electronic components will continue to add their own capabilities and to reduce their physical dimensions. Some components will become more difficult to image; others, particularly those that become thinner or that use acoustically friendly materials, may permit the use of higher frequencies to image smaller features. Since there is no good non-destructive substitute for acoustic modes, engineers who demand reliability may want to apply acoustic micro imaging to new device configurations and keep track of new acoustic imaging modes.

Supplier Hub answers the needs of a changing semiconductor industry. 

BY LUC VAN DEN HOVE, imec, Leuven, Belgium

Supplier HubOur semiconductor industry is a cyclical business, with regular ups and downs. But we have always successfully rebounded, with new technologies that have brought on the next generation of electronic products. Now however, the industry stands at an inflection point. Some of the challenges to introduce next generation technologies are larger than ever before. Overcoming this point will require, in our opinion, a tighter collaboration than ever. To accommodate that collaboration, we have set up a new Supplier Hub, a neutral platform where researchers, IC producers, and suppliers work on solutions for technical challenges. This collaboration will allow the industry to overcome the inflection point and to move on to the next cycle of success, driven by the many exciting application domains that appear on the horizon.

Call for a new collaboration model

The formulas for the industry’s success have changed. Device structures are pushing the limits of physics, making it challenging to continue progressing according to Moore’s Law. Intricate manufacturing requirements make process control ever more difficult. Also chip design is more complex than ever before, requiring more scrutiny, analysis and testing before manufacturing can even begin. And the cost of manufacturing equipment and setting up a fab has risen exponentially, shutting out many smaller companies and forcing equipment and material suppliers to merge.

In that context, more and more innovation is coming from the supplier community, both from equipment and material suppliers. But as processes are approaching some fundamental limits, such as material limits, chemical, physical limits, it is also for suppliers becoming more difficult to operate and develop next-generation process steps in an isolated way. An earlier and stronger interaction among suppliers is needed.

All this makes a central and neutral platform more important than ever. That insight and the requests we got from partners set imec on the path to organizing a supplier hub. A hub that is structured as a neutral, open innovation R&D platform, a platform for which we make a substantial part of our 300mm cleanroom floor space available, even extending our facilities. It is a platform where suppliers and manufacturers collaborate side-to- side with the researchers developing next-generation technology nodes.

Organizing the supplier hub is a logical evolution in the way we have always set up collaborations with and between companies that are involved in semiconductor manufacturing. Collaborations that have proven very successful in the previous decade and that have resulted in a number of key innovations.

Supplier Hub off to a promising start

Today, both in logic and in memory, we are developing solutions to enable 7nm and 5nm technology nodes. These will involve new materials, new transistor architectures, and ever shrinking dimensions of structures and layers. At imec, the bulk of scaling efforts like these used to be done in collaborative programs involving IDMs and foundries, but also the fabless and fablite companies. All of these programs were strongly supported by our partnerships with the supplier community.

But today, to work out the various innovations in process steps needed for future nodes, we simply need this stronger and more strategic engagement from the supplier community, involving experimenting on the latest tools, even if they are still under development. And vice-versa, the tool and material suppliers can no longer only develop tools based on specs documents. To fabricate their products successfully and on time, they need to develop and test in a real process flow, and be involved in the development of new device concepts, to be able to fabricate tools and design process steps that match the requirements of the new devices.

A case in point: it is no longer possible now to develop and asses the latest generation of advanced litho without matching materials and etch processes. And reversely, the other tool suppliers need the result of the latest litho developments. So today, all process steps have to be optimized concurrently with other process steps, integrating material innovations at the same time. And this is absolutely necessary for success.

So that’s where the Supplier Hub enters.

In 2013, imec announced an extended collaboration with ASML, involving the set up an advanced patterning center, which will grow to 100 engineers. In 2014, the new center was started as the cornerstone of the supplier hub. Mid 2014, Lam Research agreed to partake in the hub. And since then a growing number of suppliers has been joining, among them the big names in the industry. Some of more recent collaborations that we announced e.g. were Hitachi (CD-SEM metrology equipment) and SCREEN Semiconductor Solutions (cleaning and surface preparation tools).

End of 2014, ASML started installing its latest EUV-tool, the NXE:3300. In the meantime, we have initiated building a new cleanroom next to our existing 300mm infrastructure. The extra floor space will be needed to accommodate all the additional equipment that will come in in the frame of the tighter collaboration among suppliers. Finally, during our October 2014 Internal Partner Conference, we organized a first Supplier Collaboration Forum where the suppliers discussed and evaluated their projects with all partners, representing a large share of the semiconductor community.

We have also been expanding the supplier hub concept through a deeper involvement of material suppliers. These will prove a cornerstone of the hub, as many advances we need for scaling to the next nodes will be based on material innovations.

Enabling the Internet-Of-Everything

I hold great optimism for the industry. The last years, the success of mobile devices has fueled the demand for semiconductor-based products. These mobile applications will continue to stimulate data consumption, going from 4G to 5G as consumers clamor for greater data availability, immediacy, and access. Beyond the traditional computing and communications applications loom new markets, collectively called the ‘Internet of Everything.’

In addition, nanoelectronics will enable disruptive innovations in healthcare to monitor, measure, analyze, predict and prevent illnesses. Wearable devices have already proven themselves in encouraging healthier lifestyles. The industry’s challenge is now to ensure that the data delivered via personal devices meet medical quality standards. In that frame, our R&D efforts will continue to focus on ultra-low-power multi-sensor platforms.

While there are many facets to the inflection point puzzle, the answers of the industry begin to take shape. The cost of finding new solutions will keep on rising. Individual companies carry ever larger risks if their choices prove wrong. But through closer collabo- ration, companies can share that risk while developing solutions, exploring and creating new technologies, shorten times to market, and be ready to bring a new generation of products to a waiting world. The industry may indeed stand at an inflection point, but the future is bright. Innovation cannot be stifled. And collaboration remains the consensus of an industry focused on the next new thing. Today, IC does not just stand for Integrated Circuit, it indeed calls for Innovation and Collaboration.

North America-based manufacturers of semiconductor equipment posted $1.31 billion in orders worldwide in February 2015 (three-month average basis) and a book-to-bill ratio of 1.02, according to the February EMDS Book-to-Bill Report published today by SEMI.   A book-to-bill of 1.02 means that $102 worth of orders were received for every $100 of product billed for the month.

The three-month average of worldwide bookings in February 2015 was $1.31 billion. The bookings figure is 1.3 percent lower than the final January 2015 level of $1.33 billion, and is 1.0 percent higher than the February 2014 order level of $1.30 billion.

The three-month average of worldwide billings in February 2015 was $1.28 billion. The billings figure is 0.2 percent lower than the final January 2015 level of $1.28 billion, and is 0.9 percent lower than the February 2014 billings level of $1.29 billion.

“Year-to-date bookings and billings for North American semiconductor equipment are higher than last year for the same time period,” said SEMI president and CEO Denny McGuirk. “The year is off to a good start, with growth in bookings from the back-end sector.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill

September 2014 

$1,256.5

$1,186.2

0.94

October 2014 

$1,184.2

$1,102.3

0.93

November 2014 

$1,189.4

$1,216.8

1.02

December 2014 

$1,395.9

$1,381.5

0.99

January 2015 (final)

$1,279.1

$1,325.6

1.04

February 2015 (prelim)

$1,277.1

$1,308.1

1.02

Source: SEMI, March 2015

The recent acquisition of Freescale Semiconductor by NXP Semiconductors would catapult the merged entity into the world’s eighth-largest chipmaker, positioning the newly minted giant for an even more formidable presence in key industrial sectors, according to IHS, a global source of critical information and insight.

Prior to the merger, NXP ranked 15th in revenue and Freescale 18th. With combined revenue last year of approximately $10 billion, the resulting new company would have surpassed Broadcom. Only Intel, Samsung Electronics, Qualcomm, SK Hynix, Micron Technology, Texas Instruments and Toshiba would have been bigger, as shown in the table below.

Global Top 10 Semiconductor Makers’ Revenue Share

2014 Company  Revenue Share
Rank
1 Intel 14.14%
2 Samsung Electronics 10.77%
3 Qualcomm 5.46%
4 SK Hynix 4.56%
5 Micron Technology 4.56%
6 Texas Instruments 3.46%
7 Toshiba 2.90%
8 NXP-Freescale (Merged) 2.83%
9 Broadcom 2.38%
10 STMicroelectronics 2.10%

 

“The merged company’s strength will be especially apparent in automotive-specific analog applications,” said Dale Ford, vice president and chief analyst at IHS. “Automotive products clearly will be the biggest convergence resulting from a merged product portfolio of the Dutch-based NXP and its smaller U.S. rival.”

The amalgamated NXP-Freescale would place the company in second place in the area of microcontroller units (MCUs), which are integrated circuits for embedded and automatically controlled applications, including automotive engine-control systems.  The merged company could also affect the digital signal processing (DSP) market, where Texas Instruments reigns supreme. DSPs are an important component in the audio and video handling of digital signals used in myriad applications, including mobile-phone speech transmission, computer graphics and MP3 compression.

“While both NXP and Freescale boast diverse portfolios with complementary products, the high-performance lines of the two chipmakers have very different target solutions,” said Tom Hackenberg, senior analyst for MCUs and microprocessors at IHS.

Freescale has been a key strategic provider of high-reliability automotive, telecomm infrastructure and industrial solutions, including both application-specific and general-purpose products that go after high-performance applications. NXP’s broad portfolio, by comparison, has strategically targeted precision analog and low-power portable-device applications, most of which are directed at portable wireless, automotive infotainment, consumer components and a complementary base of industrial components, including secure MCUs for smart cards. Even in the auto industry, where the two companies both focus on infotainment, their technologies harmonize: NXP dominates the radio market, while Freescale fills a large demand for low- to midrange center-stack processors and instrument cluster controllers.

“The most significant processor competition will likely occur in low-power connectivity solutions, where both chipmakers offer competitive connectivity MCUs,” said Hackenberg. “In particular, the newly merged company will be well-positioned to make groundbreaking advances in the human-machine interface market.”

Freescale recently began developing its portfolio of vision-related intellectual property with Canadian maker CogniVue, used in advanced driver assistance systems (ADAS). For its part, NXP has solid voice-processing expertise. Both companies overall have strong sensor fusion intellectual property, with each maker tending toward different applications. “The resulting combination could offer strategic symmetry in combined vision-, voice- and motion-controlled systems,” Hackenberg added.

Another important aspect of the merger is that Freescale is a near-exclusive source for power architecture processors and processor intellectual property. Although its market share overall is small compared to x86 and ARM, Freescale plays a significant role in the military aerospace industry, where many high-reliability equipment controls rely on power architecture. “While the acquisition of Freescale by a foreign owner is unlikely to be a deal breaker, the development could have some bearing on the approval process in the military, as it will now involve a non-U.S. company possessing ownership of its primary source of military aerospace specific Power Architecture,” Hackenberg noted.

Ziptronix Inc., a developer and provider of patented, low-temperature direct bonding technology for 3D integration, today announced a patent licensing agreement with Sony Corporation for application in advanced image sensors. The agreement marks the continued adoption of Ziptronix’s hybrid bonding patents for high volume applications.

“This license agreement with Sony is an exciting milestone for Ziptronix because it removes any doubt that our patented DBI hybrid bonding technology is both manufacturable and beneficial for high volume applications,” noted Dan Donabedian, CEO and president of Ziptronix. “We believe it demonstrates that our patented hybrid bonding technology is both enabling and cost effective as compared to stacking with TSVs. Sony licensed Ziptronix’s ZiBond direct bonding patents in 2011, which we also believe grew their image sensor market share from a few percent to the largest market share in the industry. We expect this new license for Ziptronix’s DBI hybrid bonding patents will further contribute to Sony’s growth within the industry. Any company wishing to compete in this space will need Ziptronix’s DBI hybrid bonding patents.”

Ziptronix offers patented technology for wafer- or die-level bonding. The company’s intellectual property has been licensed for a variety of semiconductor applications including BSI sensors, RF front ends, pico-projectors, memories and 3D integrated circuits.  Founded in 2000 as a venture-backed spinoff of RTI International, the company has been issued 45 U.S. patents and 42 international patents, with 18 U.S. and international patent applications pending.