Category Archives: Wafer Level Packaging

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today introduced two new configurations to its EVG 580 ComBond series of automated high-vacuum covalent wafer bonding systems. Addressing the needs of universities and R&D institutes, and high-volume manufacturing (HVM) requirements, respectively, both system configurations achieve electrically conductive and oxide-free bonds of materials with different lattice constants and coefficients of thermal expansion at room temperature.

Applications that demand room-temperature bonding of substrates with very different material properties and that are supported by the EVG580 ComBond series include advanced engineered substrates, power devices, stacked solar cells and emerging technologies such as silicon photonics.

The new entry-level EVG580 ComBond system for universities and R&D institutes comes with one cassette station or manual load port as well as a single-arm robot, supporting up to three process modules. The EVG580 ComBond HVM system can be configured with two cassette stations or an equipment front-end module with up to four cassettes for continuous mode operation, as well as comes with a dual-arm robot to support up to six process modules for maximum throughput.

Both new ComBond system configurations, as well as the standard system that can accommodate up to five process modules, are built on a modular platform supporting wafers up to 200mm in diameter. In addition to one or more bond chambers, the systems feature a dedicated ComBond Activation Module (CAM), which provides advanced surface preparation by directing energized particles to the substrate surface to achieve a contamination-free and oxide-free bond interface. The systems operate in a high-vacuum-process environment with base pressures in the range of 5×10-8 mbar, which prevents re-oxidation of the treated wafers prior to the bonding step.

“The EVG580 ComBond system with its standard five-module configuration, which was launched last autumn, has already demonstrated its capabilities with multiple R&D partners and customers,” stated Dr. Thomas Glinsner, corporate product management director at EV Group. “With the new three-module system, we will now make this breakthrough technology available to universities and smaller R&D institutes, which often are at the forefront of pioneering advanced electronic materials and device research, such as heterogeneous integration of compound semiconductors for silicon photonics and other leading-edge applications. All ComBond systems can be further customized to address specific application development needs, such as with special metrology modules utilizing free ports of the high-vacuum handling.”

wafer bonding ev group

The industrial semiconductor market will post a 9.7 percent compound annual growth rate (CAGR) over the next several years as revenue rises from $34.8 billion in 2013 to $55.2 billion in 2018, according to IHS, a global source of critical information and insight. Increased capital spending by companies and continued economic growth, especially in the United States and China, and will help spur demand and drive sales growth for industrial semiconductors.

Based on the latest information from the Q4 2014 Industrial Semi Market Report from IHS Semiconductors and Components Service, factory automation, building and home control and commercial aircraft are driving demand for industrial semiconductors. In fact, industrial semiconductor sales posted 4.7 percent growth in the third quarter (Q3) of 2014 alone compared to the previous quarter. By the end of 2014 the market grew an estimated 16.8 percent over the previous year. Demand was especially strong for optical LEDs, which grew 23.4 percent, rising from $6.3 billion to $7.7 billion. Discrete power transistors and thyristors posted 13.4 percent growth, rising from $5.5 billion in 2013 to $6.3 billion in 2014.

ihs industrial semi report

 

Industrial OEM factory revenues were expected to grow 8.3 percent in 2014 on increased sales in the building and home-control market. High-growth categories include LED lighting and IP cameras and other digital video surveillance products.

“Because of strong growth in the industrial segment, semiconductor companies are paying more attention to this market as more chips are being used in applications that did not previously use semiconductors,” said Robbie Galoso, principal analyst for IHS. “Growth in the industrial segment has also been buoyed by a gradual acceleration in the global economy, which continues to boost industrial equipment demand, especially from the United States and China.”

The global economy was strong in 2014 and, led by the United States, it is expected to flourish through 2018. U.S. economic growth is broad-based than in other regions, with a more stabilized housing market, improved consumer finances and credit, and increased capital spending. U.S real gross domestic product (GDP) growth is expected to reach 2.4 percent in 2014, 3.1 percent in 2015 and 2.7 percent in 2016.

The United States accounted for 30.5 percent of all semiconductors used in industrial applications in 2013. China is the second largest industrial chip buyer, purchasing about 14 percent of all industrial semiconductors. Its economy will grow 7.3 percent in 2014, 6.5 percent in 2015 and 6.7 percent in 2016.

“Stronger economic growth and increased capital spending in the United States and China is good news for industrial semiconductor manufacturers because they are the leading purchasers of industrial semiconductors,” Galoso said. “A solid economy and robust industrial equipment demand will further boost sales of optical semiconductors, analog chips and discretes, which are the three largest industrial semiconductor product segments.”

LED demand shines

Revenue from optical chips for industrial applications will grow from $8.6 billion in 2013 to $15.9 billion in 2018. The optical chip segment includes LEDs for general lighting, which represented 72 percent of the optical category in 2013, and will reach 78.4 percent in 2018. Optocouplers used in motor drives in factory automation and energy distribution, conversion and storage, is the second biggest product category within optical integrated circuits (ICs).

Analog semiconductor revenue will increase from $6.7 billion 2013 to $9.9 billion in 2018, while discretes increase from $6.4 billion to $8.6 billion. The analog semiconductor segment includes voltage regulators and reference, data converters, amplifiers and comparators, and interface ICs, which are used in factory automation, motor drives, and energy conversion and storage.

Image sensors are the smallest category in the optical chip segment. These sensors are currently transitioning from charge-coupled-device (CCD) image sensors to complementary metal-oxide-semiconductor (CMOS) image sensors that are widely used in security cameras, medical imaging equipment and military devices.

Industrial semiconductors with the strongest compound annual growth rates from 2013 through 2018 will include logic semiconductors at 13.4 percent, optical semiconductors at 13 percent and sensors and actuators at 10.8 percent.

Logic ICs are widely used in automation, including programmable logic controllers, digital control systems and communication and networking that extend across various markets, machine vision, and military applications.

Growth drivers

“The robust growth in demand for industrial semiconductors over the next three years will be driven by a wide range of products and segments,” Galoso said. “These products include 3D printers, factory automation products, commercial aircraft, LED lighting, digital IP cameras, climate control devices, renewable energy products, medical electronics and wireless application-specific testers.

Industrial 3D printers is a high growth category that will help drive industrial semiconductor usage in the coming years. It includes equipment used to manufacture objects through an additive process of laying down successive layers of material, until the entire object is created.

Avionics will continue to lead growth in the industrial segment. The commercial aircraft market offset the military aircraft market in the third quarter 2014. Total avionics revenue was expected to finish 2014 with 16.9 percent growth.

Led by China and the United States, the factory automation segment has grown over the past five quarters. The segment is forecast to reach 5.9 percent growth in 2014.

XMC, a 300mm semiconductor manufacturing company, today announces it has shipped over 100 million Backside Illumination (BSI) CMOS Image Sensor (CIS) units. All of the BSI CIS units are high end products ranging from 5 to 23 mega pixels by using wafer bonding technology. In addition, the state of the art 3D wafer stacking technology developed by XMC for BSI CIS has also entered volume production now. It indicates that XMC has become one of the leading BSI CIS and 3D IC manufacturing companies in the world.

XMC is dedicated to developing advanced specialty IC manufacturing technologies and providing its customers with high performance and cost effective total solutions. The R&D of wafer-level BSI technology started in the second half of 2012. It took over one year’s joint effort with our partner to reach mass production at the beginning of 2014. A year later, the more advanced 3D wafer stacking, based on the BSI technology, has also been successfully developed. It is a wafer stacking technology that not only bonds two functional wafers (of different process technologies), but also establishes the electrical connection between the two different chips in the bonded wafers. The technology fully realizes vertical wafer integration and improves both chip reliability and efficiency.

“With the offering of the advanced wafer stacking technology, XMC enables its partners to enlarge the share of high-end CIS market,”Dr. Shaoning Mei, CTO at XMC said, “We will further enhance our 3D IC expertise on the basis of 3D wafer stacking technology, by which we can achieve high performance and low power through directly connecting the core parts of two chips. 3D IC is expected to be an important technology to keep us on track with Moore’s Law. It is also the key strength for XMC to establish its leadership in 3D IC industry.”

IRT Nanoelec, an R&D consortium focused on ICT using micro- and nanoelectronics, and CMP, which provides prototyping and low-volume production of ICs and MEMS, are launching a platform for multi-project-wafer, post-process 3D integration (3D-MPW).

The new and disruptive 3D configurations and assemblies created by this IRT Nanoelec/CMP initiative are designed to promote 3D integration.

This service, the first of its kind, extends CMP’s regular MPW offer by using mature 3D post-process technologies at wafer level from IRT Nanoelec. These technologies include through-silicon-vias (TSV, via last), fine-pitch vertical interconnects (micro pillar with solder) and specific finishing for 3D integration like under-bump metallurgy (UBM). These 3D modules will enable a wide panel of new, full 3D architectures, like multiple-die stacking with flip-chip, side-by-side heterogeneous integration, and 3D partitioning of different CMOS dies issued from CMP runs.

3D integration is highly complementary to traditional CMOS scaling, and has very strong potential in terms of size reduction, heterogeneous integration, miniaturization, performance improvements and, possibly, reduction of costs at the system level. The technology is now emerging in more and more applications, such as FPGA, 3D memories and MEMS, and involves wafer-level processing on dedicated runs.

The new platform provides for the first time access to post-process 3D technologies after regular CMOS MPW runs, for proof of concept, prototypes and/or small series production. This enables a large group of users to take advantage of cost division made possible, at silicon level, by the MPW regular services followed by post-process technologies. In addition, it allows 3D-MPW users to divide the cost of post processing. This benefits a large group of customers, such as universities, SMEs, research institutes and systems integrators, that usually do not have access to the 3D modules at large foundries.

These 3D post-process technologies require very limited re-design of existing chips, and will be initially used for specific CMOS nodes available at CMP. They may be extended in the future, depending on demand. CMP is responsible for supporting, checking and compiling the customer’s requests, while IRT Nanoelec, which has a very strong background in 3D integration – in particular through the institute CEA-Leti – will manage the 3D post-processing.

Mentor Graphics Corporation today announced that it has joined the Center for Power Electronics Systems (CPES) at Virginia Tech, the industry consortium dedicated to improving electrical power processing and distribution across various systems. CPES is focused on technologies and applications related to power electronic components: vehicular power conversion, power conversion technologies, power management, and renewable energy systems. CPES has a global reputation for advanced research in power electronics with 78 members who contribute and participate in the organization’s mission, including Toyota, GE, Fairchild, Cree, Rohm, and Mitsubishi.

Commenting on the recent MicReD Industrial Power Tester 1500A solution from Mentor, Professor G. Q. Lu, CPES affiliate faculty and professor in the departments of Materials Science and Engineering and Electrical and Computer Engineering, who has collaborated with Mentor Graphics, stated, “We expect Mentor’s ability to perform reliability testing of wide-bandgap SiC power electronics devices to be a unique resource for CPES, leveraging its proven technologies to advance the power and performance of semiconductors, IGBTs, MOSFETs and other devices in our industry. We welcome Mentor Graphics’ software contribution and combined expertise in semiconductor thermal simulation and measurement that benefit the development of reliable power electronics components and systems.”

Mentor Graphics membership supports expanded use of electronics thermal design simulation software and industry adoption of thermal characterization methods for power semiconductor lifetime prediction and thermal testing. Mentor Graphics is also donating simulation software including market-leading FloTHERM and FloTHERM XT electronics thermal analysis software and FloEFD general purpose concurrent computational fluid dynamics (CFD) software.

“We are honored to be a member of CPES and our technologies are in perfect alignment with the organization’s mission,” stated Roland Feldhinkel, general manager of Mentor Graphics Mechanical Analysis Division. “The collaboration with the global member companies and researchers will provide tremendous gains for the power electronics systems industry and its customers, and we believe Mentor’s technology will be a valued contributor for these advancements.”

Total production value of electronic systems increased 5 percent in 2014 to $1,488 billion.  Electronic system production is forecast to grow at a compound annual growth rate (CAGR) of 5.2 percent from 2013-2018. Figure 1 compares the relative market sizes and projected growth rates of 10 major systems segments covered in the 2015 edition of IC Insights’ IC Market Drivers report.  These 10 market categories represented a little over two-thirds of the total production value of all electronic systems in 2014.

Cellphones expanded their lead over standard personal computers (desktops and notebooks) as the largest electronic systems market in 2014 after overtaking standard PCs for the first time in 2013. Cellphones accounted for 18 percent of total electronics systems sales ($265.2 billion) versus about 13 percent for standard PCs ($196.0 billion) in 2014.  As seen in Figure 1, cellular phone sales are projected to rise by a CAGR of 5.6 percent in the 2013-2018 period, while standard PC revenues are expected to slump by an annual rate of -1.1 percent, partly due to the popularity of tablet computers and growing use of smartphones to access the Internet.

ic fig 1

 

Figure 2 shows the market sizes and projected growth rates of IC sales for 11 major electronic system categories covered in the 2015 IC Market Drivers report.  After dominating IC sales for most of the last two decades, standard PCs were unseated by cellphones as the largest end-use IC application in 2013 and the gap widened in 2014.  Cellular handsets accounted for 25 percent of IC sales in 2014, while standard PCs represented about 21 percent of the total.  IC sales for standard PCs have stalled out while cellphone IC revenues are projected to grow by a CAGR of 8.7 percent between 2013 and 2018.  Among these 11 end-use market segments, IC sales growth is expected to be the strongest in systems for connections to the Internet of Things (a CAGR of 22.3 percent) in the five-year forecast period.  IC revenues generated by these 11 end-use systems categories represented nearly 80 percent of total integrated circuit sales worldwide in 2014.

ic fig 2

 

IC Market Drivers 2015—A Study of Emerging and Major End-Use Applications Fueling Demand for Integrated Circuits examines the largest, existing system opportunities for ICs and evaluates the potential for new applications that are expected to help fuel the market for ICs.

“Embedded die in substrate is a promising packaging technology,” comments Yole Développement (Yole) in its latest advanced packaging report entitled “Fan-Out and Embedded Die: Technologies & Market” (Feb. 2015 Edition – Yole Développement). According to Yole’s team, this approach becomes more and more attractive for potential customers because of its numerous advantages. Embedded die in substrate: what are the next steps for the growth?

“The embedding allows a smaller form-factor, and it can be done using a mature manufacturing chain, providing low costs,” explains Jérôme Azemar, Technology & Market Analyst, Advanced Packaging and Manufacturing at Yole Développement. “The approach also offers good thermal performance, high integration capability and low inductance thanks to shorter connections”, he adds.
But these advantages still have to be realistic at high volume manufacturing scales before being able to convince customers. Embedding die in laminate substrates is indeed a promising packaging principle, but it has to overcome several challenges.

embedded die

One of these challenges is the supply chain. The process is being pushed by printed circuit board manufacturers such as AT&S and can create a new supply chain, bringing new players into the semiconductor industry. This new supply chain comes along with new business models, including packagers, module sellers, IDMs pushing for embedding solutions and R&D laboratories.

One of the supply chain’s main advantages is the usage of a mature and affordable manufacturing chain created initially for PCB manufacturing. That achieves low cost technology that would allow easier component integration, with easy access to both sides of the chips. However, a new supply chain brings with it a lack of technical experience with embedding processes and questions about business models that require clarification.

Under the report “Fan-out and Embedded Dies: Technologies & Market Trends,” Jérôme Azemar and the advanced packaging team, analyze the applications that will drive the embedded die market in the future and the potential keys for success.

Single die are the first products currently being sold, demonstrating the technology’s capabilities.

They are essentially low I/O applications with easy to embed dies such as DC/DC converters for wireless products. Yole’s expectations are that the technology will show its real potential with more complex systems such as power application SiPs. There, actives and passives will fully benefit from embedded packages thanks to good heat management and low inductance.

Among the technical requirements, one is especially important: pad pitch on the die. In order to reach volume in the mobile/wireless market, pad pitch has to go below 150μm. Some players, like TDK-EPCOS, claim they already have products with 50μm pitch.

If technical and logistic objectives like this are achieved, and if an application provides a real boost in terms of initial large volumes, the overall market will be able to grow rapidly in the near future.
Under this new advanced packaging technology & market study, Yole, the More than Moore market research and strategy consulting company gives an overview of players involved in embedded die packages. The company describes the strategies they’re hoping will overcome technical issues such as yield, resolution and reliability and their choices of business model to enter the semiconductor packaging market with.

Under this report, Yole’s analysts also detail the different milestones this technology must pass if it is to reach high volumes, and what room there is for innovations where embedded die could provide clear added value. Yole’s study report highlight the different possibilities under investigation or required by customers to achieve volume manufacturing and sustainability. These include details of technical requirements, multi-sourcing and standardization needs and integration roadmaps.

By Shannon Davis, Web Editor

Chipmaker NXP Semiconductors NV announced Sunday night that it has agreed to buy Freescale Semiconductor Ltd for $11.8 billion and merge business operations. The combined enterprise values at just over $40 billion and will create a new leader in the auto and industrial semiconductor markets.

“Financially, this deal makes sense. By being bigger, you limit the impact of the product cycles and volatile end markets,” said RBC analyst Doug Freedman.

NXP and Freescale shares were trading about 16 and 11 percent higher, respectively, on Monday morning, reflecting investors’ confidence in the deal. NXP anticipates achieving cost savings of $200 million in the first full year after closing the transaction, with a clear path to $500 million of annual cost synergies. Freescale shareholders will receive $6.25 in cash and 0.3521 of an NXP ordinary share for each Freescale common share held at the close of the transaction.

This deal is the fourth semiconductor merger and acquisition so far this year, and it will be the biggest of these by far.

Last month, Avago Technologies agreed to would buy wireless networking company Emulex Corp for more than $600 million, while MaxLinear said it would buy Entropic Communications Inc for $287 million. In January, Lattice Semiconductor announced the acquisition of Silicon Image for $600 million.

Freescale was originally created as a division of Motorola in 1948, which would become one of the world’s first semiconductor businesses. Freescale would eventually leave Motorola in 2004, to be acquired in 2006 by Blackstone Group LP, Carlyle Group LP, TPG and Permira. Now based out of Austin, Texas, Freescale currently operates in more than 25 countries, while generating net sales of $4.6 billion in 2014.

NXP is based in Eindhoven, the Netherlands and has operation in more than 25 countries, generating revenue of $5.7 billion in 2014.

“In the short-term, we will continue to benefit with the secular trend of increasing semiconductor content in auto market. The trend has a positive effect on both companies’ portfolio of products. Longer term, the merged company is superbly positioned to become the thought leader in the merging areas of secure cars and Advanced Driver Assistance Systems to facilitate smarter driving,” NXP said on a Monday investor call.

The transaction is expected to close the second half of the 2015 calendar year, after which Freescale shareholders will own approximately 32 percent of the combined company.

Credit Suisse acted as financial adviser to NXP, while Morgan Stanley advised Freescale.

“Fan-Out Wafer Level Packaging (FOWLP) is already in high-volume” announces Yole Développement (Yole) in its new report, Fan-Out and Embedded Die: Technologies & Market. According to Yole’s analysts, FOWLP market reaches almost $200M in 2015. And the More than Moore market research and strategy consulting company, Yole expects 30% CAGR in the coming years. What can explain such a great potential?

Fan-Out Wafer Level Packaging (FOWLP) started volume commercialization in 2009/2010 and started promisingly, with initial push by Intel Mobile. However, it was limited to a narrow range of applications, essentially single die packages for cell phone baseband chips. But this growth reached its limit in 2011. And in 2012 big fab-less wireless/mobile players started slowly volume production after qualifying the technology.

It faced strong competition from other packaging technologies, such as wafer-level chip scale packaging (WLCSP) in 2013/2014. Intel Mobile also backed off from the technology, and the main manufacturers reduced their prices in 2014, creating a transition phase with low market growth.

Today, according to Fan-Out and Embedded Dies: Technologies & Market Trends report, Yole’s analysts now expect strong growth. They explain: “The market is worth almost $200M and we anticipate 30% CAGR is in coming years”. One of the key factors driving this is the arrival of 2nd generation FOWLP. More customers are also being convinced, a wider range of potential applications reached, and technology qualifications started during the transition phase completed by strong fabless players.

What can explain such great potential? Primarily, mobile customers have high expectations of miniaturization and higher integration while keeping costs low. This leads naturally to WLP for cost and performance and system-in-package (SiP) solutions for integration and functionality. FOWLP has proven its ability to reach these targets. Its small form-factor and low cost potential shown in the 1st generation are now enhanced with high-integration capability of the 2nd generation.

“Benefiting from the delay in introducing 3D through-silicon via (TSV) architectures, FOWLP is currently seen as the best fit for the highly demanding mobile/wireless market and is attractive for other markets focusing on high performance and small size”, explains Jérôme Azemar, Technology & Market Analyst, Advanced Packaging & Manufacturing, Yole Développement.

Under this technology & market report, Yole provides a complete overview of the different market expectations and a detailed application-by-application breakdown. The company also describes the different strategies and products of each player involved in FOWLP, from the main outsourced assembly and test companies, like STATS ChipPAC and Nanium, to foundries like TSMC. Since cost is always the first driver, the report also focuses on equipment and material challenges and substrate size evolution, both for wafers and panels.

Graphene, a single-atom-thick lattice of carbon atoms, is often touted as a replacement for silicon in electronic devices due to its extremely high conductivity and unbeatable thinness. But graphene is not the only two-dimensional material that could play such a role.

University of Pennsylvania researchers have made an advance in manufacturing one such material, molybdenum disulphide. By growing flakes of the material around “seeds” of molybdenum oxide, they have made it easier to control the size, thickness and location of the material.

Unlike graphene, molybdenum disulfide has an energy band gap, meaning its conductivity can be turned on and off. Such a trait is critical for semiconductor devices used in computing. Another difference is that molybdenum disulphide emits light, meaning it could be used in applications like LEDs, self-reporting sensors and optoelectronics.

The study was led by A. T. Charlie Johnson, professor in the Department of Physics & Astronomy in Penn’s School of Arts & Sciences, and includes members of his lab, Gang Hee Han, Nicholas Kybert, Carl Naylor and Jinglei Ping. Also contributing to the study was Ritesh Agarwal, professor of materials science and engineering in Penn’s School of Engineering and Applied Science; members of his lab, Bumsu Lee and Joohee Park; and Jisoo Kang, a master’s student in Penn’s nanotechnology program. They collaborated with researchers from South Korea’s Sungkyunkwan University, Si Young Lee and Young Hee Lee.

Their study was published in the journal Nature Communications.

“Everything we do with regular electronics we’d like to be able to do with two-dimensional materials,” Johnson said. “Graphene has one set of properties that make it very attractive for electronics, but it lacks this critical property, being able to turn on and off. Molybdenum disulphide gives you that.”

Graphene’s ultra-high conductivity means that it can move electrons more quickly than any known material, but that is not the only quality that matters for electronics. For the transistors that form the basis for modern computing technology, being able to stop the flow of electrons is also critical.

“Molybdenum disulphide is not as conductive as graphene,” Naylor said, “but it has a very high on/off ratio. We need 1’s and 0’s to do computation; graphene can only give us 1’s and .5’s.”

Other research groups have been able to make small flakes of molybdenum disulphide the same way graphene was first made, by exfoliating it, or peeling off atomically thin layers from the bulk material. More recently, other researchers have adopted another technique from graphene manufacture, chemical vapor deposition, where the molybdenum and sulfur are heated into gasses and left to settle and crystalize on a substrate.

The problem with these methods is that the resulting flakes form in a scattershot way.

“Between hunting down the flakes,” said Kybert, “and making sure they’re the right size and thickness, it would take days to make a single measurement of their properties”

The Penn team’s advance was in developing a way to control where the flakes form in the chemical vapor deposition method, by “seeding” the substrate with a precursor.

“We start by placing down a small amount of molybdenum oxide in the locations we want,” Naylor said, “then we flow in sulfur gas. Under the right conditions, those seeds react with sulfur and flakes of molybdenum disulphide being to grow.”

“There’s finesse involved in optimizing the growth conditions,” Johnson said, “but we’re exerting more control, moving the material in the direction of being able to make complicated systems. Because we grow it where we want it, we can make devices more easily. We have all of the other parts of the transistors in a separate layer that we snap down on top of the flakes, making dozens and potentially even hundreds, of devices at once. Then we were able to observe that we made transistors that turned on and off like they were supposed to and devices that emit light like they are supposed to.”

Being able to match up the location of the molybdenum disulphide flakes with corresponding electronics allowed the researchers to skip a step they must take when making graphene-based devices. There, graphene is grown in large sheets and then cut down to size, a process that adds to the risk of damaging contamination.

Future work on these molybdenum disulphide devices will complement the research team’s research on graphene-based biosensors; rather than outputting the detection of some molecule to a computer, molybdenum disulfide-based sensors could directly report a binding event through a change in the light they emit.

This research also represents first steps that can be applied toward fabricating a new family of two-dimensional materials.

“We can replace the molybdenum with tungsten and the sulfur with selenium,” Naylor said, “and just go down the periodic table from there. We can imagine growing all of these different materials in the places we choose and taking advantages of all of their different properties.”