Category Archives: Wafer Level Packaging

Root cause deconvolution is a quick and cost effective way to determine the underlying root causes represented in a population of failing devices from test data alone.

BY GEIR EIDE, Mentor Graphics, Wilsonville, OR

With 22nm FinFET-powered laptops now available and foundries announcing timelines for single-digit manufacturing nodes, it’s clear not everybody got the memo declaring Moore’s law dead and obsolete. While each new manufacturing node introduces new defect mechanisms, one notable trend is the dramatic increase in number and complexity of design-sensitive defects. This means that in addition to the low yield seen initially as a new manufacturing process is introduced, variability from design to design makes yield a continuing challenge even as the process matures.

The obvious question to ask when you stare at a pile of failing devices is: Why are these devices failing? The pile can represent a number of different defect mechanisms (or root causes). Some may be familiar, while others are new. Some may be easy to find, while others are virtually invisible. Physical failure analysis (PFA) is used to find defects in failing devices, but this is a very costly and time consuming process. Determining what to submit to PFA is therefore a balancing act between controlling expense and finding the relevant defect. Wouldn’t it be great if you could determine the underlying root causes early, and pick the die for PFA that represents the causes of interest in an effective and low cost manner? This is the promise of a new scan test diagnosis technology called root cause deconvolution.

FIGURE 1. Typical application: Root Cause Deconvolution determines root cause distribution and devices most likely to fail for each root cause. Defect courtesy [2].

FIGURE 1. Typical application: Root Cause Deconvolution determines root cause distribution and devices most likely to fail for each root cause. Defect courtesy [2].

Software-based diagnosis of test failures is an established method for localizing defects in digital semiconductor devices. Diagnosis software determines the defect type and location for each failing device based on the design description, scan test patterns, and tester fail data. But diagnosis results contain ambiguity or noise. The diagnosis result for one specific die may point to more than one possible location. Each location may in turn have multiple properties or root causes. For example, the suspect location can span multiple layers (metal3, via4, metal4) while the true root cause is an open defect in just one of these layers. You may observe that many diagnosis results call out net segments that include a particular via type. What you cannot see from the diagnosis results alone is whether that is to be expected or not, i.e. whether this is a common via type or not. This means that plain diagnosis results cannot be used to determine the underlying root cause distribution. Similarly, you may see more bridges in metal3 than metal4, not knowing whether that is to be expected or if it points to a systematic defect. A method called zonal analysis manages this noise by finding relative differences in the diagnosis reports. This method is most effective for identifying hidden systematic defects at fairly high yields, such as the last 1%-2% in high volume manufacturing [1].

But until now there has not been a way to effectively eliminate the noise in the diagnosis results and determine the underlying root causes represented in a population of failing devices. The new root cause deconvolution (RCD) technology is based on Bayesian probability analysis, which is well-known in machine learning applications. It leverages design statistics such as critical area per net segment per metal layer and count of tested cells per cell type. The technology uses a probabilistic model that calculates the proba- bility of observing a set of diagnosis results for a given defect distribution. This model is then used to determine the most likely defect distribution for a given set of diagnosis results.

A typical application of RCD is shown in FIGURE 1. For one wafer, the failing cycles are recorded for devices that failed scan test patterns, and then layout- aware diagnosis is performed (1). RCD analysis is done on the diagnosis results, identifying the under- lying root cause distribution (2). This result can then be compared with equivalent distributions from the same design or comparable designs. Having this data available before any devices are submitted to PFA significantly accelerates the analysis time. You can then select the root cause of interest, in this case the most significant contributor. The RCD analysis will then identify the die that have the largest probability of failing because of this defect mechanism. Before submitting a die to PFA (4), you know where to look for the defect, and also what to look for.

In a comprehensive experiment [3], RCD results for four lots of failing devices correlated to the conclusions reached through inline inspection, failure analysis, and known process changes. RCD is a quick and cost effective way to determine the underlying root causes represented in a population of failing devices from test data alone. This provides significant value to the yield and failure analysis process at fabless semiconductor companies.

References

1. W. Yang, C. Hao, “Diagnosis-Driven Yield Analysis Improves Mature Yield”, Chip Design Magazine, Fall 2011.

2. M. Sharma, et.al., “Efficiently Performing Yield En- hancements by Identifying Dominant Physical Root Cause from Test Fail Data”, IEEE International Test Conference, 2008

3. B. Benware, et.al., “Determining a Failure Root Cause Distribution From a Population of Layout-Aware Scan Diagnosis Results”, IEEE D&T of Computers, Volume 29, Issue 1.

Applied Materials, Inc. today introduced the Endura Ventura PVD system that helps customers reduce the cost of fabricating smaller, lower power, high-performance integrated 3D chips. The system incorporates Applied’s latest innovations to its industry-leading PVD technology that enables the deposition of thin, continuous barrier and seed layers in through-silicon-vias (TSVs). Demonstrating Applied’s precision materials engineering expertise, the Ventura system also uniquely supports the use of titanium in volume production as an alternate barrier material for lower cost. With the launch of the Ventura system, Applied is expanding its comprehensive toolset for wafer level packaging (WLP) applications, including TSVs, redistribution layer (RDL) and Bump.

TSVs are a critical technology for vertically fabricating smaller and lower power future mobile and high-bandwidth devices. Vias are short vertical interconnects that pass through the silicon wafer, connecting the active side of the device to the back side of the die, providing the shortest interconnect path between multiple chips. Integrating 3D stacked devices requires greater than 10:1 aspect ratio TSV interconnect structures to be metallized with copper. The new Ventura tool solves this challenge with innovations in materials and deposition technology to manufacture TSVs more cost-effectively than previous industry solutions.

“Building on 15 years of leadership in copper interconnect technology, the Ventura system enables fabrication of robust high-aspect ratio TSVs, with up to 50 percent barrier seed cost savings compared to copper interconnect PVD systems,” said Dr. Sundar Ramamurthy, vice president and general manager of Metal Deposition Products at Applied Materials. “These innovations deliver a higher-performance and more functional, yet, compact chip package with less power consumption to meet leading-edge computing needs. Customers are realizing the benefits of this new PVD system and are qualifying it for volume manufacturing.”

Supporting the manufacture of high-yielding 3D chips, the Ventura system introduces advances in ionized PVD technology that assure the integrity of the barrier and seed layers that are critical to superior gap-fill and interconnect reliability. These developments significantly improve ion directionality to enable the deposition of thin, continuous and uniform metal layers deep into the vias to achieve the void-free fill necessary for robust TSVs. With the improvement in directionality, higher deposition rates can be achieved, while the amount of barrier and seed material needed can be reduced. These attributes of the Ventura system and the adoption of titanium as an alternate barrier are expected to improve device reliability and reduce the overall cost of ownership for TSV metallization.

Applied Materials, Inc. provides equipment, services and software to enable the manufacture of advanced semiconductor, flat panel display and solar photovoltaic products.

STATS ChipPAC Ltd., a provider of advanced semiconductor packaging and test services, today introduced encapsulated Wafer Level Chip Scale Package, a packaging technology that raises the industry standard of durability for Wafer Level Chip Scale Packaging (WLCSP).

WLCSP is one of the fastest growing segments in the semiconductor industry driven by mobile electronics that require compact, high performance packages. Although WLCSP is considered a mature technology, there is now an increased sensitivity in the semiconductor industry to reduce the possibility of damage to the package during the surface mount technology (SMT) process. As the industry transitions to more advanced silicon node products, the exposed die that is inherent in the WLCSP design becomes more of a concern due to the fragile dielectric layers.

“WLCSP is a bare die package that is constantly exposed to potential cracking, chipping and handling damages before or during the SMT process. This is particularly true for advanced node products where the die is very thin and dielectric layers are extremely fragile,” said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer, STATS ChipPAC. “As mobile device manufacturers tighten their technical specifications to reach new levels of reliability in their products, the industry will see more stringent component level and board level reliability (BLR) requirements. eWLCSPTM is a robust packaging solution that cost effectively addresses the increased durability requirements for our customers in advanced silicon nodes down to 28nm.”

eWLCSPTM features a thin protective coating on the four sidewalls of the die, achieving increased durability and reliability within the standard WLCSP size specification. The significant benefit of encapsulation is the light and mechanical protection for the bare die. The protective layer also safeguards the silicon during socket insertion for test. eWLCSP delivers electrical performance that is equivalent to standard WLCSP with proven results in component level reliability (CLR), temperature cycle on board (TCoB) and drop test.

The encapsulation advantages in eWLCSP are the result of STATS ChipPAC’s new FlexLine manufacturing method. FlexLine is an innovative approach to wafer level manufacturing that seamlessly processes multiple silicon wafer diameters in the same manufacturing line, delivering unprecedented flexibility in producing both fan-out and fan-in packages. Flexline is based on STATS ChipPAC’s well established, high volume manufacturing process for fan-out wafer level packaging that provides the ability to scale a device to larger panel sizes for a compelling cost reduction compared to conventional wafer level packaging methods. The FlexLine process has been qualified at advanced silicon nodes down to 28nm, ball pitches down to 0.40mm and body sizes as small as 2.5×2.5mm.

Dr. Han continued, “FlexLine is a strong manufacturing platform that enables unique technology enhancements such as eWLCSP and a cost effective manufacturing approach to wafer level packaging. Using the FlexLine method, 200mm incoming wafers can be reconstituted into 300mm or larger panel sizes, providing customers with significant per unit cost reduction as the panel size increases. In addition, a conventional WLCSP can be converted to eWLCSP without any silicon design change required, regardless of the current silicon wafer diameter.”

­Ziptronix Inc. and EV Group today announced they have successfully achieved submicron post-bond alignment accuracy on customer-provided 300mm DRAM wafers. The results were achieved by implementing Ziptronix’s DBI Hybrid Bonding technology on an EVG Gemini FB production fusion bonder and SmartView NT bond aligner. This approach can be used to manufacture fine-pitch 3D ICs for a variety of applications including stacked memory, advanced image sensors and stacked systems-on-chip (SoCs).

“The performance of DBI Hybrid Bonding technology is not limited by connection pitch, but requires the right alignment and placement tool with an ability to scale that has been a challenge to find until now,” said Paul Enquist, CTO and VP Engineering at Ziptronix. “EVG’s fusion bonding equipment has been optimized to achieve consistent submicron post-bond alignment accuracy. This advancement in alignment accuracy provides a clear path to high-volume manufacturing (HVM) of our technology.”

Pitch scaling on next-generation 3D technologies is expected to continue for many years to come. Fine-pitch hybrid bonding is already in use in high-performance 3D memory products, and has been announced for HVM of 3D image sensors. DBI Hybrid Bonding can be used at the die or wafer level; however, wafer-level bonding enables a great cost benefit by bonding all the die at once. With much of the processing for DBI Hybrid Bonding taking place at wafer scale, there is the added benefit of low cost-of-ownership.

“Demonstrating submicron accuracy is critical to achieving fine-pitch connections in HVM for a wider variety of applications,” said Paul Lindner, Executive Technology Director at EVG. “As the industry pushes to realize 3D ICs, joint efforts such as our work with Ziptronix to develop manufacturing approaches offer customers a tremendous value-add.”

Ziptronix Direct Bond Interconnect Hybrid Bonding is a conductor/dielectric bonding technology that includes a variety of metal/oxide and/or nitride combinations, does not use adhesives and is currently the most suitable for volume manufacturing in the marketplace. It allows for strong, room temperature dielectric bonding, low temperature conductive bonding and finer-pitch interconnect over Cu/Cu or other metal bonding because the bond occurs between both the dielectric and the conductive surfaces, which effectively bonds the entire substrate interface area.

EVG’s SmartView Automated Bond Alignment System for Universal Alignment offers a proprietary method of face-to-face wafer-level alignment, which is key to achieving the required accuracy in multiple wafer stacking for leading-edge technologies. In addition to improving alignment capabilities on its SmartView bond aligner to reach submicron accuracies, EVG has optimized it so that surfaces can be prepared simultaneously for bonding, electrical connectivity and mechanical strength.

Later this month, IC Insights’ May Update to The 2014 McClean Report will show a ranking of the 1Q14 top 25 semiconductor suppliers.  A preview of the top 20 companies is presented in Figure 1.  The top 20 worldwide semiconductor (IC and O S D—optoelectronic, sensor, and discrete) sales ranking for 1Q14 includes nine suppliers headquartered in the U.S., three in Taiwan, three in Europe, two in South Korea, two in Japan, and one in Singapore, a relatively broad representation of geographic regions.

The top-20 ranking includes three pure-play foundries (TSMC, GlobalFoundries, and UMC) and six fabless companies.  It is interesting to note that the top four semiconductor suppliers all have different business models.  Intel is essentially a pure-play IDM, Samsung a vertically integrated IC supplier, TSMC a pure-play foundry, and Qualcomm a fabless company.

IC foundries are included in the top 20 ranking because IC Insights has always viewed the ranking as a top supplier list, not as a marketshare ranking, and realizes that in some cases semiconductor sales are double counted.  With many of our clients being vendors to the semiconductor industry (supplying equipment, chemicals, gases, etc.), excluding large IC manufacturers like the foundries would leave significant “holes” in the list of top semiconductor suppliers.  Foundries and fabless companies are clearly identified in Figure 1.  In the April Update to The McClean Report, marketshare rankings of IC suppliers by product type were presented and foundries were excluded from these listings.

It should be noted that not all foundry sales should be excluded when attempting to create marketshare data. For example, although Samsung had a large amount of foundry sales in the first quarter, most of its sales were to Apple.  Apple does not re-sell these devices, so counting these foundry sales as Samsung semiconductor sales does not introduce double counting.

Overall, the list shown in Figure 1 is provided as a guideline to identify which companies are the leading semiconductor suppliers, whether they are IDMs, fabless companies, or foundries.

Figure 1

Figure 1

Outside of the top five spots, there were numerous changes within the 1Q14 top-20 semiconductor supplier ranking.  As shown, MediaTek jumped up four positions in 1Q14 as compared to 1Q13 into 12th place. MediaTek continues to experience extremely strong demand for its devices in the booming low-end smartphone business in China and other Asia-Pacific locations.  Moreover, MediaTek and MStar finalized their merger on February 1, 2014.  Annual post-merger sales for MediaTek are expected to be well over $6 billion.

After Avago’s purchase of LSI Corp. on May 6, 2014, the combined annual semiconductor sales run-rate of the two companies is likely to be over $5 billion.  Also, last year’s Micron/Elpida merger essentially created a new “giant” semiconductor company with Micron’s sales expected to be over $17 billion this year.

It should be noted that the sales of Micron and Elpida (merged on July 1, 2013), MediaTek and MStar, and Avago and LSI use the combined sales of the two companies for both 1Q13 and 1Q14, regardless of when the merger actually occurred.  This was done in an attempt to make the company’s 1Q14/1Q13 sales growth rates more directly comparable and give a clearer picture of the merged company’s sizes going forward.

Another potential merger to keep a watch for in the future is Fujitsu and Panasonic.  In February of this year, the two Japan-based companies signed a memorandum of understanding to combine the two companies’ system LSI businesses and form a new fabless semiconductor company.  IC Insights estimates that the combined 1Q14 semiconductor sales of these two companies was about $1.25 billion (down from $1.44 billion in 1Q13), which would have ranked the “merged” company as the sixteenth largest semiconductor company in the first quarter of this year.

In total, the top 20 semiconductor companies’ sales increased by 9% in 1Q14 as compared to 1Q13, which was two points higher than IC Insights’ current 7% forecast for total worldwide semiconductor market growth this year.  As shown, it took total semiconductor sales of just over $1.0 billion to make the 1Q14 top 20 ranking.

Figure 2 shows that there was a 58-percentage-point range of year-over-year growth rates among the 1Q14 worldwide top 20 semiconductor suppliers—from +48% for MediaTek/MStar to -10% for ST (it should be noted that excluding the legacy ST-Ericsson products, ST’s 1Q14/1Q13 sales increased 1%).

Figure 2

Figure 2

The success of the fabless and fab-lite business models and the continued strong growth of the memory market are evident when examining the top 20 semiconductor suppliers that logged double-digit growth in 1Q14.  As shown, 10 of the top 11 1Q14 performers were either memory suppliers (SK Hynix, Micron, and Samsung) or fabless/fab-lite companies (MediaTek, AMD, Infineon, Freescale, Avago/LSI, NXP, and Nvidia).

Deca Technologies, an electronic interconnect solutions provider to the semiconductor industry, today announced that it has shipped its 100-millionth component. The company attributes this milestone to strong demand from portable electronics manufacturers for wafer-level chip scale packages (WLCSP) manufactured using Deca¹s unique, integrated Autoline production platform, which is designed to achieve faster time-to-market at lower cost.

Leveraging advanced Autoline volume production technologies from SunPower Corp., a solar technology and energy services provider, Deca achieved this milestone by addressing cycle time and capital cost challenges that semiconductor device manufacturers have struggled with using the conventional approach to WLCSP manufacturing.

Demand for WLCSP is being driven by manufacturers of wireless connectivity, audio and power management components for the handset and wearable electronics markets. Demand fluctuations in these markets can lead to challenges in managing inventories. Customers have found that Deca’s unique approach helps them better manage their inventories and reduce their working capital.

“Congratulations to the Deca team on achieving this significant milestone,” said Brent Wilson, senior vice president of the Global Supply Chain Organization at ON Semiconductor. “Deca’s innovative technologies and focus on customer service have made the company a valuable part of our supply chain. We look forward to continued shared success in the future.”

“Reaching 100 million units is an important milestone for Deca because it validates our unique approach to WLCSP manufacturing,” said Chris Seams, CEO of Deca Technologies. “Based on the demand forecasted by our customers, we anticipate passing the half-billion mark in unit shipments this year.”

“As a customer of Deca Tech, Cypress has used the fast New Product Introduction capability of Deca to streamline its back-end process and achieve cycle times of fewer than three days for full turnkey wafer-level packaging, test and singulation,” said T.J. Rodgers, president and CEO of Cypress Semiconductor Corp. “We are even more pleased with Deca as our subsidiary,” Rodgers continued. “The company’s quick ramp to the 100-million-unit milestone is proof of the value proposition that we envisioned when we invested in this market.”

The Global Semiconductor Alliance (GSA) is celebrating 20 years of industry collaboration this year. Over the past 20 years, GSA has recognized public and private semiconductor companies that have demonstrated excellence through their success, vision, strategy and future opportunities in the industry. This year’s commemorative Award’s Dinner Celebration will be held on Thursday, December 11, 2014, at the Santa Clara Convention Center in Santa Clara, Calif.

The celebration honors the achievements of semiconductor companies in several categories ranging from outstanding leadership to financial accomplishments, as well as overall respect within the industry. GSA is currently accepting nominations for the following award categories:

Most Respected Private Semiconductor Company Award
Outstanding EMEA Semiconductor Company Award
Start-Up to Watch Award

The “Most Respected Private Semiconductor Company Award” is designed to identify the private company garnering the most respect from the industry in terms of its products, vision and future opportunity. GSA’s Private Awards Committee, comprised of members of the Emerging Company CEO Council, venture capitalists and select serial entrepreneurs in the industry, reviews all private semiconductor companies, conducts analysis of each company’s performance and likelihood of long-term success, and provides a list of respectable private companies to be voted on by GSA membership. On-line voting takes place to allow GSA members, including semiconductor companies and partners, to cast a ballot for the private semiconductor company that they most respect. Nominations are open until June 27, 2014.

GSA’s Private Awards Committee selects up to two winners for the “Start-Up to Watch Award” by identifying the semiconductor company (or companies) that demonstrates the potential to positively change its market or the industry through the innovative use of semiconductor technology or a new application for semiconductor technology. Nominations will be accepted until June 27, 2014.

As a global organization, the GSA recognizes companies headquartered in the EMEA and APAC regions. Award winners are chosen by the leadership council of each respective region and are semiconductor companies that demonstrate the most strength when measuring products, vision, leadership and success in the marketplace. Nominations for the Outstanding EMEA Semiconductor Company Award will be accepted until July 11, 2014.

The GSA’s most prestigious award, the Dr. Morris Chang Exemplary Leadership Award recognizes individuals, such as its namesake, Dr. Morris Chang, for their exceptional contributions to drive the development, innovation, growth and long-term opportunities for the semiconductor industry. This year, there will be a special presentation honoring past Dr. Morris Chang Exemplary Leadership Award recipients.

“We are very excited to celebrate GSA’s 20 year evolution as a neutral industry platform as well as the proliferation of the entire semiconductor ecosystem at this year’s dinner,” said Jodi Shelton, co-founder and president of GSA. “Since its inception in 1994, it has been an honor to be part of this remarkable industry and have the opportunity to recognize the companies that have had such an impact on growing it into the industry that it is today, an industry that is the bedrock of all modern technical innovation.”

In this week’s Nature Communications, imec presents the development of fullerene-free organic photovoltaic (OPV) multilayer stacks achieving a record conversion efficiency of 8.4 percent.  This breakthrough achievement is an important step to bring organic photovoltaic cells to a higher level in the competitive thin-film photovoltaics marketplace.

imec image 01

Organic solar cells are an interesting thin-film photovoltaic technology due to their compatibility with flexible substrates and tunable absorption window.  Although the power conversion efficiency of organic solar cells has increased rapidly in the last decade, further enhancements are needed to make the production of organic photovoltaics more easily scalable into industrial production processes. Imec’s organic solar cells with record 8.4 percent power conversion efficiency were realized by introducing two innovations. Firstly, the implementation of fullerene-free acceptor materials resulted in high open-circuit voltages and useful absorption spectra in the visible spectrum. Secondly, high short-circuit currents were achieved by developing a multilayer device structure of three active semiconductor layers with complementary absorption spectra, and an efficient exciton harvesting mechanism.

Fullerenes are the dominant acceptor materials in current OPV cells due to their ability to accept stable electrons and their high electron mobility. However, the small absorption overlap with the solar spectrum limits the photocurrent generation in fullerene acceptors, and their deep energy level for electron conduction limits the open-circuit voltage. Imec implemented two fullerene-free materials as acceptor, increasing open-circuit voltages compared to OPV cells with fullerene acceptors.

To increase the efficiency of organic solar cells, complex tandem architectures are often proposed to combine the exciton harvesting of multiple photo-active materials. The imec team now proposes a simple three-layer stack to improve the spectral responsivity range. This device architecture comprises two fullerene-free acceptors and a donor, arranged as discrete heterojunctions. In addition to the traditional exciton dissociation at the central donor-acceptor interface, the excitons generated in the outer acceptor layer are first relayed by energy transfer to the central acceptor, and subsequently dissociated at the donor interface.  This results in a quantum efficiency above 75 percent between 400nm and 720nm. With an open-circuit voltage close to 1V, a remarkable power conversion efficiency of 8.4 percent is achieved. These results confirm that multilayer cascade structures are a promising alternative to conventional donor-fullerene organic solar cells.

These results were presented in Nature Communications.

The research leading to these results has received funding from the European Community’s Seventh Framework Programme.

STATS ChipPAC, a provider of advanced semiconductor packaging and test services, has designed and implemented an innovative new manufacturing method that is a significant paradigm shift from conventional wafer level manufacturing. This breakthrough approach, known as FlexLine, delivers an unmatched level of flexibility and cost savings for wafer level packaging (WLP).

With conventional WLP, an integrated circuit (IC) is fabricated, packaged and tested while still in a wafer format to streamline the manufacturing process. WLP leverages the same semiconductor equipment infrastructure as wafer fabrication which is progressively more expensive for larger wafer diameters and finer silicon (Si) geometries. The costs associated with transitioning to larger wafer diameters have resulted in extreme pricing pressures on WLP, particularly for mature technology such as wafer level chip scale packaging (WLCSP).

“Growing demand for WLCSP in a range of advanced mobile products, from low-cost to high-end smartphones and tablets, is driving capacity constraints in the industry, particularly with 200mm wafers. This is causing extreme pressure on our customers to weigh the high cost of transitioning to more advanced silicon nodes against the need to achieve dramatic cost reductions for more competitive end products,” said Chong Khin Mien, Senior Vice President of Product and Technology Marketing, STATS ChipPAC. “Capacity and cost challenges for WLCSP exist today in 200mm and 300mm wafer diameters and will inevitably intensify when the semiconductor industry transitions to 450mm wafers. This is an exciting time to drive a fundamental change in the manufacturing process for WLCSP.”

STATS ChipPAC’s new FlexLine method is an innovative approach to wafer level manufacturing that provides freedom from wafer diameter constraints while enabling supply chain simplification and significant cost reductions that are not possible with a conventional manufacturing flow. FlexLine seamlessly processes multiple silicon wafer diameters in the same manufacturing line without changing equipment sets or bill of materials used in the packaging process. In fact, FlexLine enables customers to simplify their supply chain across multiple devices, thereby achieving significant cost reductions that are not possible with a conventional manufacturing flow.

“STATS ChipPAC is driving a significant paradigm shift in wafer level packaging with our FlexLine method. We have leveraged our proven reconstitution process, which has produced more than half a billion units of fan-out wafer level packages, to extend flexibility and cost advantages to fan-in WLCSP devices. We are the first company in the world to introduce a WLP method that is completely independent of incoming wafer sizes, including future 450mm wafer size, and delivers unprecedented flexibility in producing both fan-out and fan-in packages on the same manufacturing line,” said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer, STATS ChipPAC.

By normalizing multiple wafer diameters to a uniform processing size through reconstitution, the original wafer diameters become irrelevant as this no longer dictates manufacturing capacity or limits process capabilities. When 200mm wafers are reconstituted into 300mm or larger panel sizes, customers have greater potential for cost reduction than conventional WLP manufacturing. As the panel size increases, the cost of producing wafer level packages drops significantly when compared to conventional WLP methods.

Dr. Han noted, “With FlexLine, we are able to help our customers achieve at least a 15- 30% cost reduction using the optimum design requirements for their WLCSP devices. Later this year we will introduce unique technology enhancements to WLCSP that improve the reliability performance over WLCSPs produced with conventional methods. Our FlexLine method provides a strong manufacturing platform that enables future innovation in our wafer level packaging portfolio.”

GLOBALFOUNDRIES and Fraunhofer Institute for Integrated Circuits IIS today announced the extension of their long-term collaboration, focusing on 40nm and 28nm processes. GLOBALFOUNDRIES will also join the European Multi Product Wafer (MPW) Program EUROPRACTICE.

Through the collaboration GLOBALFOUNDRIES will offer its leading-edge foundry capabilities to Fraunhofer IIS as an aggregator, and Fraunhofer will enable the academic network in Europe to get access to GLOBALFOUNDRIES’ process technologies and Process Design Kits (PDK) via EUROPRACTICE.

“As one of the largest foundries worldwide and the largest wafer manufacturer in Europe we are proud to enter this prestigious program,” said Karl Lange, GLOBALFOUNDRIES Vice President of Sales for Europe. “With Fraunhofer as channel partner, combined with our broad technology portfolio and process know-how, we will add significant value to EUROPRACTICE.”

“The offer of GLOBALFOUNDRIES technologies down to 28nm to Europe’s universities and research institutes is an important step for EUROPRACTICE and will stimulate education and research in IC design,” said Josef Sauerer, Head of the Integrated Circuits and Systems Department at Fraunhofer IIS. “Also, our contract research with industries will benefit from GLOBALFOUNDRIES’ advanced technology portfolio”

Fraunhofer IIS and GLOBALFOUNDRIES started their collaboration in 2004 with the successful launch of 180nm and later 55nm programs. The extended collaboration will introduce technology nodes down to 28nm in the European Wafer Shuttle Program, helping European academia and research institutes to get access and support for CAD tools and ASIC prototyping at reduced costs.