Category Archives: Wafer Level Packaging

Green manufacturing: What you need to know

January 23, 2014

Tatsuo Enami Executive Officer & General Manager of Sales, Gigaphoton, Inc.

Green is the color for the decade and future decades as each country is developing its own standards for energy consumption and implementing its green initiatives. At one time considered a passing trend, green initiatives are now mandatory and force manufacturers to not only maintain corporate responsibility, but to positively impact the bottom line. As a result, high-volume manufacturers must work with vendors and suppliers that will help enable their overall cost and green manufacturing goals. Tracking and managing total operational costs is critical for sustaining a cost-effective, high-volume manufacturing (HVM) environment. Effective partners are already engaged in and developing systems on ‘green’ platforms using technology and services that balance performance with environmental impact, all within the barriers of cost. It includes companies that are designing systems using innovative techniques and new technologies that not only reduce the cost of energy, but also look at ways to reduce the cost of consumables, and the cost of downtime for HVM. By taking a total cost-of-operation approach when considering vendors and suppliers in a green manufacturing strategy, the resulting energy and environmental improvements can significantly lower fab operating costs.

When considering light sources, the power consumption of excimer lasers will continue to increase, as high-power lasers grow in demand especially for 450-mm processes, it has increased 4.5x over the past 6 years. As these processes gear up for HVM, the environmental impact cannot be ignored. The estimated cost for utilities for lasers, which includes electricity consumption, gas consumption and heat management, will be approximately 30% of the total cost-of-operation. Clearly, reducing utility costs is critical. As a result, the true value of a laser for HVM weighs heavily on its effectiveness in controlling utility costs. To address this issue, several companies are working to find solutions. Gigaphoton is currently developing a new hybrid laser system that utilizes a solid-state laser chamber. This system will require a maximum power of only 36kW compared to 60kW on the current system. When considering costs, the use of a hybrid laser system for HVM can result in approximately 40% less overall power consumption from the laser system alone. As there are others in development by other companies, this is an example of one solution that is in development to reduce energy and help enable HVM.

Keep in mind, a successful partner in your green manufacturing strategy will develop wider technology solutions that also include reducing the cost of consumables and the cost of downtime. Companies that have invested time and considerable resources to develop eco-friendly systems will provide the most effective all-around solutions. For example, to further reduce the overall cost-of-operation and maintenance, determine if your potential partner has a roadmap to develop longer-life consumables, or develop a system that removes some of the consumables all together. In the case with hybrid lasers, this would be the Line-Narrowing Module (LNM) and the Enhanced Front Mirror (EFM). Gas is another consumable that also affects downtime. New techniques for system optimization have been developed that reduce the amount of gas needed by 50% and minimize the down time for maintenance by half compared to existing laser systems.

There are many companies that are working to provide ‘green’ solutions for its customer. Gigaphoton has been leading the ‘green’ concept since 2007. By working with our customers to identify technology, performance and cost models for HVM, Gigaphoton has developed the EcoPhoton program. When considering a green manufacturing strategy for HVM, to significantly reduce the overall cost-of-operation partner companies need to provide solutions that reduce energy consumption, and also a roadmap to develop longer-life consumables, gas modules with less volume and refill requirements, all of which contribute to minimizing down time for maintenance. The right partner can make the environment greener as well as your bottom line. •

Progress on 450mm at G450C

January 23, 2014

Pete Singer, Editor-in-Chief

At Semicon Europa, Paul Farrar, general manager of G450C, provided an update on the consortium’s progress in demonstrating 450mm process capability. He said 25 tools will be installed in the Albany cleanroom by the end of 2013, progress has been made on notchless wafers with a 1.5mm edge exclusion zone, they have seen significant progress in wafer quality, and automation and wafer carriers are working.

G450C is an initiative by five big chip makers — Intel, TSMC, GLOBALFOUNDRIES, IBM and Samsung – partnered with New York state and CNSE. The main goal is to develop 10nm capability on 450mm wafers in 2015 or 2016. “What we have to demonstrate is that a film on 300mm, when we scale it up to 450mm, we can do it with the same capability and, more importantly, at a very significantly reduced cost per process area. In other words $/cm2 need to go down significantly. That’s how you hit the scaling that we’ve typically seen in a wafer transition which is in the 30% range,” Farrar said.

Farrar said the facility looks quite different now than it did in March, when it was fairly empty. 18 tools have been installed so far, with a total of 25 tools delivered into the Albany complex by the end of 2013. “2013 is the year that I call install and debug,” Farrar said. “We’ll have approximately 50% of the toolset in the facility by the year end. It doesn’t mean that they’ll all be up and running but they will be placed in Albany or virtually at the suppliers, with about 35% of the toolset coming in 2014 and the last little bit that will be delivered will be the lithography tool in early 2015.” The program is organized around unit processes, including: film deposition and growth, wafer clean and strip, CMP and other processes, inspection and metrology, etch and plasma strip, and lithography.

In call cases, G450C will have at least one process that will be required for the 14nm flow. In most cases (about 70%) they will have multiple suppliers, at least two and sometimes three. “At the end, we’ll have both unit process and what I would call modules – 2 or three step processes – demonstrated. And then our member companies will take those building blocks and they will put their devices and their IP and then go build out factories,” Farrar said.

G450C is also trying to take advantage of having a clean slate to make a switch from notched wafers – which provide a useful indicator regarding the crystal orientation of the silicon – to notchless wafers, which are perfect circles. “If you think about the physics around a notch, it really makes it difficult to get uniform films,” Farrar said. “A circle is a lower stress form. We get 1-1.5% better in getting closer to the edge. Using chips around the notch and perhaps getting to 1.5mm edge exclusion. We won’t get there if we don’t have notchless wafers. Our goal is to collaborate with our IC makers, our tool suppliers and materials suppliers, along with our facilities group.”

Probably the most critical part of the 450mm puzzle is lithography. Farrar said the consortia has been working with Nikon. “We were able to work with Nikon so that we now have immersion capability, in Japan, starting in June of 2014 and we’ll then have that tool installed in Albany at the end of the first quarter of 2015. We will have a true lithography capability which will enable us to get the efficient and actual process recipes that the deposition supplier will need to see so that they can demonstrate the capabilities at the 450 wafer form factor,” he said. “In the interim, we’re working on DSA (directed self assembly). We’re starting to see some pretty good results. I don’t think this will be a high volume technique but it’s a way that we can get something that works started in the early process modules in 2013 and early 2014.”•

Besi and Imec collaborate on thermocompression technology

January 21, 2014

Today, at the SEMI European 3D TSV Summit, nanoelectronics research center imec and Besi, a global equipment supplier for the semiconductor and electronics industries, announced they are joining forces to develop a thermocompression bonding solution for narrow-pitch die-to-die and die-to-wafer bonding with high accuracy and high throughput. Through this collaboration, imec and Besi will pave the way to industrial adoption of thermocompression bonding for 3D IC manufacturing.

3D IC technology, stacking multiple dies into a single device, aims to increase the functionality and performance of next-generation integrated circuits while reducing footprint and power consumption. It is a key technology to enable the next generation of portable electronics, such as smartphones and tablets, which require smaller ICs that consume less power.

One of the key challenges to making 3D IC manufacturing a reality is the development of high-throughput automated process flow for narrow-pitch, high-accuracy die-to-die and die-to-wafer bonding. Flip chip and reflow soldering, which are currently combined for bonding, require lenient bonding accuracy on large bump pitches (around 150-50µm bump pitch). Bump pitches need to further scale down to 40-10 µm to realize a sufficiently high performance. This needs high accuracy in bonding within the range of 1-2um @3sigma. Moreover, an automatic process flow is essential for industrial adoption. Thermocompression bonding is a method that enables this high bonding accuracy on narrow bump pitches, although with this comes long cycle times due to temperature and pressure profiles and processing methods which hinder industrial adoption of this technology up to now.

Imec and Besi will conduct joint research to develop a high-throughput thermocompression bonder in an automated process flow, with high accuracy and shorter cycle times, paving the way to enabling a manufacturable 3D, 2.5D and 2.5D/3D hybrid technology.

“We are excited to work with a key research center such as imec and leverage its expertise in fine pitch bonding materials and processes to increase the yield and reliability of our equipment ,” said Richard Blickman, CEO at Besi. “This collaboration will enable us to benchmark our Chameo tool to meet the industrial needs of the semiconductor industry, offering our customers a viable and effective solution for 2.5D/3D IC manufacturing.”

Intel vs. TSMC: An Update

January 21, 2014

By Zvi Or-Bach, President and CEO of MonolithIC 3D

On January 14, 2014 we read on the Investors.com headlines page – Intel Seen Gaining Huge Pricing Advantage Over TSMC. Just three days later comes the responding headline: TSMC: We’re “Far Superior” to Intel and Samsung as a Partner Fab.

These kinds of headlines are not seen too often in the semiconductor business domain and it is not clear what the objectives are for such. It will be hard to believe that this is an attempt to manipulate the investor community, yet there are only a handful of super high volume design wins that are driving the leading edge devices, and for those wins the fight should be taking place in the ‘board’ room. So, let’s dive a bit into the details behind these headlines.

The first headline relates to Jefferies analyst Mark Lipaci releasing an analysis report stating: “Intel will have a die size and transistor cost advantage over Taiwan Semiconductor (TSM) for the first time by fourth-quarter 2014, which could lead to a 50% pricing advantage in processors in 12 months, and a 66% pricing advantage in 36 months.” We can find more information in the blog titled: Intel: Primed for Major Phone, Tablet Share on Cheaper Transistors, Says Jefferies. Quoting Lipaci: “At the same time that Intel has started focusing on computing devices in mobile form factors, it appears that TSMC is hitting a wall on the transistor cost curve. The chart below was presented by TSMC’s CTO. We believe that due to Intel’s larger R&D budget, its recent focus on the mobile/tablet market, and its higher R&D spend relative to TSMC, that it will produce a lower cost transistor than TSMC for the first time ever in 4Q14. We believe Intel extends that cost lead 24 months after than in 2016.”

Lipaci then used the following chart to illustrate the build up of Intel advantage vs. TSMC.

The Jefferies report goes further and provides the following charts for 14nm and 10nm.

Clearly, the primary advantage that the report is pointing out is the lack of the double margin associated with the foundry model vs. the IDM model. It seems that this argument has clearly been disproven by now. In the early days of the foundry industry most IDMs would argue that the foundry model would not work because of the double margin aspect – the foundry would need about 50% gross margin and then the fables company would need an additional 50% gross margin – which would make it completely uncompetitive vs. the IDM. Twenty years later it was proven, again, that there is no “free lunch.” The chip fabrication business needs a margin to be sustainable and the design business needs a margin to be sustainable. And the better business model is to have those managed by different companies as each could build excellence in its own value proposition. Intel did enjoy for many years effective exclusivity in the Windows based processors. Intel has not been able so far to show much success in mobile or any other non-Windows market. Since Intel is now trying to position themselves as a better foundry than TSMC, then clearly for their potential foundry customers this double margin argument is moot.

The charts above also compare Intel’s cost advantage vs. TSMC older nodes (Intel’s 14nm vs. TSMC’s 20 nm and Intel’s 10nm vs. TSMC’s 16nm). It is not clear that Intel is so far ahead. Intel 14nm had been delayed to the first quarter of 2014 and TSMC has committed to be in volume production in the later part of 2014. But the real competition is on the ability to bring fabless companies to volume using one’s advanced process node. Key to this is the availability of libraries, EDA full tool set support, and major IP such as ARM processors. It is far from being clear that Intel is really far ahead of TSMC in this critical area. And then, these days it is not so clear that using a more advanced process node buys one an end-device cost advantage. In fact, the foundries have already made it clear that beyond the 28nm node they do not see cost reduction, due to the extra cost associated with advanced node lithography and other issues. Even Intel admitted at their latest analyst day that advanced nodes are associated with escalating depreciation and other costs, as illustrated by the following Intel chart – see the left most graph.

We should note that the Y axes of these graphs are logarithmic which indicate a significant increase of deprecation costs. However, Intel claims it will more than neutralize this increase of costs by accelerating the dimensional scaling when going to 14nm and 10nm, as is presented with the middle graph above. This would lead to an overall sustaining of the historical cost per transistor reduction as is illustrated by the rightmost graph above. Note: the asterisk (*) on those graphs indicates that numbers relating to 14nm and 10nm are forecasts only. Since Intel is committed to be in volume production at the 14nm node any day now, the number associated with 14nm should not be a forecast anymore and we hope to see them released soon.

The simple indication of technology node effective transistor density these days would be the bit cell size. As we have presented many times before, modern SoC device area is dominated by the embedded 6T SRAM. At IEDM 2013, TSMC made public their 6T SRAM bit cell area for 16nm: 0.07 sq. micron. We could not find any Intel public release for their 14nm 6T SRAM bit cell size. We did find an Intel chart for older nodes. This 6T bit cell size chart was presented at IDF2012:

Accordingly, the 14nm node 6T SRAM size for conventional dimensional scaling should be 0.092 * (14/22)² = 0.037 sq. micron. And if Intel can really scale more aggressively to compensate for the extra capital costs then their 6T SRAM at 14nm should be about 0.03 sq. micron or even smaller. As we don’t have any official number we could wait until their early production devices of the 14nm node get analyzed or to the eventual release of their number. But short of an official number, we did find a 2013 presentation from the TRAMS project, of which Intel is a partner, as illustrated in the following charts:

It is now clear that EUV will not be available for the 14nm node, and accordingly the bit cell size from the chart above is 0.062 sq. micron. This is a bit better than that of TSMC but a far cry from 0.03 sq. micron.

If Intel does have a really good number, it would be reasonable to expect that they will make it public soon, to entice the high volume fabless companies such as Qualcomm and Apple to explore Intel’s foundry option.

As for the Jefferies analyst assertion “We believe that due to Intel’s larger R&D budget, its recent focus on the mobile/tablet market, and its higher R&D spend relative to TSMC, that it will produce a lower cost transistor than TSMC”, it is not clear if Intel’s R&D budget is truly larger. TSMC’s R&D budget is dedicated to the foundry side of the business while Qualcomm, Apple, ARM and many other fabless vendors R&D budgets support the design part of any new product release. The total ecosystem behind TSMC and ARM is clearly not smaller than that of Intel. In this month’s SEMI ISS Conference, IC Insights provided very interesting numbers regarding the record of 2013 as was reported in a blog titled: Is Intel the Concorde of Semiconductor Companies?

Top 10 CAPEX Spenders in 2013:

Samsung $12B
TSMC $11.2B
Intel $10.5B
GF $5.5B
SK Hynix $3.7B
Micron $3B
Toshiba $2.9B
UMC $1.5B
Infineon $880M
10.ASE (OSAT) $770M

Yes, Samsung and TSMC both outspent Intel. Just wait until you see the capacity numbers and you will know why.

Top 10 IC Wafer Capacity Leaders in 2013:

Samsung 12.6%
TSMC 10%
Micron 9.3%
Toshiba 8%
SK Hynix 7%
Intel 6.5%
ST 3.5%
UMC 3.5%
GF 3.3%

10.TI 3.0%

Clearly, Intel is not larger than TSMC as a foundry and it is not clear why would it have a sustainable per transistor cost advantage.

Cost is important but it is far from being the only parameter when choosing a foundry partner. Selecting a foundry partner is truly selecting a partner. The design of leading edge devices is a very costly and lengthy effort, and has a pivotal effect on the business success for the fabless customer. TSMC had built trustful relationships for many years with its fabless customers. It is not clear how easy it is going to be for Intel to become a trustful foundry partner. So far it seems that Intel is still a proud IDM that insists that its customer will support its branding like the “Intel Inside” campaign or the recent announcement of Branding the cloud: Intel puts its stamp on cloud services across the globe. Intel’s repeating emphasis of their transistor cost advantage vs. that of TSMC suggests that Intel considers TSMC as their main competition for the mobile and tablet business. But then their consistent offering of SoC products for the space, as illustrated by the recent Intel chart below, and the Jefferies’ cost analysis above, suggests that Intel is actually an IDM competing with the likes of Qualcomm in this space. It may create concerns in the minds of potential fables customers.

And as a final note, we don’t know how much better the Intel process at 14nm and 10nm is vs. that of TSMC. We do know that when we ask someone for directions, if he says ‘make a right turn’ but with his hand he is pointing left, we should go ahead and turn left. So along with all of these confusing statements we learned just this week that Intel Cancels Fab 42, which was supposed to be the most advanced large capacity fab effort of Intel. I wonder if it should be considered as the hand pointing….

ARM and UMC extend 28nm partnership

January 16, 2014

ARM and global semiconductor foundry UMC this week announced an agreement to offer the ARM Artisan physical IP platform along with POP IP for UMC’s 28nm high-performance low-power (HLP) process technology.

UMC and ARM will provide an advanced process technology and comprehensive physical IP platform under this agreement, with the goal of supporting customers targeting a wide range of consumer applications such as smartphones, tablets, wireless and digital home services.

“UMC’s ‘United for Excellence’ approach includes unified collaboration with our IP suppliers to deliver high-value design support solutions to our foundry customer,” said S. C. Chien, vice president, IP and Design Support Division, UMC. “UMC’s 28nm dual process roadmap includes both poly SiON and high-K/metal gate-based technologies. 28HLP is the foundry industry’s most competitive Poly SiON 28nm technology in terms of power consumption, performance and area, with a robust design platform to help expedite our mobile and communication customers’ time-to-market. We are excited to broaden our collaboration with ARM to further strengthen our 28HLP platform with ARM’s highly popular POP IP core-hardening acceleration technology.”

The energy-efficient ARM Cortex-A7 processor has seen broad adoption in smartphones, tablets, DTV and other consumer products. The ARM POP IP for the Cortex-A7 processor is targeted for 1.2GHz on UMC’s 28HLP platform, and delivery began in December 2013.

UMC’s 28HLP process is the foundry’s enhanced 28nm Poly-SiON technology that provides an optimal balance of size, speed and power leakage. These process characteristics makes the process the optimal choice for a variety of applications that require low power consumption without compromising performance, including portable, wireless LAN, and both wired and handheld consumer products. The foundry is currently in pilot production for customer products on 28HLP, with volume production expected in early 2014.

“Through our close collaboration with UMC, ARM’s physical IP and POP IP enable optimal SoC implementation and streamline the design flow so that our mutual customers can achieve world-class implementation and get to market in the shortest time possible,” said Dipesh Patel, executive vice president and general manager, Physical Design Group, ARM. “Our standard cells, next-generation memory compilers and POP IP deliver the features, quality, and rigorous silicon validation that UMC’s customers demand, and help ARM deliver on our commitment to provide the best physical IP platforms at leading foundries.”

ARM Physical IP Platform

The ARM Artisan physical IP platform for UMC’s 28nm poly SiON process provides the building blocks to implement high-performance, low-power SoC designs. ARM’s silicon-proven IP platform offers a comprehensive set of memory compilers, standard cells and logic, and general-purpose interface products that meet the most demanding performance and power requirements for mobile communications and computing.

ARM’s standard cell libraries and memory compilers incorporate multi-channel and mixed Vt features to enable a wide performance and power spectrum which utilizes the performance and power range of UMC’s leading-edge poly SiON process. These features ensure that power budgets for performance-critical SoC designs can be met.

POP IP technology

POP IP technology comprises three key elements necessary for optimized ARM processor implementation. These include Artisan physical IP logic libraries and memory instances tuned for a given ARM core and process technology, comprehensive benchmarking reports pinpointing conditions and results ARM achieved for core implementation, and detailed POP implementation knowledge and methodologies that enable end customers to achieve successful implementation quickly with minimized risk. POP IP products are available from 40nm to 28nm with roadmap down to finFET process technology for a wide range of Cortex-A series CPU and Mali GPU products.

Semiconductor plastic packaging materials market to approach $21B by 2017

January 15, 2014

The market for semiconductor packaging materials, including thermal interface materials, is expected to maintain its $20 billion value through 2017, despite shifts away from the use of precious metals such as gold in wire bonding, according to a new study by SEMI and TechSearch International. Despite continued price pressure, organic substrates remain the largest segment of the market, worth an estimated $7.4 billion globally in 2013 growing to more than $8.7 billion by 2017. Most packaging material segments are encountering low revenue growth as end users seek lower cost solutions for packaging and downward pricing pressures are severe. In addition, the transition to copper and silver bonding wire has significantly reduced impact of gold metal pricing in wire bond packages.

The SEMI report, titled “Global Semiconductor Packaging Materials Outlook—2013/2014 Edition,” covers laminate substrates, flex circuit/tape substrates, leadframes, bonding wire, mold compounds, underfill materials, liquid encapsulants, die attach materials, solder balls, wafer level package dielectrics and thermal interface materials.

Several areas are experiencing stronger growth. The expansion of CSPs with laminate substrates is driven by explosive growth in mobile computing and communications devices such as smartphones and tablets. The same products are driving growth in wafer level packages (WLPs), which are in turn driving use of dielectric materials used for redistribution. The growth in flip chip adoption continues to expand the market for underfill materials. A number of key segments are seeing a consolidation of the supplier base, though new entrants in Asia are entering some segments.

Semiconductor Packaging Materials Segment	Estimate of 2013Global Market ($M)
Organic Substrates	$7,408
Leadframes	$3,342
Bonding Wire	$4,455
Mold Compounds	$1,394
Underfill Materials	$208
Liquid Encapsulants	$849
Die Attach Materials	$665
Solder Balls	$280
Wafer Level Package Dielectrics	$94
Thermal Interface Materials	$620

The findings in the report are based on more than 150 in-depth interviews conducted with packaging subcontractors, semiconductor manufacturers and materials suppliers. It includes previously unpublished data on revenue, unit shipments and market shares for each packaging material segment; a five-year forecast of revenue and units (2012-2017); supplier rankings (for key segments) and listing (including new players); and an analysis of regional market trends and size.

The report also identifies important technology and business trends affecting the packaging materials market, as well as opportunities for suppliers. Some of the key opportunities include:

Thinner substrates for packages in mobile products and leading-edge CSP substrates to handle fine bump pitch of ≤110 µm
Alternatives to the typical epoxy or acrylic resin for thermal interface materials, including filler technologies such as carbon nanotubes or new approaches using graphene

Softer Pd-coated copper wire for circuit under pad applications
Low moisture level sensitivity mold compounds and encapsulants for bare copper and silver alloy wire
Die attach film materials with thickness 10 µm and under
No-flow underfill materials
Continued trend of Pb-free solder balls for BGAs and CSPs, smaller diameter balls for WLP
Wafer-level package dielectrics with low temperature cure, lower dielectric constant, and lower cost

This information was derived from the SEMI Global Semiconductor Packaging Materials Outlook—2013-2014 Edition (www.semi.org/en/node/45446).

Xilinx and University of Florida honored with SEMI Award for advancements in interposers and CMOS fab process

January 15, 2014

SEMI today announced that two teams — from the University of Florida and Xilinx — are recipients of the 2013 SEMI Award for North America. The development team at Xilinx was recognized for their commercialization of the silicon interposer and the University of Florida team was recognized for developing a cornerstone of the modern era of computational modeling of CMOS fabrication process with the Florida Object-Oriented Process Simulator, FLOOPS. Liam Madden accepted the award on behalf of the Xilinx team, and Mark Law and Kevin Jones (University of Florida) accepted their awards during a banquet at the 2014 SEMI Industry Strategy Symposium (ISS) yesterday in Half Moon Bay, Calif.

The University of Florida team of Mark Law and Kevin Jones developed a cornerstone of the modern era of computational modeling of CMOS fabrication process with the Florida Object-Oriented Process Simulator (FLOOPS) which was introduced in 1990. FLOOPS has developed into a widely used, flexible code for multi-dimensional modeling for advanced IC fabrication processes. The proliferation of the use of FLOOPS as a vital component of process development activities enabled the continued advances in CMOS transistor performance throughout the last decade. The 3D nature of FLOOPS proved especially valuable as CMOS transistor design shifted from planar to multi-gate forms.

Law directed the FLOOPS code development and Jones led an extensive process characterization program, providing a detailed understanding of the relevant dopant-defect interactions needed to validate the specific models used in the FLOOPS code. The robust flexibility of FLOOPS serves as a valuable operational model for other efforts as IC development becomes increasingly dependent on efficient and accurate computational modeling capabilities in all areas of IC device fabrication and operation. There are now over 200 registered users of the FLOOPS code, including many SEMI member companies. In addition, the team works with graduates who enrich the global talent pool of many SEMI member companies.

The team at Xilinx — Trevor Bauer, Liam Madden, Kumar Nagarajan, Suresh Ramalingam, Steve Trimberger, and Steve Young — is recognized for commercialization of the silicon interposer which provides more than two orders of magnitude increase in die-to-die bandwidth per watt. This achievement effectively addressed both challenges of decreasing power and increasing bandwidth for advanced digital ICs. It also decreased latency to only 20 percent for standard input/output connections. Initially announced in 2011 and first shipped in 2012, the incorporation of a silicon interposer, also called 2.5D technology, delivers performance and power requirements dramatically improved compared to standard packaging.

When Xilinx used a silicon interposer in their packaging of advanced FPGA, it represented a major innovation in assembly and packaging technology and provides a learning curve for the many of the technologies that will be needed for high-volume production of 3D-stacked die. The product was realized by dividing their advanced FPGA into four die using 28nm technology and mounting the die side by side using microbumps on a silicon interposer. These die are connected to each other using a 65nm generation redistribution layer on the interposer and, in-turn, to the package substrate using through silicon vias (TSV) in the silicon interposer. The elements of redistribution layers on silicon, TSVs, and microbumps were already available but never combined to provide this high bandwidth, low power packaging solution.

“SEMI is proud to honor both Xilinx and the University of Florida with a SEMI Award. In addition to developing a key component of CMOS fabrication process with FLOOPS, the University of Florida has contributed valuable time and effort into workforce development for SEMI member companies for many years,” said Karen Savala, president, SEMI Americas. “Xilinx’s contribution is not only the design of the FPGA packaging using four die, but working with leaders in the foundry, assembly and packaging industries to develop a supply chain enabling volume production.”

“The FLOOPS technology enabled movement of some process development from the factory to the computer decreasing time and cost to implement new device designs,” said Bill Bottoms, chairman of the SEMI Award Advisory Committee. “The commercialization of the TSV based silicon interposer for high performance digital circuits and establishing the supply chain will also substantially accelerate the commercialization of full 3D integration.”

The SEMI Award was established in 1979 to recognize outstanding technical achievement and meritorious contribution in the areas of Semiconductor Materials, Wafer Fabrication, Assembly and Packaging, Process Control, Test and Inspection, Robotics and Automation, Quality Enhancement, and Process Integration.

The award is the highest honor conferred by SEMI. It is open to individuals or teams from industry or academia whose specific accomplishments have broad commercial impact and widespread technical significance for the entire semiconductor industry. Nominations are accepted from individuals of North American-based member companies of SEMI. For a list of past award recipients, visit www.semi.org/en/About/Awards/AwardNorthAmerica/P037176.

On January 13, SEMI also recognized two individuals — Rick Wallace, CEO and president of KLA-Tencor, and L.T. Guttadauro, executive director of the Fab Owners Association — who have provided outstanding support to the SEMI Foundation through donations, vision and volunteer efforts. The SEMI Foundation was created in 2001 to support education in the area of science, technology, engineering and math (STEM). A key program of the SEMI Foundation is High Tech U (HTU), a hands-on STEM career exploration program that is industry driven and supported through the generosity of SEMI member companies worldwide. For more information, visit www.semi.org/en/About/SEMIFoundation.

Economic recovery and pervasive computing to propel semiconductor manufacturing supply chain

January 14, 2014

Macroeconomic and microelectronic industry growth opportunities and innovation challenges underscored diverse perspectives from analysts, economists, technologists, semiconductor manufacturers and supply chain executives speaking at the SEMI Industry Strategy Symposium (ISS) that opened yesterday. The executive conference offers the year’s first strategic outlook for the global microelectronics manufacturing industry and offered encouraging forecasts buttressed by the silicon requirements for the pervasive computing era.

Opening keynoter Rick Wallace, president and CEO of KLA-Tencor, invoked Robert Frost prose on the “The Road Not Taken” to illustrate competing industry views about growth. Wallace contrasted consolidation-driven industry mergers to what he characterized as more agile productivity-oriented innovation growth. He rejected dual-source strategies as the optimal path for the industry and its supply chain and called for industry to make a more convincing appeal to young talent. In a provocative differentiation from competitors, Wallace questioned whether “too big to fail is also too big to innovate.”

Robert C. Fry, senior economist at Dupont, pointed to low but persistent global economic growth and highlighted positive data for global industrial production. He forecast global GDP growth of 3.1 percent in 2014 — up from 2.4 percent in 2013. Moreover, he commented on the increasing correlation between global GDP and semiconductor output, with high tech once again growing faster than the economy. Fry stated that global leading indexes are trending up, but not strongly or universally. Semiconductor shipments are finally setting new highs again and semi shipments have been trending up for more than a year.

Bill McClean, president of IC Insights, also pointed to better GDP growth trends, from 2.1 percent (2008-2012) to a forecast of 3.4 percent growth for 2014. Noting the trend toward mobility, he said that 2014 will be the first year that communications IC spending surpassed computing IC spending. He forecast 7 percent semiconductor market growth in 2014 to $350.7 billion and called for capital equipment spending of $62.3 billion, 9 percent higher than 2013 ($57.2 billion).

Bob Johnson, research VP at Gartner, stated that in the short term, growth will return to equipment markets in 2014 with annual growth between 16 and 21 percent. He expects quarterly weakness in the first half of 2014 after a strong fourth quarter in 2013. Longer term, he sees foundries battling IDMs for supremacy in mobility markets, technology shifts on the horizon with the advent of 3D NAND and EUV, and 450mm implementation beginning by end of 2017. Also, Johnson said that by 2017, the dominant semiconductor revenue opportunity in the “Internet of Things” will shift from infrastructure to the “Things,” and that the challenge will be in how to bring thousands of new products to market rapidly and cheaply.

Mark Thirsk, managing partner at Linx Consulting, discussed chemicals and materials needed for advanced semiconductor devices and forecast an improved outlook for 2014 with strong Q2 and Q3. A high upside potential remains in specialty materials for semiconductors, but significant R&D requirements remain a barrier. Materials demand grows faster than semiconductor unit growth due to process complexity — with Patterning, CVD and ALD, and CMP all driving materials demand growth. For the next 3-5 years, 3D packaging and TSV processing are key areas.

In the next SEMI Industry Strategy Symposium session, presenters spoke of both the challenges and opportunities inherent in Pervasive Computing. Nick Yu, senior VP at Qualcomm, discussed the unprecedented opportunity that the mobile era offers. Yu stated that what consumers want is a digital “6th sense,” basically the “augmentation of human ability.” The smartphone experience is also becoming the expectation in other device categories. Lama Nachman, principal engineer at Intel Labs, continued this thought with a presentation on “Context is Everything,” stating that Intel wants to fundamentally transform the relationship between humans and computers with “context” — for communication, introspection, meetings, health, and more. She said that the platform implications of context include: “always-on” sensing and computing, low-power sensors and I/O, effective workload partitioning, and security and privacy.

Dale Ford, VP and chief analyst at IHS, stated that the semiconductor market growth continues its cyclicality, with September 2012 beginning a new cycle that will peak in the second half of 2014. Ford said that capital expenditures declined by 9 percent in 2012 and an additional 3.7 percent in 2013, with Intel and Samsung transitioning existing capacity for use on next-generation technology. Pablo Temprano, senior director at Samsung Semiconductor, also stressed that a transformation is in progress. Discussing memory growth and investment in the mobile era, he said that Mobile is driving the Cloud (2013 Capex at $10 billion for just top 4: Google, Microsoft, Amazon, Facebook). The total memory Capex Consensus forecast is $16 billion for 2014.

Finally, Rod Morgan, VP at Micron Technology, said that an increasingly connected lifestyle is driving memory requirements with mobile multi-functional devices, with embedded sensors and significantly greater memory consumption. Fast growing memory in a highly interconnected world demand is split across multiple sub-segments. The $16.4 billion mobile memory segment is a portion of the overall memory market (RAM $31.0 billion; Flash $26.6 billion). Citing the reliability, technology and security requirements of these embedded mobile device microelectronics, Morgan called for greater supply chain collaboration to enable the network infrastructure be successful. He said, “The pace at which we enable the infrastructure will determine the speed of innovation.”

Conference speakers on Day 2 and Day 3 of ISS will discuss how these and other mega-trends are enablers for future growth in Pervasive Computing.

The SEMI Industry Strategy Symposium (ISS) examines global economic, technology, market, business and geo-political developments influencing the semiconductor processing industry along with their implications for your strategic business decisions. For more than 35 years, ISS has been the bellwether semiconductor conference for senior executives to acquire the latest trend data, technology highlights and industry perspective to support business decisions, customer strategies and the pursuit of greater profitability. For information on SEMI, visit: www.semi.org.

Imec celebrates 30 years

January 14, 2014

Nanotechnology research and development center imec, today announced the celebration of its 30th anniversary. Founded in 1984 as a non-profit organization, imec has grown to be a multi-disciplinary expertise center in the fields of semiconductor chips and systems, electronics for life sciences, body area networks, energy, photovoltaics, sustainable wireless communication, image sensors and vision systems, and flexible electronics and displays. Through innovations in nanoelectronics, imec has collaborated with numerous partners from universities, research institutes and top companies, creating solutions and developing emerging technology for a sustainable environment.

In the domain of semiconductor technologies, imec has enabled notable advancements in global semiconductor chip manufacturing in the three decades since its founding. At the forefront in advancing immersion lithography, EUV, double patterning imec has driven lithography as a key solution to overcome the challenges in scaling down features in silicon chips. In 2013, imec and ASML broadened their partnership with the launch of a Patterning Center. When complete, this Center will offer the global semiconductor ecosystem the most advanced patterning knowledge for sub-10nm technologies, crucial to addressing future scaling and infrastructure challenges. This Center will be extended through partnerships with other suppliers into a “Suppliers Hub,” to collaborate on the development of next generation process technology solutions.

Launched in 2003, imec’s research platform addressed the needs of the semiconductor value chain during the crucial transition from 200mm to 300mm silicon wafers as a manufacturing standard. The platform allows companies to collaborate on advanced process module and device research, targeting technology generations two to three nodes ahead of state-of-the-art IC production. Today, this initiative has evolved to a global collaboration platform with global industry leaders such as Intel, Samsung, TSMC, GLOBALFOUNDRIES, Micron, SK Hynix, Toshiba, SanDisk, Panasonic, Sony, Qualcomm, Altera, Fujitsu, nVidia, Xilinx, and others, driving semiconductor industry innovations.
Imec’s main achievements in semiconductor process technology research include:

1) Development of sub-22nm process technologies: From silicides to copper (Cu), to the introduction of low-k and high-k/metal gates, imec’s R&D has explored techniques to overcome interconnect metallization issues. In 2013, imec demonstrated the world’s first 3D compound semiconductor FinFET. Integrating III-V and silicon materials on the same 300mm silicon wafer through a unique silicon fin replacement process, imec demonstrated progress toward continued CMOS scaling at 7nm and below, enabling future hybrid CMOS-RF and CMOS-optoelectronics.

2) Contributions to manufacturability and circuit performance of advanced devices: Imec’s outstanding cleaning expertise has resulted in wafer cleaning solutions with high particle removal efficiency and minimal chemical use. The Rotagoni cleaning method, developed in 2001, solved the challenges faced by single-wafer wet cleaning. Also, imec pioneered research on 3D integrated circuits as a potential road to build more complex, more powerful and more cost-effective electronic systems, combining different types of functionalities on an ever smaller footprint. In 2008, imec demonstrated, for the first time ever, 3D integrated circuits.

Imec’s innovation in nanoelectronics has been a driver for developments in many other domains including healthcare, energy, photovoltaics, communications, and mobility, where imec has applied its semiconductor technology expertise. In 2013, imec’s life science research gained momentum by forging new R&D collaborations with Johns Hopkins University, Janssen Pharmaceutica, Pacific Biosciences, Panasonic, JSR, and others. Such collaborations will lead to breakthroughs in healthcare with the development of the next generation of “lab-on-chip” concepts, powerful supercomputers for life sciences research, and sensor array tools to advance neuroscience research.

“It’s our ambition to further position imec as a unique innovation hub for Europe and the world, where disruptive technology ideas are generated and come to fruition,” stated Luc Van den hove, president and chief executive officer at imec. “We welcome scientists, researchers and engineers from companies of various fields to collaborate with us as they advance and tune their innovations. Imec has proven to be the birthplace of new discoveries, and we confidently look forward to the next 30 years of innovation that will be the backbone of the solutions that will help make the world a better, more sustainable place.”

Imec, AlixPartners to develop model for lowering costs of advanced semiconductor tech

January 13, 2014

Nanoelectronics research center imec and AlixPartners, a global business advisory firm, announced today that the two companies are co-developing a cost modeling solution to assess the cost of advanced semiconductor technology options. The work is aimed at assisting the semiconductor industry in improving the operational intelligence around costs of future technology nodes.

This modeling will assess the cost of various patterning options for N10/N7 nodes, advanced packaging solutions and 3D NAND memory – all topics with big impacts on the price-tag of future consumer electronics. Imec and AlixPartners will be comparing the “should-be” cost of lithography-patterning from a system perspective and will assist in providing this information to industry suppliers and materials providers to better provision the development of extreme ultraviolet (EUV) lithography and/or 193inm multi-patterning lithography solutions. This model, designed to address advanced patterning costs, will also be crucial for fabless semiconductor companies (those that outsource their manufacturing) that are defining product strategy in close collaboration with foundries.

Economics today are challenging Moore’s law as the costs associated with node progression have been rising significantly. Below the 28nm node, the semiconductor industry is struggling to maintain its historical 30-percent cost savings per logic gate node over node. At the same time, consumer markets today are demanding cheaper smartphones and other devices, including for the Internet of Things (IoT).