Category Archives: Wafer Level Packaging

How to verify incident implant angles on medium current implants

October 30, 2013

BOBBY ISAACS and ANYA CORNELL, Texas Instruments, Dallas, Tex.

Results can depend on the properties of the wafers used, the conditions of the implant, the conditions of the anneal process, and even the measurement technique.

Semiconductor chip geometries continue to shrink, causing once unimportant parameters in the manufacturing process to become more critical. With the shrinkage in transistor size and requirements for improved precision in devices, ion implantation has become an increasingly more delicate and accurate operation. Implantation angle has become extremely important as transistors have decreased in size and voltage specifications. Adjustment and pocket implants, channeling implants, and high accuracy sidewall and HALO implants have become requirements for high performance, with little to no tolerance for incorrect implantation placement.

FIGURE 1. Illustration of wafer slicing angle and associated offset.

Older generations of ion implanters have been designed with only cursory regard to the extreme precision now required for implant placement. Because of this, semiconductor manufacturers must regularly monitor the implantation angle of these tools as part of normal production operations. In this monitoring, multiple potential issues exist that could cause a misinterpretation of the proper implantation angle, resulting in faulty tool calibration or production of out of tolerance product. This article will describe several variables to be considered when defining the angle of implant for a tool, and offer recommended conditions to achieve reliable and repeatable performance on two older implant tool sets.

The standard production test to determine if the angle of implant is accurate involves implanting 5 to 7 wafers tilted around a theoretical channeling angle, annealing the wafers to activate the implant, and charting the sheet resistance vs. implanted angle to find the channel. This procedure is commonly called a V-curve test. The as-measured channeling angle (found by identifying the minimum sheet resistance of the charted curve for the wafers, or the bottom of the “V”) should be equal to the theoretical channeling angle if the tool set-up is accurate. Unfortunately, the number of steps required by this procedure introduces errors that could lead to a false result. The properties of the wafers used, the conditions of the implant, the conditions of the anneal process, and even the measurement technique can all significantly affect the outcome.

Experimental
One of the most commonly overlooked variables that can introduce significant error into measurement of the angle of implant is the wafer which is used for the testing. One relevant silicon property of the wafers, the surface orientation angle offset (angle tolerance of the on-axis cut), has a significant effect. All wafers have a base surface orientation angle offset, as required by the process of slicing the wafers from the ingot (FIGURE 1).

This offset can directly translate into an offset in the V-curve measurement, depending on the angular rotation of the slice. It has been shown in previous work[3] that channeling is minimized at implant angles higher than 0.5°. In this work, the effect of the orientation angle offset on channeling was similarly studied. Implants were performed with 200mm, , N-type (phosphorus-doped) CZ wafers of resistivity 3-5 Ω-cm, surface orientation angle of 0.0+/-1°(on-axis ), Oi spec of <=32 ppma (ASTM-79), and LLS of <20 @0.20µm. The wafer type was chosen for use with Boron implant (P-type dopant) and the orientation was picked for its good channeling properties. Using the above specification, wafers were chosen at various extremes of the angle window (close to 0° and close to 1°) in order to characterize the effect of wafer angle variation. Other silicon properties shown in the spec above, such as surface defects, oxygen concentration, and resistivity are in the standard range for a typical test wafer. These parameters have a lesser effect on the implant angle measurement and were not explored in this study.

FIGURE 2(L). Comparison of Varian E500 V-curves generated using Thermawave vs TRS-100. FIGURE 3(R). Effect of wafer orientation angle offset on V-curve of Axcelis Optima MD.

The two implant tool types used were an Axcelis Optima MD implanter and a Varian E500 implanter. Implant conditions were chosen as follows based on experimentation and comparison of common processes among multiple manufacturing facilities utilizing several tool types: Boron11 at 100 keV energy, 1.0e14 ion/sq dose, 35° tilt, and 0° twist. Boron11 was chosen as the dopant for its small mass and channeling properties, as discussed in Downey, et.al.[2] Energy of 100 keV is high enough to prevent outgassing of the dopant during the anneal process, and 1.0e14 ion/sq dose was chosen to place the resultant resistance as measured on a standard Tencor RS-100 into a stable range for the measurement equipment.[1] For all tests, the ion beam was optimally tuned to minimize beam instability or non-linearity. The potential process variables influencing beam steering on the tool were not explored during this experimentation, but it should be commented that an improperly tuned ion beam will also significantly affect the result. A tilt angle of 35° was chosen as the optimal channeling condition. Although multiple potential channeling angles exist for [100] N-type silicon wafers, the angle of 35.26o has shown the most sensitive, clear channel for implant angle testing[1], and it is also recommended by Varian Semiconductor[4]. A twist angle of 0° was applied for best resolution of the channel in all but one of the tests, which utilized a rotation angle of 90° to characterize the effect of the wafer substrate angle offset.

The anneal process needed to be selected in such a way as to eliminate any variation or sensitivity due to temperature of anneal, anneal time, or even annealer tool type. An anneal temperature of 1060oC for 30 seconds was selected from earlier work[1] as the condition at which small temperature variations can be tolerated. Two types of annealer tools were used – an Axcelis Summit furnace annealer, and an AG Associates 8800 lamp annealer – to determine if the V-curve could be shifted through anneal by varying the tool type.

FIGURE 4. Effect of wafer orientation angle offset and wafer rotation on V-curve of Varian E500

Measurement of sheet resistance is well documented for ion implant processing. For this experimentation, Thermawave and Tencor RS-100 measurement tools were researched to identify possible areas of concern in the measurement of V-curve wafers. The advantage to Thermawave processing is the elimination of the need for anneal after implant, removing this source of potential variation. Also, a previous experiment with a different implant has shown that the Tencor RS-100 produces a sharper V-curve than the Thermawave (see sample V-curve in FIGURE 2). Therefore, the Tencor RS-100 tool was chosen for the present work. Testing on the Tencor RS-100 was performed using both 9-point and 49-point radial measurement patterns.

Results and discussion
By far the strongest effect was observed from the silicon wafer orientation angle offset. In particular, at angles above 0.5o, the effect was so pronounced that it shifted the V-curve. See below graph of two sets of wafers processed with identical implant and anneal conditions. The only difference was the orientation angle offset (0.04° vs 0.68°), as shown in FIGURE 3.

In an effort to further characterize the effect of a larger orientation angle offset of the wafers, testing was performed by rotating the wafers 90o during the implant to measure the change in the resultant V-curve. Using wafers with very small surface orientation offset angles (0.04o), the change in the measured V-curve could not be easily seen. However, using wafers with a surface orientation offset angle above 0.5o (0.68o), the change in the measured rotated V-curve became much more visible (FIGURE 4). Repeatability of the tests using high surface orientation angles was also noted to be inconsistent, with significant variance in results from test to test.

FIGURE 5. Effect of anneal tool and temperature on V-Curve of Varian E500.

Based on the results presented above, it is our recommendation that high-angle offset wafers (above 0.5°) should not be used for implant angle qualifications. It is also recommended that the surface orientation angle of the test wafers be scrutinized if the V-curve produced shows abnormal variance from the expected outcome. To reduce variability from other wafer parameters, we also recommend a tight resistivity specification (ex: 3-5 ohm-cm) for the silicon ingot, and advocate the use of wafers not only from the same ingot, but from the same area of the ingot, to ensure similar properties.

Minor effects were observed from other variables studied. An experiment comparing two anneal temperatures confirmed earlier findings1 of 1060C being the optimal temperature to produce a sharper V-curve (FIGURE 5). The type of anneal tool was also a factor. Although the process was matched as closely as possible through matching of the thermal budget, a difference could be seen between the annealer types (Fig. 5, left). Based on the clarity of the V-curve inflection on the lamp annealer, this tool was used as the benchmark for anneals during other experiments.

FIGURE 6. Effect of measurement map resolution on V-Curve of Axcelis Optima MD.

As for the Sheet Resistance measurement, very little to no effect was observed from varying the measurement pattern and number of measured points. A 9-point measurement showed the same accuracy as a 49-point measurement, making the additional points unnecessary (FIGURE 6).

Conclusion
As a result of this testing, multiple recommendations can be made to ensure accurate and repeatable measurement of the implant angle of a tool. These areas can result in significant variation of results if not accounted for during testing. The silicon quality of the wafers is one of the most overlooked variables in performance of implant angle measurement. The surface orientation angle offset can significantly change the measured implant angle, especially in ranges above 0.5° (from on-axis cut). Wafers with angle cut tolerance greater than 0.5° produce inconsistent results, severe enough to shift the sheet resistance values or even the entire V-curve, and are therefore not recommended for implant angle testing.

The parameters used in implantation also contribute significantly to the resolution and accuracy of a V-curve test. Although multiple potential channeling angles exist for [100] N-type silicon wafers, a 35° angle is recommended as the most sensitive, clear channel for implant angle testing.[1,4] The implanted species, energy, and dose all contribute to the stability and repeatability of the measurements. Once implanted, the anneal of the wafer must be tuned to a temperature and thermal budget that minimizes variation, as this will also cause slight changes in results. Finally, measurement techniques can change the outcome of a V-curve test through differences in the measurement tool used.

Once the angle of implant of a given tool is characterized, regular verification (qualification) is highly recommended, especially for events which involve components handling wafer orientation. To save on wafer cost, a test may be performed using 1 or 3 wafers once the baseline sheet resistance of the channeling angle is obtained, and charted through standard SPC techniques. If a failure is observed, escalation of the testing can then include a full 5 or 7 wafer V-curve test to determine if the angle of implant has shifted. Standard troubleshooting for common sheet resistance failure events should be included in disposition of a failure, since hardware issues in the form of leaks, contamination and other failure modes can influence the sheet resistance measurement obtained during angle testing.

Acknowledgments
The authors would like to thank TI silicon material technologist Thomas McKenna for valuable insight into starting material properties, as well as Jeff Bell of SUMCO-USA for providing substrate orientation angle data.

1. Rathmell, M.A. (2006). Implant Angle Monitoring – A Comparison of Channeling Features. Ion Implantation Technology Conference Proceedings, Marseille, France, June 11-16.

2. Downey, D.F., Arevalo, E.A., Eddy, R.J. (2000). The Significance of Controlling “Off-Axis” (from 1-0-0) Oriented Si Wafers During High Angle Implants. Ion Implantation Technology Conference Proceedings, Alpbach, Austria, September 17-22.

3.Guo, B.N., Variam, N., Jeong, U., Mehta, S., Posselt, M., & Lebedev, A. (2002). Experimental and Simulation Studies of the Channeling Phenomena for High Energy Implantation. Ion Implantation Technology Conference Proceedings, Taos, New Mexico, USA, September 22-27.

4.Canning, Stephen, (7/17/2006). BKM – System related Checks for Process Control, PSB2621A, Varian Semiconductor VSEA Product Support Bulletins, Pg. 6.

BOBBY ISAACS is an Ion Implant Fabrication Engineer for Texas Instruments’ DMOS5 manufacturing site in Dallas, TX ([email protected]). ANYA CORNELL is an Ion Implant and Silicon Processing Engineer for Texas Instruments’ MFAB manufacturing site in Portland, Maine.([email protected]).

MEMS devices for biomedical applications

October 28, 2013

By Dr. Ramesh Ramadoss, Formfactor, San Jose, CA

Micro-Electro-Mechanical Systems (MEMS) are a class of miniature devices and systems fabricated by micromachining processes. MEMS devices have critical dimensions in the range of 100 nm to 1000 µm (or 1 mm). MEMS technology is a precursor to the relatively more popular field of Nanotechnology, which refers to science, engineering and technology below 100 nm down to the atomic scale. Occasionally, MEMS devices with dimensions in the millimeter-range are referred to as meso-scale MEMS devices. Figure 1 shows relevant dimensional scale alongside biological matter.

Figure 1. Dimensional scale of MEMS and Nanotechnology. (Adapted from Nguyen et al. [1]).

Initially, MEMS technology was based on silicon using bulk micromachining and surface micromachining processes. Figure 2 shows an SEM image of a surface micromachining based polysilicon MEMS device, an electrostatic motor, which consists of twelve fixed stator electrodes and a rotor that spins around the pivot at its center. Gradually, other materials such as glass, ceramics and polymers have been adapted for MEMS. Especially, polymers are attractive for biomedical applications due to their bio-compatibility, low cost, and suitability for rapid prototyping. Other micromachining processes employed for fabrication of MEMS include dry plasma etching, electroplating, laser machining, micromilling, micromolding, stereolithography, and inkjet printing.

Figure 2. An SEM image of a MEMS electrostatic motor. (Source: https://www.mems-exchange.org/).

MEMS devices can actuate or sense on a micro-scale. MEMS devices can function individually or in combination with other devices to generate effects of meso- or macro- scale. Some advantages of MEMS devices include small size, light weight, low power consumption and high functionality compared to conventional devices. Further, MEMS technology offers cost reduction due to batch processing techniques similar to semiconductor Integrated Circuit (IC) manufacturing. Initially, MEMS technology emerged as an offshoot of the semiconductor industry and eventually established itself as a specialized field of study with a significant market share. According to Yole Développement, the MEMS industry market in 2012 was $11 billion, which is a 10 percent growth from the previous year.

MEMS applications

MEMS applications in various functional domains are shown in Figure 3. The term “functional domain” is used to refer to a domain in which the MEMS device performs a function such as sensing or actuation. In the early stages, MEMS proved to be a revolutionary technology in various fields of the physical domain such as Mechanical (e.g., Pressure sensors, Accelerometers, and Gyroscopes), Microfluidics (e.g., Inkjet nozzles), Acoustics (e.g., Microphone), RF MEMS (e.g., Switches and Resonators), and Optical MEMS (e.g., Micromirrors). Gradually, MEMS technology has demonstrated unique solutions and delivered innovative products in chemical, biological and medical domains as well. MEMS have penetrated into consumer electronics, home appliances, automotive industry, aerospace industry, biomedical industry, recreation and sports [2].

Figure 3. MEMS applications in various functional domains.

Typically, electronics are used to interface MEMS devices from its functional domain (i.e., Physical, Chemical, or Biological) to the electrical domain for signal transduction and/or recording. It should be pointed out that the term MEMS was originally coined to refer to miniature sensors and actuators operating between electrical and mechanical domains. Gradually, the term MEMS has evolved to encompass a wide variety of other microdevices fabricated by micromachining. For example, a micromachined electrochemical sensor is referred to as a MEMS device even though there is no functional role played by this device in the mechanical domain. Similarly, the term “BioMEMS” is used to refer to the science and technology of microdevices fabricated by micromachining for biological and medical applications. BioMEMS may or may not include any electrical or mechanical functions. BioMEMS application areas include biomedical transducers, microfluidics, medical implants, microsurgical tools, and tissue engineering. As shown in Figure 4, the global BioMEMS market is expected to almost triple in size, from $1.9 billion in 2012 to $6.6 billion in 2018 [3].

Figure 4. BioMEMS market forecast by Yole Développement [3]. (Source: http://www.yole.fr/).

BioMEMS applications

In this section, a few representative BioMEMS applications are presented. A survey of all products available on the market is beyond the scope of this article.

a) MEMS Pressure Sensors The first MEMS devices to be used in the biomedical industry were reusable blood pressure sensors in the 1980s. MEMS pressure sensors have the largest class of applications including disposable blood pressure, intraocular pressure (IOP), intracranial pressure (ICP), intrauterine pressure, and angioplasty. Some manufacturers of MEMS pressure sensors for biomedical applications include CardioMEMS, Freescale semiconductors, GE sensing, Measurement Specialties, Omron, Sensimed AG and Silicon Microstructures.

According to World Health Organization (WHO), Glaucoma is the second leading cause of blindness in the world after cataracts. MEMS implantable pressure sensors are used for continuous IOP monitoring in Glaucoma patients. A normal eye maintains a positive IOP in the range of 10-22 mmHg. Abnormal elevation (> 22 mmHg) and fluctuation of IOP are considered the main risk factors for glaucoma. Glaucoma, often without any pain or significant symptoms, can cause an irreversible and incurable damage to the optic nerve. This initially affects the peripheral vision and possibly leads to blindness without timely lifetime treatment. Therefore, it is critical to accurately monitor IOP and provide prompt treatments at the early stages of glaucoma development. Sensimed’s Triggerfish^TM implantable MEMS IOP sensor is shown in Figure 5. It consists of a disposable contact lens with a MEMS strain-gage pressure sensor element, an embedded loop antenna (golden rings), and an ASIC microprocessor (2mmx2mm chip). The MEMS sensor includes a circular active outer ring and passive strain gages to measure corneal curvature changes in response to IOP. The loop antenna in the lens receives power from the external monitoring system and sends information back to the system.

Figure 5. Sensimed’s TriggerfishTM implantable MEMS IOP sensor. (Source: http://www.sensimed.com/).

b) MEMS Inertial Sensors MEMS accelerometers are used in defibrillators and pacemakers. Some patients exhibit unusually fast or chaotic heart beats and thus are at a high risk of cardiac arrest or a heart attack. An implantable defibrillator restores a normal heart rhythm by providing electrical shocks to the heart during abnormal conditions. Some peoples’ hearts beat too slowly, and this may be related to the natural aging process or a genetic condition. A pacemaker maintains a proper heart beat by transmitting electrical impulses to the heart. Conventional pacemakers were fixed rate. Modern pacemakers employ MEMS accelerometers and are capable of adjusting heart rate in accordance with the patient’s physical activity. Medtronic is a leading manufacturer of MEMS based defibrillators and pacemakers. Figure 6 shows a MEMS accelerometer-based Medtronic’s SureScan^TM pacemaker and implantation of a pacemaker inside the body next to the heart. This pacemaker is designed to be compatible with magnetic resonance imaging (MRI).

Figure 6a.

MEMS inertial sensors (accelerometers and gyroscopes) were employed to develop one of the most unique wheelchairs, the iBOT^TM Mobility system, shown in Figure 7. A combination of multiple inertial sensors in this system enables the user to operate the wheelchair and lift to a standing height just balancing on two wheels. This allows the wheelchair user to interact with others face-to-face. The iBOT^TM system was developed by Dean Kamen in a partnership between DEKA and Johnson and Johnson’s Independence Technology division. Unfortunately, it is no longer available for sale from Independence Technology. Another related example is the Segway PT, a two-wheeled, self-balancing, battery-powered electric vehicle, also invented by Dean Kamen. It is produced by Segway Inc. of New Hampshire, USA.

Figure 7. Independence Technology’s iBOTTM mobility system. (source: http://www.ibotnow.com/).

c) MEMS Hearing-Aid Transducer A hearing-aid is an electroacoustic device used to receive, amplify and radiate sound into the ear. The goal of a hearing aid is to compensate for the hearing loss and thus make audio communication more intelligible for the user. In the US, hearing aids are considered medical devices and are regulated by the FDA. According to NIH, approximately 17 percent (36 million) of American adults report some degree of hearing loss. There is a strong relationship between age and reported hearing loss. Also, about 2 to 3 out of every 1,000 children in the United States are born deaf or hard-of-hearing.

According to statistics, 80% of those who could benefit from a hearing-aid chose not to use one. The reasons include reluctance to recognize hearing loss and social stigma associated with common misconceptions about wearing hearing aids. Thus, it is highly desirable to miniaturize hearing-aids without compromising performance. MEMS technology enables reduction of form factor, cost, and power consumption compared to conventional hearing-aid solutions. Figure 8 shows Analog Devices small size (7.3 mm³) MEMS microphone suitable for hearing-aid applications.

Figure 8. Analog Devices MEMS microphone for hearing-aid applications. (Source: http://www.analog.com/).

d) Microfluidics for diagnostics Microfluidics involve movement, mixing and control of small volumes (nanoliters) of fluids. A typical microfluidic system is comprised of needles, channels, valves, pumps, mixers, filters, sensors, reservoirs, and dispensers. Microfluidics enable bedside or at the point-of-care (POC) medical diagnosis. Especially, POC diagnosis is important in developing countries where access to centralized hospitals is limited and expensive. A POC diagnostic microfluidic system uses bodily fluids (saliva, blood, or urine samples) to perform sample preconditioning, sample fractionation, signal amplification, analyte detection, data analysis, and results display. In 1985, Unipath introduced the first POC microfluidic device, ClearBlue^TM, for pregnancy test from urine sample and is still available on the market. Recently, a comprehensive review article on the commercialization of microfluidic devices for POC diagnostics was published by Chin et al. [4].

One of the world’s most significant public health challenges, particularly in low- and middle- income countries, remains to be HIV/AIDS. According to WHO, 34 million people are living with HIV, and around 7 million eligible people are waiting for antiretroviral therapy. POC diagnosis is very crucial for the enumeration of absolute numbers of T-helper cells, commonly referred to as a CD4 count, for monitoring the course of immunosuppression caused by HIV and the initiation of antiretroviral therapy. The Alere Pima™ CD4 test system, shown in Figure 9, offers a revolutionary POC solution by providing an absolute CD4 count from either a fingerstick or a venous whole blood sample. The test requires approximately 25 microliters of whole blood sample to be loaded into the cartridge capillary. All test reagents are sealed within the disposable cartridge. On insertion of the cartridge into the analyzer, the test process automatically begins and displays direct CD4 measurement within 20 minutes.

Figure 9. Alere’s PimaTM point-of-care CD4 test system: a) disposable cartridge, and b) analyzer with a slot for cartridge insertion. (Source: http://alere-technologies.com/).

e) Microfluidics for drug delivery Microfluidics enable advanced drug delivery technologies such as triggered release, timed release and targeted delivery. Some applications include transdermal drug delivery (e.g., microneedle arrays and needle-less jet-based system), implantable drug delivery systems (e.g., drug-eluting stents and insulin pump), and drug delivery vehicles (e.g., micro- and nano– particles).

In the US, Diabetes mellitus has a mortality of 180,000 per year. It can be managed through proper diet and exercise, glucose-lowering oral medications and/or insulin therapy. One of the most notable insulin delivery systems for diabetes therapy, JewelPUMP^TM, is shown in Figure 10. This system was developed by Debiotech in collaboration with STMicroelectronics. The MEMS nanopump^TM mounted on a disposable skin patch provides continuous insulin through jet-based infusion delivery. The whole system weighs only 25 grams and holds up to 500 units of insulin and can be used for a 7 day period without any need for refill or replacement. The JewelPUMP^TM is directly programmed from a large display remote controller. It can be attached to the body using a disposable skin patch and can be detached when necessary, thereby offering more freedom to the patient.

Figure 10b. Attachment of the system to the body using a disposable skin patch (left) JewelPUMPTM (middle) and programmable remote controller (right) (Source: http://www.debiotech.com/).

f) Micromachined needles Micromachining enables fabrication of needles smaller than 300 µm, which is the limit of conventional machining methods. Typically, the length of the MEMS-based microneedles is less than 1 mm. Microneedles have been used for drug delivery, bio-signal recording electrodes, blood extraction, fluid sampling, cancer therapy, and microdialysis. Frequently, microneedles are integrated and used in conjunction with microfluidic systems. Solid and hollow microneedles have been fabricated out of silicon, glass, metals, and polymers using micromachining processes. Microneedles have been demonstrated with various body shapes (cylindrical, canonical, pyramid, candle, spike, spear, square, pentagonal, hexagonal, octagonal and rocket shape) and tip shapes (volcano, snake fang, cylindrical, canonical, micro-hypodermis and tapered). Figure 11 shows solid microneedles fabricated by reactive ion etching of silicon [5] and hollow microneedles fabricated by laser machining of a polymer.

Figure 11a. Micromachined needles: silicon based solid needles. (Source: Henry et al. [5]).

Figure 11a. Micromachined needles: polymer based hollow needles. (Source: http://www.lasermicromachining.com/).

g) Microsurgical tools Surgery is treatment of diseases or other ailments through manual and instrumental methods. In surgery, the majority of trauma to the patient is caused by the surgeon’s incisions to gain access to the surgical site. Minimally invasive surgical (MIS) procedure aims to provide diagnosis, monitoring, or treatment of diseases by performing operations with very small incisions or sometimes through natural orifices. Advantages of MIS over conventional open surgery includes less pain, minimal injury to tissues, minimal scarring, reduced recovery time, shorter hospital visits, faster return to normal activities and often lower cost to the patient. Common MIS procedures include angioplasty, catheterization, endoscopy, laparoscopy, and neurosurgery. MEMS based microsurgical tools have been identified as a key enabling technology for MIS [6]. A pair of silicon MEMS based microtweezers and metal MEMS based biopsy forceps are shown in Figure 12. It should be noted that some of these feasibility demonstrations have yet to be qualified for clinical applications.

Figure 12a. Micromachined surgical tools: a pair of silicon MEMS tweezers. (Source: http://www.memspi.com/).

Figure 12b. Micromachined surgical tools: a pair of metal MEMS biopsy forceps. (Source: http://www.microfabrica.com/).

Cardiovascular disease continues to be the leading cause of death in the United States. One of the common fatal cardiovascular conditions is narrowing of blood vessels due to accumulation of plaque that can lead to heart attack, stroke and other serious issues. Angioplasty is a procedure designed to restore normal blood flow through clogged or blocked arteries. A cardiac stent is inserted into a blood vessel via a catheter and then expanded to enlarge the vessel. There are two general types of stents: Metal stents and polymer stents. Metal stents are the conventional type. Two main types of polymer stents are resorbable and nonresorbable. The former type is attractive as it may be absorbed or dissolved inside the body. Figure 13 shows a stent fabricated on a bio-resorbable polymer by laser micromachining.

Figure 13. Micromachined resorbable polymer stent. (Source: http://resonetics.com/).

Other BioMEMS applications include tissue engineering [7] and microfluidics for cell biology, proteomics, and genomics [8]. A comprehensive coverage of various BioMEMS applications can be found in the recent books [9] and [10].

In the 21^st century, BioMEMS devices are anticipated to revolutionize the biomedical industry similar to that of semiconductor devices to the electronics industry in the last century. As evident from the market trend, there are tremendous opportunities for MEMS in the biomedical industry. However, FDA approval process necessary for certain applications can cause significant delays for new BioMEMS devices entering the market.

References

1. N.-T. Nguyen, S. A. M. Shaegh, N. Kashaninejad, and D.-T. Phan, “Design, fabrication and characterization of drug delivery systems based on lab-on-a-chip technology,” Advanced drug delivery reviews (2013).

2. M. Bourne, A Consumer’s Guide to MEMS & Nanotechnology, Bourne Research LLC, 1st edition, 2007.

3. BioMEMS 2013: Microsystem Device Market for Healthcare Applications, Yole Developpment, France, Feb. 2013.

4. C.D. Chin, V. Linder, and S. K. Sia. “Commercialization of microfluidic point-of-care diagnostic devices,” Lab on a Chip 12.12 (2012): 2118-2134.

5. S. Henry, D. V. Mc Allister, M. G. Allen and M. R. Prausnitz, “Microfabricated Microneedles: A Novel Approach to Transdermal Drug Delivery,” Journal of Pharmaceutical Sciences, 1998, 87, pp. 922-925.

6. K. Rebello, “Applications of MEMS in Surgery,” Proceedings of the IEEE, vol. 92, no. 1, Jan. 2004, pp. 43-55.

7. C. M. Puleo, H. C. Yeh, T. H. Wang, “Applications of MEMS technologies in tissue engineering,” Tissue Engineering, 13(12), 2007, pp. 2839-2854.

8. F. A. Gomez, Biological Applications of Microfluidics, Wiley-Interscience, 1st edition, 2008.

9. A. Folch, Introduction to BioMEMS, CRC Press, 1st edition, 2013.

10. Shekhar Bhansali (Editor), and Abhay Vasudev (Editor), MEMS for Biomedical Applications, Woodhead Publishing, 1st edition, 2012.

Dr. Ramesh Ramadoss is currently employed as a Senior Manager in the MicroProbe Product Group of FormFactor Inc., San Jose, California. He received his B.E. degree from Thiagarajar College of Engineering, Madurai, India in May 1998 and Ph.D. degree in Electrical Engineering from the University of Colorado at Boulder in May 2003. From June 2003 to Dec. 2007, he was employed as an Assistant Professor in the Department of Electrical and Computer Engineering at Auburn University, Auburn, Alabama. From Jan. 2008 to Mar. 2012, he was employed as a Program Manager, MEMS R&D, FormFactor Inc., Livermore, California. Since April 2012, he has been employed at MicroProbe, San Jose, CA (Acquired by FormFactor Inc.). He is the author or coauthor of 3 book chapters and 53 papers in the MEMS field (Google Scholar Citations: 476, h-index: 14, and i10-index: 17). He has conducted MEMS R&D projects for DARPA, NASA, US Army, AOARD, Sandia National Labs, Motorola Labs, Foster-Miller Inc. and FormFactor Inc.

EU project to industrialize world record high-density capacitors

October 23, 2013

CEA-Leti, Fraunhofer IPMS-CNT and three European companies — IPDiA, Picosun and SENTECH Instruments — have launched a project to industrialize 3D integrated capacitors with world-record density.

The two-year, EC-funded PICS project is designed to develop a disruptive technology through the development of innovative ALD materials and tools that results in a new world record for integrated capacitor densities (over 500nF/mm²) combined with higher breakdown voltages. It will strengthen the SME partners’ position in several markets, such as automotive, medical and lighting, by offering an even higher integration level and more miniaturization.

The fast development of applications based on smart and miniaturized sensors in aerospace, medical, lighting and automotive domains has increasingly linked requirements of electronic modules to higher integration levels and miniaturization (to increase the functionality combination and complexity within a single package). At the same time, reliability and robustness are required to ensure long operation and placement of the sensors as close as possible to the “hottest” areas for efficient monitoring.

For these applications, passive components are no longer commodities. Capacitors are indeed key components in electronic modules, and high-capacitance density is required to optimize – among other performance requirements – power-supply and high decoupling capabilities. Dramatically improved capacitance density also is required because of the smaller size of the package.

IPDiA has for many years developed an integrated capacitors technology that out performs current technologies (e.g. tantalum capacitors) in terms of stability in temperature, voltage, aging and reliability. Now, a technological solution is needed to achieve higher capacitance densities, reduce power consumption and improve reliability. The key enabling technology chosen to bridge this technological gap is atomic layer deposition (ALD) that allows an impressive quality of dielectric.

The PICS project consortium will address all related technological challenges and set up a cost-effective industrial solution. Picosun will develop ALD tools adapted to IPDiA’s 3D trench capacitors. SENTECH Instruments will provide a new solution to more accurately etch high-K dielectric materials. CEA-Leti and Fraunhofer IPMS-CNT will help the SMEs create innovative technological solutions to improve their competitiveness and gain market share. Finally, IPDiA will manage the industrialization of these processes.

About PICS The PICS project has received funding from the European Union’s Seventh Framework Program managed by REA-Research Executive Agency http://ec.europa.eu/rea (FP7/2007-2013) under grant agreement n° FP7-SME-2013-2-606149.

The PICS Project will last for two years and the consortium consists of three SMEs: IPDiA (France, coordinator), Picosun (Finland) and Sentech Instruments (Germany), and two leading research organizations: Fraunhofer IPMS-CNT (Germany) and CEA-Leti (France). Project objectives are to bring to mass production high density and high voltage capacitors based on ALD and etching development. Further information is available at www.fp7-pics.eu

About IPDiA IPDiA is a preferred supplier of high performance, high stability and high reliability silicon passive components to customers in the medical, automotive, communication, computer, industrial, and defense/aerospace markets. The company portfolio includes standard component devices such as silicon capacitors, RF filters, RF baluns, ESD protection devices as well as customized devices. IPDiA headquarters are located in Caen, France. The company operates design centers, sales and marketing offices and a manufacturing facility certified ISO 9001 / 14001 / 18001 / 13485 as well as ISO TS 16949 for the Automotive market. For further information, please visit www.ipdia.com

About Picosun Picosun is the world leading provider of ALD solutions for global industries. Picosun’s pioneering, unmatched expertise in ALD equipment design and manufacturing reaches back to the invention of the technology itself. Today, PICOSUN™ ALD systems are in daily production use in numerous prominent industries around the globe. Picosun is based in Finland, it has its subsidiaries in USA and Singapore, and world-wide sales and support network. For more information, visit www.picosun.com.

About SENTECH Instruments SENTECH Instruments GmbH develops, manufactures, and sells worldwide advanced quality instrumentation for Plasma Process Technology, Thin Film Measurement, and Photovoltaics. The medium-sized company founded in 1990 has grown fast over the last decades and has today 60 employees. SENTECH is located in Berlin, capital of Germany, and has moved to its own company building in 2010 in order to expand its production facilities.

SENTECH plasma etchers and deposition systems including ALD support leading-edge applications. They feature high flexibility, reliability, and low cost of ownership. SENTECH’s plasma products are developed and manufactured in-house and thus allow for customer-specific adaptations. More than 300 units have been sold to research facilities and industry for applications in nanotechnology, micro-optics, and optoelectronics. More information: www.sentech.de

About Fraunhofer IPMS-CNT Fraunhofer IPMS-CNT is a German research institute that develops advanced 300 mm semiconductor process solutions for Front-End and Back-End-of Line applications on state-of-the-art process- and analytical equipment. Research is focused on process development enabling 300 mm production, innovative materials and its integration into Systems (SoC/SiP) as well as nanopatterning through electron beam lithography. Fraunhofer is largest application-oriented research organization in Europe with 66 institutes and 22,000 employees. More information: www.cnt.fraunhofer.de

About CEA-Leti By creating innovation and transferring it to industry, Leti is the bridge between basic research and production of micro- and nanotechnologies that improve the lives of people around the world. Backed by its portfolio of 2,200 patents, Leti partners with large industrials, SMEs and startups to tailor advanced solutions that strengthen their competitive positions. It has launched more than 50 startups. Its 8,000m² of new-generation cleanroom space feature 200mm and 300mm wafer processing of micro and nano solutions for applications ranging from space to smart devices. Leti’s staff of more than 1,700 includes 200 assignees from partner companies. Leti is based in Grenoble, France, and has offices in Silicon Valley, Calif., and Tokyo. Visit www.leti.fr for more information.

Noel Technologies now providing 450mm wafer services

October 1, 2013

Noel Technologies, a Silicon Valley specialty foundry offering process development and substrate fabrication, has increased its capabilities by offering 450mm wafer services. Noel now jumps into the R&D transition to the larger wafer size as toolmakers and customers prepare for the 450mm generation.

The specialty foundry will first offer services for 450mm wafers in wet processes, etches, and wafer cleaning. Later this year, they will add photoresist spin coatings and in 2014 plans include adding LPCVD nitride & LPCVD undoped poly films.

“We wanted to be at the essential leading edge of the transition to the next wafer size,” commented Noel Technologies Founder and CTO Leon Pearce. “We will start by putting in the R&D foundation and offering several coating, cleaning and films processes. We realize this transition may take time and that the larger size offers challenges to manufacturers and foundries alike, including handling, cleanliness and creative process solutions. We’re dedicated to learning to process 450mm wafers along with our customers as they trend toward that transition.”

Noel Technologies, Inc. is a Silicon Valley based foundry focused on process development, optimization, quality and delivery. An ISO 9001 registered facility, Noel Technologies offers process development and fabrication now up to 450mm.

GE acquires Imbera

September 26, 2013

GE Healthcare Finland Oy, in partnership with GE Idea Works, announced today that it has completed the acquisition of Imbera Electronics Oy, a pioneering Finnish company that has spent over 10 years developing advanced embedded electronics packaging technology and manufacturing solutions. Financial terms of the transaction were not disclosed.

Embedded electronic packaging technologies can reduce the size and cost of components used in digital electronics by over 50 percent, enabling much higher integration for increasingly feature-rich consumer products such as smartphones and tablets. This embedded packaging is also used in advanced avionics, power distribution and a variety of other applications.

“We are extremely pleased to add the cutting edge technology and intellectual property of Imbera Electronics Oy as a component of GE’s existing electronics packaging portfolio,” said Larry Davis, vice president and microelectronics packaging program director at GE Idea Works.

Risto Tuominen, CEO and founder of Imbera Electronics Oy, commented that “Combining the high volume-focused and cost effective embedded technology from Imbera with the advanced thermal and power handling capability of GE creates the most compelling technology platform for advanced high density electronics packaging.”

This acquisition expands and extends GE’s position in advanced electronics and electronics packaging and creates one of the most extensive intellectual property and technology portfolios for embedded electronic packaging in the world, covering applications from low-power consumer products to high-power industrial electronics. GE plans to continue developing and licensing the Imbera Electronics Oy intellectual property and technology portfolio in combination with its established power overlay portfolio.

3D-IC: Two for one

September 25, 2013

Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. blogs about upcoming events related to 3D ICs.

This coming October there are two IEEE Conferences discussing 3D IC, both are within an easy drive from Silicon Valley.

The first one is the IEEE International Conference on 3D System Integration (3D IC), October 2-4, 2013 in San Francisco, and just following in the second week of October is the S3S Conference on October 7-10 in Monterey. The IEEE S3S Conference was enhanced this year to include the 3D IC track and accordingly got the new name S3S (SOI-3D-Subthreshold). It does indicate the growing importance and interest in 3D IC technology.

This year is special in that both of these conferences will contain presentations on the two aspects of 3D IC technologies. The first one is 3D IC by the use of Through -Silicon-Via which some call -“parallel” 3D and the second one is the monolithic 3D-IC which some call “sequential.”

This is very important progress for the second type of 3D IC technology. I clearly remember back in early 2010 attending another local IEEE 3D IC Conference: 3D Interconnect: Shaping Future Technology. An IBM technologist started his presentation titled “Through Silicon Via (TSV) for 3D integration” with an apology for the redundancy in his presentation title, stating that if it 3D integration it must be TSV!

Yes, we have made quite a lot of progress since then. This year one of the major semiconductor research organization – CEA Leti – has placed monolithic 3D on its near term road-map, and was followed shortly after by a Samsung announcement of mass production of monolithic 3D non volatile memories – 3D NAND.

We are now learning to accept that 3D IC has two sides, which in fact complement each other. In hoping not to over-simplify- I would say that main function of the TSV type of 3D ICs is to overcome the limitation of PCB interconnect as well being manifest by the well known Hybrid Memory Cube consortium, bridging the gap between DRAM memories being built by the memory vendors and the processors being build by the processor vendors. At the recent VLSI Conference Dr. Jack Sun, CTO of TSMC present the 1000x gap which is been open between on chip interconnect and the off chip interconnect. This clearly explain why TSMC is putting so much effort on TSV technology – see following figure:

System level interconnect gaps

On the other hand, monolithic 3D’s function is to enable the continuation of Moore’s Law and to overcome the escalating on-chip interconnect gap. Quoting Robert Gilmore, Qualcomm VP of Engineering, from his invited paper at the recent VLSI conference: “As performance mismatch between devices and interconnects increases, designs have become interconnect limited. Monolithic 3D (M3D) is an emerging integration technology that is poised to reduce the gap significantly between device and interconnect delays to extend the semiconductor roadmap beyond the 2D scaling trajectory predicted by Moore’s Law…” In IITC11 (IEEE Interconnect Conference 2011) Dr. Kim presented a detailed work on the effect of the TSV size for 3D IC of 4 layers vs. 2D. The result showed that for TSV of 0.1µm – which is the case in monolithic 3D – the 3D device wire length (power and performance) were equivalent of scaling by two process nodes! The work also showed that for TSV of 5.0µm – resulted with no improvement at all (today conventional TSV are striving to reach the 5.0µm size) – see the following chart:

Cross comparison of various 2D and 3D technologies. Dashed lines are wirelengths of 2D ICs. #dies: 4.

So as monolithic 3D is becoming an important part of the 3D IC space, we are most honored to have a role in these coming IEEE conferences. It will start on October 2nd in SF when we will present a Tutorial that is open for all conference attendees. In this Monolithic 3DIC Tutorial we plan to present more than 10 powerful advantages being opened up by the new dimension for integrated circuits. Some of those are well known and some probably were not presented before. These new capabilities that are about to open up would very important in various market and applications.

In the following S3S conference we are scheduled on October 8, to provide the 3D Plenary Talk for the 3D IC track of the S3S conference. The Plenary Talk will present three independent paths for monolithic 3D using the same materials, fab equipment and well established semiconductor processes for monolithic 3D IC. These three paths could be used independently or be mixed providing multiple options for tailoring differently by different entities.

Clearly 3D IC technologies are growing in importance and this coming October brings golden opportunities to get a ‘two for one’ and catch up and learn the latest and greatest in TSV and monolithic 3D technologies — looking forward to see you there.

Pitching for IC packages

September 13, 2013

By Sandra L. Winkler, New Venture Research

Itty bitty computers, smart phones, ipods, and more – these “must have” small electronic devices that Apple Computer and other companies have popularized, are forcing the hand of IC package designers to shrink the package to fit within these little hand-held gadgets.

Shrinking the package can be a challenge, as is routing these devices to a PCB. Creative package designs, such as stacked packages, SiPs, and interconnection methods of through silicon vias (TSVs) are all being put into play to achieve a small footprint, enhanced electrical performance, while consuming less battery power. Information on those technologies can be found in New Venture Research’s Advanced IC Packaging, Technologies, Materials, and Markets, 2012 Edition.

Package Pitch

Another method of reducing the form factor and reduced signal length is to reduce the package pitch, or the distance between the center of one second-level interconnect to the other as the interconnect to the printed circuit board (PCB). The package pitch of a device, combined with the I/O count, will determine the size of a package substrate or leadframe, the test socket size, and the footprint of the device on a PCB.

Reducing the pitch on an IC package often results in smaller solder balls on an array package, and will require that the electrical traces to the package on the PCB be closer together.

When a package pitch is altered, this will in turn have an effect on the PCB layout, the solder ball size where applicable and volume of solder paste, the test socket and DUT board, and all the parts used to make the package itself.

When combining the total packages together, the pitch of 0.4 mm has the largest growth of all the pitch sizes, while the 0.5-mm pitch comprises the largest single package pitch. Figure 1 displays the percentages of these pitches for the years 2012 versus 2017.

Figure 1 Total IC Package Pitch Forecast, 2012 vs. 2017
(Click to view full screen.)

The advantages of a hybrid scan test solution

September 12, 2013

By Ron Press, Mentor Graphics Corp

Scan testing is the standard practice for test of integrated circuits. The vast majority of IC production test is based on automatic test pattern generation (ATPG) using the scan logic. Scan ATPG is a mature technology with very predictable and high quality results. It also enables precise defect diagnosis to help yield analysis and improvement. With the growth in the size of ICs and smaller fabrication processes, embedded compression was added to the scan DFT logic, which reduces the growing time to apply tests by a couple of orders of magnitude. Today, embedded compression is commonplace.

However, some devices must be tested when there is little or no tester interface available. In these cases, built-in self-test (BIST) is necessary. Recently, the growth in ICs for safety critical applications, like automotive and medical, has boosted the demand for BIST. However, more and more ICs need both kinds of test. It turns out that embedded compression and logic BIST use similar types of logic, so it makes sense to save DFT logic area by sharing the compression and BIST logic in a hybrid test solution. The DFT and infrastructure of each technology can also provide advantages to the other technology. This kind of hybrid compression/BIST solution not only saves DFT area, but provides better test quality.

With the hybrid test approach, you have the option to provide embedded compression ATPG patterns from a tester or to have the patterns automatically applied and analyzed within the device logic BIST. You can insert hybrid logic in a top-down flow with a central controller and shared compression decompressor/LFSR and compaction/MISR logic in one or more blocks (Fig 1). You can also do it in a bottom-up flow, which lets you complete the logic insertion in each block, including wrapper isolation chains. The resulting blocks with hybrid test logic can be used in any IC and the logic BIST or embedded compression patterns for the block can be directly retargeted. This plug-n-play logic and pattern approach saves significant ATPG time in the top-level IC.

Embedded compression ATPG provides advantages to logic BIST in a hybrid solution. Because embedded compression ATPG has high quality production defect detection, the logic BIST might not be required to have as high a fault detection. Thus, fewer test points are necessary for random pattern resistive logic, which could be a significant logic BIST area savings. Another advantage that originally came from embedded compression is low power test. The hybrid test approach uses low power shift logic so that the toggle activity can be selected by the user in either ATPG or BIST.

Similarly, logic BIST in a hybrid approach provides advantages for embedded compression ATPG. X-bounding used by logic BIST to remove unknown states is necessary to produce a predictable signature in the MISR. It also makes the circuit much more testable for ATPG, especially if any test points are also added. As a result, the logic BIST infrastructure provided in the hybrid approach causes embedded compression ATPG to have higher coverage and fewer patterns. ATPG is normally the primary means of defect detection, but with logic BIST additional detection is possible due to the high number of detections of each fault (high multiple detection).

These are all compelling reasons why a hybrid test approach is attractive for any user implementing logic BIST. In fact, it is being adopted by automotive IC designers who need both autonomous test and very high-quality production ATPG patterns. What many don’t realize is that it also provides notable advantages for ATPG even if a hard logic BIST requirement doesn’t exist. With this approach, burn-in doesn’t need a tester to apply ATPG patterns since logic BIST could be used and overall ATPG compression and pattern count are improved.

Click to view full screen.

Figure 1. A hybrid test solution with compression (embedded deterministic test) and logic BIST sharing a majority of the decompressor/LFSR and compactor/MSIR logic.

Ron Press is the technical marketing manager of the Silicon Test Solutions products at Mentor Graphics. The 25-year veteran of the test and DFT (design-for-test) industry has presented seminars on DFT and test throughout the world. He has published dozens of papers in the field of test, is a member of the International Test Conference (ITC) Steering Committee, and is a Golden Core member of the IEEE Computer Society, and a Senior Member of IEEE. Press has patents on reduced-pin-count testing and glitch-free clock switching.

Fab equipment spending up 25% in 2014

September 9, 2013

The SEMI World Fab Forecast indicates that capital expenditure for semiconductor fab equipment spending will increase to US$ 39.8 billion in 2014, the highest on record. Semiconductor revenue has improved in 2013 compared to 2012 and early forecasts for 2014 project revenue growth averaging about eight percent. Semiconductor companies have adjusted their capital expenditure accordingly, and the SEMI report tracks over 200 projects, with details revealing that fab equipment spending is expected to decline by one percent in 2013 (to $31.8 billion), but increase by 25 percent in 2014, including new, used and internally manufactured in-house equipment.

Overall fab spending in the first half of 2013 was slow, especially for fab equipment spending. Fab equipment spending is stronger in the second half of 2013, with a 30 to 40 percent increase over the first half. The SEMI data shows a different outlook for fab construction projects, forecasting a 25 percent spending increase in 2013 to over $7 billion and then a drop of 16 percent in 2014 to about $5.9 billion. Fabs under construction this year will begin equipping next year which affects fab equipment spending.

While DRAM equipment spending dropped by 35 percent in 2011 and 25 percent in 2012, the SEMI data shows that DRAM fab equipment spending will increase by 17 percent in 2013 and at least 30 percent in 2014. An increase of about 2 to 3 percent for installed capacity for DRAM in 2014 is small but remarkable, given that the industry has not added any new DRAM capacity for years, and actually cutback capacity between 2011 and 2013.

The sector with largest growth rate for fab equipment spending in 2014 is expected to be Flash with a 40 to 45 percent increase (YoY). Over the last few years, capacity additions for the Flash sector also stagnated though technology investments. SEMI’s reports show detailed predictions for robust spending in DRAM and Flash by several large companies including Micron and Samsung. Overall fab equipment spending for Flash alone is expected to hit a record of almost $8 billion in 2014. After Flash and DRAM, MPU is expected to show the next largest growth in 2014, with fab equipment spending growing by over 40 percent (YoY). Intel is now preparing for 14nm, kicking off an MPU surge for 2014. The World Fab Forecast report gives insight into Intel’s preparations for 14nm.

Since the last fab database publication at the end May 2013, the SEMI worldwide dedicated analysis team has made 242 updates to 205 facilities (including Opto/LED fabs) in the database. The latest edition of the World Fab Forecast lists 1,147 facilities (including 247 Opto/LED facilities), with 66 facilities with various probabilities starting production this year and in the near future. SEMI added 14 new facilities and closed eight facilities.

The SEMI World Fab Forecast uses a bottom-up approach methodology, providing high-level summaries and graphs; and in-depth analyses of capital expenditures, capacities, technology and products by fab. Additionally, the database provides forecasts for the next 18 months by quarter. These tools are invaluable for understanding how the semiconductor manufacturing will look in 2013 and 2014, and learning more about capex for construction projects, fab equipping, technology levels, and products.

The SEMI Worldwide Semiconductor Equipment Market Subscription (WWSEMS) data tracks only new equipment for fabs and test and assembly and packaging houses. The SEMI World Fab Forecast and its related Fab Database reports track any equipment needed to ramp fabs, upgrade technology nodes, and expand or change wafer size, including new equipment, used equipment, or in-house equipment. Also check out the Opto/LED Fab Forecast. Learn more about the SEMI fab databases at: www.semi.org/MarketInfo/FabDatabase and www.youtube.com/user/SEMImktstats

Will 2014 be the next Golden Year?

September 5, 2013

By Christian Gregor Dieseldorff, SEMI Industry Research & Statistics Group (September 3, 2013)

Next year could be a golden year for the industry.

While GDP in 2013 is generally about the same as in 2012, it is expected to rise in 2014, to 3.8 percent from 3.1 percent. Semiconductor revenue has improved in 2013 compared to 2012 and early forecasts for 2014 project revenue growth averaging about 8 percent. Semiconductor companies have adjusted their capital expenditure accordingly, and the SEMI World Fab Forecast data now indicates fab equipment spending for 2014 will reach historic highs.

The SEMI World Fab Forecast report tracks over 200 projects, with details revealing that fab equipment spending declines by 1 percent in 2013, but will increase 25 percent in 2014, including new, used and in-house equipment.

Overall fab spending in the first half of 2013 was slower, especially for fab equipment spending. Excluding a large purchase by Globalfoundries for used 300mm equipment from Promos (US$ 30 billion) the decline in 2013 would have been -3.4 percent instead of -1 percent. Fab equipment spending is expected to be stronger in the second half of 2013, with a 30 to 40 percent increase over the first half, though the year will end with an overall equipment spending decrease of -1 percent.

SEMI’s data show a different outlook for fab construction projects, forecasting a 25 percent increase in 2013 and then a drop of 16 percent in 2014. Fabs being built this year will begin equipping next year which affects fab equipment spending.

Semiconductor device revenues did not grow in 2012 (dropped by about 2.7 percent), thus many companies slowed down capacity additions last year. With some improvement in the market, the SEMI data indicate that more capacity will be added in the 2^nd half of 2013 and even more in 2014, for overall capacity growth of about 4 percent.

Underdog DRAM surges to the front of the pack with 30 percent growth in 2014

Fab equipment spending for dedicated foundries remains strong in 2013 ($12B) and in 2014 ($13B) — a growth rate of 5 percent in 2014. Foundry equipment spending growth rates have been more controlled and not changing as dramatically as in other industry segments. In the years prior to the economic downturn, fab equipment spending for DRAM was the highest spending industry segment. Since 2011, however, the dedicated foundry sector replaced DRAM as the leading industry sector. See figure.

Fab equipment spending growth for DRAM turned negative in 2011 and 2012, as companies consolidated or diverted memory capacity into other products such as System LSI. DRAM equipment spending dropped by double digits in 2011 and 2012 (-35 percent and -25 percent respectively). SEMI’s data show that this will change dramatically, with DRAM fab equipment spending surging by 17 percent in 2013 and at least 30 percent in 2014. Driven by increased average selling prices (ASPs), up by about 40 percent in 2013, companies begin to see profit on DRAM and slowly invest in new capacity. See figure.

An increase of about 2 to 3 percent for installed capacity for DRAM in 2014 is small but remarkable, given that the industry has not added any new DRAM capacity for years, and actually decreased capacity between 2011 and 2013.

The sector with largest growth rate for fab equipment spending in 2014 is expected to be Flash with 40 percent to 45 percent (YoY). Over the last few years, with fears of oversupply and price collapse, capacity additions for the Flash sector also stagnated. Some companies even stopped or reduced adding new capacity (for example, Sandisk in 2012 and in 2013), leading to a tight supply, but a rebound in capacity is expected in the 2^nd half of 2013 and through 2014. SEMI’s reports show detailed predictions for robust spending in DRAM and Flash by several large companies.
For example, Micron, which officially acquired Elpida and Rexchip in July 2013, will dedicate almost half of its total 2014 capital expenditure to DRAM. After converting several fabs from memory to System LSI, rival Samsung is also expected to change tactics, spending less on System LSI and more on Memory in 2013 and 2014. Samsung’s Flash facility in China is expected to ramp to phase 1 by end of 2014. (The World Fab Forecast report reveals more detail on this and other surprising changes for S1 facilities and Line 16.) Overall fab equipment spending for Flash alone is expected to hit a record of almost $8B in 2014. The largest contributors are the Samsung fab in China and Line 16, Hynix M12 and M11, Flash Alliance fabs and Micron fabs.

MPU joins DRAM as the next underdog

After Flash and DRAM, MPU is expected to show the next largest growth in 2014, with fab equipment spending growing by over 40 percent (YoY). While MPU languished in 2011 and 2012, and even dipped into negative growth in 2013, with low utilization in some fabs, Intel is now preparing for 14nm, kicking off an MPU surge for 2014. The World Fab Forecast report gives insight into Intel’s preparations for 14nm.

Semiconductor companies appear to have mastered the art of fast adaptation to chip prices and business developments. With improving prices for DRAM, similar changes steer various sectors of the industry into unprecedented growth. With GDP predictions around 3 to 4 percent, revenue expectations in upper single digits, and historic numbers for equipment spending, next year could be a golden year for many semiconductor companies and equipment manufacturers.

SEMI World Fab Forecast Report

Since the last fab database publication at the end May 2013 SEMI’s worldwide dedicated analysis team has made 242 updates to 205 facilities (including Opto/LED fabs) in the database. The latest edition of the World Fab Forecast lists 1,147 facilities (including 247 Opto/LED facilities), with 66 facilities with various probabilities starting production this year and in the near future. We added 14 new facilities and closed 8 facilities.