Category Archives: Wafer Level Packaging

EV Group, a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today unveiled a new polymer via-filling process for 3D-IC/through-silicon-via (TSV) semiconductor packaging applications.  Available on the EVG100 series of resist processing systems, the new NanoFill process provides void-free via filling of very deep trenches and high-aspect ratio structures, and is suitable for all common polymeric dielectrics—offering a highly flexible, low-cost and production-ready via-fill platform for interposer development for 3D-integrated image sensors and other device types.

TSV interconnects are critical to the development of 3D-ICs since they enable through-chip communication between the vertically stacked device layers.  Currently, most TSVs employ a solid copper via structure.  However, the mismatch in coefficient thermal expansion (CTE) between the copper via and the surrounding silicon can create a high amount of stress on the via structure, which results in long-term reliability issues.  Replacing copper as the conducting material is not practical due to the general ease of use of the process as well as the fact that the tooling infrastructure for copper is already well established.  However, replacing the solid copper via with a partial copper-plated via that is filled with a polymeric dielectric has been demonstrated to reduce CTE mismatch and stress, thus minimizing reliability issues. EVG’s proprietary process and system enable simultaneous void-free via filling and dielectric redistribution layer (RDL) formation utilizing a field-proven process technology that is compatible with all standard polymeric materials.

“3D packaging represents a fundamental change in the semiconductor industry that paves the way for continued advances in device performance and cost reduction through ‘More than Moore’ approaches,” stated Markus Wimplinger, corporate technology development and IP director at EV Group.  “EV Group has made significant investments in our portfolio of wafer-level manufacturing solutions to add new products and capabilities, such as our NanoFill solution, to help our customers accelerate the commercialization of 3D-integrated devices.”

EVG’s new NanoFill via-filling solution provides numerous advantages over traditional spin coating and dry lamination techniques, including providing complete via filling for permanent passivation and planarization without forming voids or cavities.  The solution’s ability to use all common polymeric materials provides customers with a high degree of flexibility.  In addition, a sidewall passivation option is available that provides cost and throughput benefits for selected applications.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, announced today that Dow Corning has joined its network of top technology providers to support EVG’s LowTemp platform for room-temperature wafer bonding and debonding processes.  The addition of Dow Corning to EVG’s list of collaboration partners follows intensive co-development efforts between the two companies, including stringent testing of Dow Corning’s simple and innovative bi-layer temporary bonding technology.  EVG launched its new open LowTemp platform in July when it also announced the expansion of its global materials supply chain to accelerate the growth of high-end 3D-IC packaging.

“As a global leader in advanced silicone technology and expertise, Dow Corning is an important and much welcomed addition to our open temporary wafer bonding/debonding materials platform,” said Dr. Thorsten Matthias, business development director, EV Group.  “Their collaborative approach and exceptional materials expertise helped us to develop an innovative, cost-effective temporary bonding solution that now offers our customers expanded options for room-temperature bonding and debonding of active and carrier wafers using conventional manufacturing methods.”

EVG’s LowTemp temporary bonding/debonding platform (TB/DB) features three different room-temperature wafer-debonding processes – ultraviolet (UV) laser debonding, multilayer adhesive debonding and ZoneBOND technology – that have been qualified for the company’s high-volume production.

EVG said that Dow Corning’s bi-layer TB/DB silicone technology is a natural fit for its platform in that it comprises an adhesive and release layer that enables simple, room-temperature TB/DB, and delivers best-in-class performance with regard to low total thickness variation.  It also provides excellent chemical resistance and good thermal stability when exposed to temperatures reaching 300 degrees Celsius.

Through this non-exclusive agreement, the two companies plan to offer the advanced semiconductor packaging industry a cost-effective TB/DB solution to support high-volume production of 3D-IC packaging applications.

“This collaboration signifies another major milestone for Dow Corning, EVG and the semiconductor industry as a whole with regard to 3D IC and through silicon via development,” said Andrew Ho, global industry director, Advanced Semiconductor Materials at Dow Corning.  “In addition to signaling another important validation of Dow Corning’s simple, room-temperature temporary bonding/debonding technology, it enables further commercialization of EVG’s leading-edge open platform for volume manufacturing.  Equally important, this technology represents a major step forward toward the further integration of the 3D-IC packaging process for next-generation microelectronic applications.”

3D-IC integration promises to significantly improve the form factor, bandwidth and functionality of microelectronic devices by enabling once-horizontal chip structures to be fabricated into vertical architectures.  However, this revolutionary new technology first requires simple, cost-effective TB/DB solutions to adhere active device wafers to thicker carrier wafers.  This allows subsequent thinning of the active wafer down to 50 microns or less, and fabrication of through-silicon vias that enable vertical interchip communication.

Cascade Microtech, Inc. and imec today announced breakthroughs in probing stacked integrated circuits (3D-SICs), fueling an important growth engine for the semiconductor market. Through a Joint Development Agreement, Cascade Microtech partnered with imec to successfully probe 25µm-diameter micro-bumps on a wide I/O test wafer with its fully-automated CM300 probe solution utilizing an advanced version of Pyramid Probe technology. This achievement comes as part of imec’s 3D integration research program which includes other industry partners from the entire semiconductor value chain.

The 3D semiconductor market (including 3D-SIC, 2.5D interposer, and 3D WLCSP) is expected to represent nine percent of the total semiconductor value by 2017, according to Yole Développement. Logic 3D SoC/SiP (including interposer chips, APE, CPU, FPGA, wide I/O memory, etc.) will be the biggest industry using 3D platforms in the next few years. 3D applications will emerge in high-performance computing, and electronic markets such as nanotechnology and medical applications, which will benefit from the high-density integration that 3D technology offers.

The semiconductor industry is exploring new methods to increase the functionality of ICs at a smaller footprint, extending Moore’s Law. 3D-SICs offer a solution to the speed, power and density requirements demanded by future mobile electronics platforms. Through-silicon vias (TSV) used in 3D-SICs shorten interconnects between logic elements, thus reducing power while increasing performance. Within imec’s 3D integration research program, industry leaders are jointly developing design, manufacturing, and test solutions to bring this new technology to high-volume manufacturing.

Cascade Microtech’s CM300 flexible on-wafer measurement system was designed to deliver superior positioning accuracy and repeatable contact, offering a level of precision that supports both shrinking pad sizes and pitch roadmaps. The CM300 captures the true electrical performance of devices with high-performance capabilities that include low leakage and low noise. As a comprehensive probing solution employing the latest advances in Pyramid Probe technology, the CM300 has proven to meet the fine-pitch (40 µm area array), low-force (< 1gf/tip) advanced probing requirements of 3D-SICs.

“We are excited that our work with Cascade Microtech has resulted in such a breakthrough. I believe together we’ve achieved a first in the industry,” said Erik Jan Marinissen, Principal Scientist at imec in Leuven, Belgium. “We are able to hit 25 µm-diameter micro-bumps with a high level of accuracy due to the probe-to-pad alignment features of Cascade Microtech’s CM300. And advances in their Pyramid Probe technology have enabled us to probe micro-bumped wafers with 40/50 µm pitch according to the JEDEC Wide-I/O Mobile DRAM standard.”

“Cascade Microtech’s CM300 probe solution is designed to provide greater alignment accuracy to probe directly on small, fragile micro-bumps. In conjunction with a fine-pitch, low-force Pyramid Probe card, we have achieved consistent, accurate measurements on a wide I/O test wafer using a single-channel, wide I/O probe core with an array of 6 x 50 tips at 40/50 µm pitch, with the ability to shrink down to 20 µm pitches in the future,” said Steve Harris, Executive Vice President, Engineering, Cascade Microtech. “Together, imec and Cascade Microtech are enabling the ongoing future of CMOS technologies through this ground-breaking work. 3D integration will undoubtedly result in increased performance and yield while reducing overall costs.”

 

Toshiba Corporation and Amkor Technology, Inc. today announced that the companies have completed Amkor’s acquisition of Toshiba Electronics Malaysia Sdn. Bhd., Toshiba’s semiconductor packaging operation in Malaysia. The transaction also includes Toshiba’s license to Amkor of related intellectual property rights and a manufacturing services agreement between Toshiba and Amkor.

Under the manufacturing services agreement, Toshiba has agreed to purchase and TEM has agreed to supply packaging and test services for certain discrete semiconductor products and analog LSI products.

Established in 1973, TEM has steadily expanded the scale of its packaging operations, primarily of discrete and analog semiconductors. In recent years, its main product has been power semiconductors.

Toshiba positions power semiconductors as a driver of growth for its semiconductor business and seeks to maximize cost competitiveness across its front- and back-end operations. Transferring ownership of TEM to the Amkor group will allow TEM to take full advantage of Amkor’s large scale production and materials procurement capabilities and boost the overall efficiency of its power semiconductor operations.

Toshiba will continue to subcontract power semiconductor packaging and test to Amkor as an important source of key products. As it does so, Toshiba will shift its focus and resources to front-end wafer fabrication for power semiconductors by reinforcing production capabilities at Kaga Toshiba Electronics Corporation, Toshiba Group’s discrete semiconductor production facility in Ishikawa Prefecture, Japan.

Amkor expects the transaction to further strengthen its relationship with Toshiba and to grow its semiconductor packaging and testing business. Amkor plans to leverage the technology and scale of this new factory to attract leading power discrete customers to Amkor.

Semiconductor revenue worldwide will see improved growth this year of 6.9 percent and reaching $320 billion according to the mid-year 2013 update of the Semiconductor Applications Forecaster (SAF) from International Data Corporation (IDC). The SAF also forecasts that semiconductor revenues will grow 2.9 percent year over year in 2014 to $329 billion and log a compound annual growth rate (CAGR) of 4.2 percent from 2012-2017, reaching $366 billion in 2017.

Continued global macroeconomic uncertainty from a slowdown in China, Eurozone debt crisis and recession, Japan recession, and the U.S. sequester’s impact on corporate IT spending are factors that could affect global semiconductor demand this year. Mobile phones and tablets will drive a significant portion of the growth in the semiconductor market this year. The industry continued to see weakness in PC demand, but strong memory growth and higher average selling prices (ASPs) in DRAM and NAND will have a positive impact on the semiconductor market. For the first half of 2013, IDC believes semiconductor inventories decreased and have come into balance with demand, with growth to resume in the second half of the year.

"Semiconductors for smartphones will see healthy revenue growth as demand for increased speeds and additional features continue to drive high-end smartphone demand in developed countries and low-cost smartphones in developing countries. Lower cost smartphones in developing countries will make up an increasing portion of the mix and moderate future mobile wireless communication semiconductor growth. PC semiconductor demand will remain weak for 2013 as the market continues to be affected by the worldwide macroeconomic environment and the encroachment of tablets," said Nina Turner, Research Manager for semiconductors at IDC.

According to Abhi Dugar, research manager for semiconductors, embedded system solutions, and associated software in the cloud, mobile, and security infrastructure markets, "Communications infrastructure across enterprise, data centers, and service provider networks will experience a significant upgrade over the next five years to support the enormous growth in the amount of data and information that must be managed more efficiently, intelligently, and securely. This growth is being driven by continued adoption of rich media capable mobile devices, movement of increasingly virtualized server workloads within and between datacenters, and the emergence of new networking paradigms such as software defined networking (SDN) to support the new requirements."

Regionally, Japan will be the weakest region for 2013, but IDC forecasts an improvement over the contraction in 2012. Growth rates in all regions will improve for 2013 over 2012, as demand for smartphones and tablets remain strong and automotive electronics and semiconductors for the industrial market segment improve in 2013.

Rudolph Technologies, Inc., a provider of process characterization, photolithography equipment and software for the semiconductor, FPD, LED and solar industries, today released three new application-specific configurations of its industry-leading NSX 320 Automated Macro Defect Inspection System. The suite includes specially-designed configurations for wafer level packaging, 2.5D (interposer) and 3DICs using through-silicon via (TSV) as interconnects. The first NSX 320 Metrology System for wafer level packaging shipped in June to a major outsourced assembly and test (OSAT) facility in Asia.

“These new application-specific configurations of our established NSX 320 System are designed to address the emerging need for fast, precise three-dimensional (3D) measurements in the rapidly growing advanced packaging market sector,” said Rajiv Roy, vice president of business development and director of back-end marketing at Rudolph Technologies. “We have completed the integration of 3D measurement sensors, recently acquired from Tamar Technology, into the NSX System. Tamar’s sensor technology is well recognized and widely used, and integrating it into the NSX 320 System adds critical capability required for enabling advanced packaging applications such as copper pillar bumping and TSV.”

The NSX 320 wafer level packaging configuration is designed to measure film thickness (polymers, photoresist, glass), thin remaining silicon thickness (RST), surface topography, copper pillar height and solder bump height. The advanced wafer level packaging configuration adds measurements of the wafer profile (warp and bow), total stack thickness and thick/thin RST (bonded wafer before and after grind). The 3DIC configuration is capable of all the above measurements plus via depth, trench depth, bonded wafer TTV and adhesive layers.

Roy stated, “3DIC device volume is forecasted to grow to $38.4B by 2017, according to Yole Développement. Rudolph is positioned to address the growth requirements for wafer level packaging, as well as 2.5D and other advanced packaging technologies, with industry-proven metrology tools that offer superior speed and measurement solutions.”

Cree, Inc. announces that its 1200 V SiC MOSFETs are being incorporated into the latest advanced power supplies from Delta Elektronika BV. Delta Elektronika demonstrated a 21 percent decrease in overall power supply losses and a reduction in component count by up to 45 percent when compared to power supply products using traditional silicon technology.

Since 1959, Netherlands-based Delta Elektronika BV has produced power supplies for a range of industrial applications, such as specialized equipment used in factories, automation and industrial power conversion. Its power supplies typically provide high efficiency with low noise levels and are well known for their long operating lifespan.

“We are pleased to have Delta Elektronika BV as one of the volume adopters of our newest generation of SiC MOSFETs,” said Cengiz Balkas, general manager, Cree Power and RF. “Delta Elektronika BV has a half-century legacy of producing some of the most reliable, efficient and compact power supplies on the market. The industrial power supply market, which values efficiency, reliability and power density, is a key market for SiC MOSFET technology. Our new second-generation SiC MOSFET portfolio, which now includes a 160 m-Ohm MOSFET for the 5-10 kW market, is receiving strong market pull.”

Introduced in March 2013, Cree’s second-generation SiC MOSFETs have been well received throughout the power industry and are experiencing an increasing rate of adoption in several key applications, including a design-in at a major manufacturer’s next-generation, highly efficient PV inverters. With SiC, power supply manufacturers are able to reduce their component count to help improve reliability while maintaining or improving the power supply’s efficiency. Improving power density can also lead to reductions in the size, weight, volume and in some cases, even the cost of power supplies. SiC has been demonstrated to achieve more than twice the power density than typical silicon technology in standard power supply designs.

Alchimer, S.A. today announced a collaboration with the French research institute CEA-Leti to evaluate and implement Alchimer’s wet deposition processes for 300mm high-volume manufacturing. The project will evaluate Alchimer’s Electrografting (eG) and Chemicalgrafting (cG) processes for isolation, barrier and seed layers. When combined, Alchimer’s wet deposition processes have been demonstrated to achieve 20:1 aspect ratio through silicon vias (TSVs) due to their ability to coat conformally regardless of via topography, diameter or depth.

3D integration is moving towards a "via middle" approach where TSVs are formed after front-end processes, but prior to stacking.  Several applications are in the development phase, leading to constraints and different specifications for TSVs. Alchimer’s technology shows the potential to break through existing barriers to achieve high aspect ratio TSVs. This collaboration will evaluate the potential of its technology and its suitability for high-volume manufacturing.

"Current techniques, such as PECVD isolation and iPVD metallization, have performance limitations that are limiting achievable TSVs to 10:1 aspect ratios," said Bruno Morel, CEO of Alchimer. "Our 3D TSV products have unequivocally demonstrated their ability to deliver 20:1 aspect ratios at a significantly reduced cost as compared to current approaches. Now it is critical to validate the products’ full potential for 300mm high-volume manufacturing as well as to study their compatibility with the overall 3D integration process. Leti’s leading 3D expertise and world-class infrastructure will allow us to do that.

"Collaborating with Alchimer fits perfectly our strategy of delivering innovative solutions to industry," added Fabrice Geiger, head of Leti’s Silicon Technology Division. "Alchimer’s eG technology is a promising, cost-effective and breakthrough solution to address the challenges of future 3D TSV integration. Through this collaboration, Alchimer will have access to Leti’s expertise in the domain of 3D TSV integration and its world-class 300mm 3D platform capabilities."

eG is based on surface chemistry formulations and processes. It is applied to conductive and semiconductive surfaces and enables self-oriented growth of thin coatings of various materials, initiated by in-situ chemical reactions between specific precursor molecules and the surface. This process achieves a combination of conformality, step coverage and purity that cannot be matched by dry processes.

Developers have made major progress in the technology to manufacture printed or flexible circuits, sensors, batteries and displays. But frankly it’s been hard to build applications with much market pull without logic or memory as well, and those have been much harder to make. However, now printed memory and solutions for integrating conventional silicon die into flexible systems are edging into production, to potentially improve performance for a wider range of applications.  On the display side, easily integrated printed or flexible transparent conductive films for touch screens are starting to see some market traction.

Yole Développement projects the market for printed and flexible electronics will remain a modest ~$176 million this year, but will see 27 percent CAGR to ~$950 million by 2020, driven largely by printed layers integrated into large OLED displays.

Thinning patterned die makes flexible silicon on polymer

One interesting solution to add performance to flexible electronics could be an open platform for making flexible silicon die. American Semiconductor proposes drastically thinning conventional fabricated silicon wafers, and coating them with a combination of polymers. The resultant silicon-on-polymer approach protects and eases handling of the ultra-thin die, says CEO Doug Hackler, who will discuss the technology in a program on such hybrid solutions in the emerging market program series at SEMICON West in San Francisco in July. He reports user interest for large area distributed sensing systems that include ICs within structural composites in aircraft bodies to monitor stress, for bio sensors that conform to the body, for RF for wireless data transmission from printed sensors, and for drivers for flexible displays.

The company has qualified TowerJazz’s 130nm process to make SOI CMOS for its initial flexible standard microcontroller, and has worked with the foundry to establish design rules to make an open platform for other designers to create their own flexible chips. American Semiconductor thins these fabricated wafers by standard methods down to about ~40µm. “And then from <40µm it gets trickier and more proprietary,” says Hackler. But once these flexible silicon-on-polymer die are diced and released, they can be handled pretty much like standard chips. “The dicing and release are a little different, but once the die are on tape, then it appears feasible to do traditional pick and place,” he says, noting the company intends to use printed connections instead of bonding wire or solder bumps. After assembly on a flexible substrate, perhaps by a pick-and-place module integrated on a roll-to-roll printing tool, the devices would typically be laminated or overcoated for additional protection. The company plans to follow its flexible microcontroller with a standard analog/digital converter to take in sensor data, and an RF IC to send out the data. 

Innovative solutions for assembling silicon on flexible substrates move towards production

Packaging and assembling tiny thin die on flexible substrates remains a challenge, but multiple suppliers are making progress towards solutions that are starting to edge into commercial production. One approach particularly suitable for attaching sensors to the body is the spring-like stretchy wiring developed by MC10 for attaching thin silicon die to flexible substrates, for everything from wearable heart rate and fitness monitors to sensor membranes that can be implanted directly on organs inside the body. VP of R&D Kevin Dowling reports the company’s first commercial application is in a soft skullcap from Reebok that uses flexibly connected motion sensors to measure impacts to the head.

Tiny die size could also help with both cost and attachment of rigid die to conformable substrates, although handling and assembling them then becomes more of an issue. Terepac Corp. CTO Jayna Sheats notes that plenty of logic for simple controls could be very tiny and low cost — microprocessors with ~8000 transistors like the Z-80 generation currently used for many embedded control applications take up  <70µm2 of silicon with 90nm design rules, for millions on a wafer. But the die are too tiny to make the input/output connections or to handle with traditional pick and place for packaging and assembly. So Terepac proposes a photochemical assembly process instead, picking up an array of thinned and diced chips with a sticky printhead, positioning the chips over the substrate with a tool similar to a proximity aligner, and vaporizing the proprietary polymer/adhesive behind each selected chip with a combination of heat and UV so it falls into the desired position.  Chips can then be attached to the flexible substrate by conductive adhesive, electroplating, or printed connections. The company is working with equipment manufacturing partners including Rockwell International to construct manufacturing facilities for customers with products for the Internet of Things.

Jabil reports progress in low temperature attachment technologies for use with heat-sensitive flexible substrates. And Sandia National Lab reports it’s come up with a solution for the common researchers’ problem in this field of how to build prototypes of flexible systems when the necessary ultra thin chips only come in costly wafer-level volumes. Researchers there have figured out how to thin off-the-shelf single die for developing flexible systems.

Printed memory targets low-cost, high-volume applications          

Thin Film Electronics, meanwhile, is developing systems that use its simple, low cost printed memory. The company’s 20-bit memory can be produced in volume for under ~$0.05, targeted at applications like consumer packaging, with volumes of billions of units a year where roll-to-roll printing makes most sense, says Chandrasekhar Durisety, assistant director, North America, who will give an update on the company’s progress towards commercialization at the session. Thin Film is introducing a next generation of passive array memory, in 4×4 (16 bit), 5×5 (25 bit) or 6×6 (36-bit) options, a more conventional format with fewer pads at higher density for easier addressing than its initial 20-bit in-line architecture. 

The company is working with a global consumer product maker on using low-cost printed memory to make brand authentication cost effective for a wide range of lower-priced products. It’s also working with major flexible packaging supplier Bemis Company Inc. on sensor labels for food, healthcare and consumer products that can collect and wirelessly communicate sensor information at roughly the same low cost as current color-changing chemical indicators. The digital system under development — with Thin Film’s printed memory, an electrochromic display from Acreo, and printed logic technology from PARC — stores data when the temperature exceeds a certain range, to indicate more clearly than a color gradient can whether the product is usable or not. 

Thin Film aims to add electronics to applications that currently don’t use them, to add simple intelligence at prices far below those possible with silicon, such as low-cost brand authentication, temperature sensors on packaging, or simple electronics in toys.  “Silicon die could add significant capability to printed electronics. But with fabrication and assembly it would likely be more expensive than either silicon or printed electronics alone,” suggests Durisety.”  

Market starts to develop for printed/flexible ITO replacements

Another key potential market for printed/flexible electronics is next-generation transparent conductive film to replace brittle and expensive indium tin oxide in touch screens and displays, lighting, and photovoltaics.  Touch Display Research says the market for non-ITO transparent conductors will be about $206 million this year, and grow to some $4 billion by 2020.  “High demand for touchscreens for notebook and PC size displays has created a shortage of ITO touch sensors since the end of last year to drive more interest in these technologies, and the more flexible and potentially cheaper replacement technologies are getting more mature,” notes Jennifer Colegrove, president and analyst, who will speak at the FlexTech workshop on transparent conductors. She notes that Atmel, FUJIFILM, Unipixel and Cambrios are all in some phase of production.

There is, however, a confusing range of contending options for processes and materials for these films.  Applied Materials has interesting progress in its roll-to-roll deposition technology, while FUJIFILM Dimatix targets ink jet printing the materials, and NovaCentrix offers rapid thermal curing that doesn’t heat the substrate. Materials options range from nano metal wires at Cambrios Technology, Carestream and Sinovia, to embossed and metalized patterns from Unipixel, to carbon nanotubes at Brewer Science and graphene at Nanotech Biomachines. 

These and other speakers will talk about the challenges and solutions to move printed/flexible electronics into real markets at SEMICON West’s emerging technology programs, July 9-11 in San Francisco.

· Mon, July 8: Market Symposium, SF Marriott Marquis, Keynote: “New Directions in Flexible and Printed Electronics,” Dr. Ross Bringans, VP at PARC (1:00-5:30pm)

· Tue, July 9: Materials Growth Opportunities at Both Ends of the Spectrum (1:30-3:30pm)

· Wed, July 10: FlexTech Alliance Workshop: Emerging Materials and Processes for Transparent Conductors, SF Marriott Marquis (10:00am-5:00pm)

· Thur, July 11: Integrating Conventional Silicon in Flexible Electronics at the Extreme Electronics TechXPOT, South Hall (10:30am-1:10pm)

For more information, visit www.semiconwest.org/SessionsEvents/PlasticElectronics

Paula Doe is an analyst for advanced technologies for the global trade association SEMI.

Deca Technologies, an electronic interconnect solutions provider to the semiconductor industry, today announced it has named semiconductor industry veteran Chris Seams its new CEO. Seams brings more than 25 years expertise in managing operations, manufacturing, and sales and marketing. He has also been appointed to the company’s board of directors.

Seams joins Deca from Cypress Semiconductor Corporation, where he served as executive vice president of Sales and Marketing. He takes over for Tim Olson, who will now serve as Deca’s Chief Technology Officer and a member of its board of directors.

"Deca has two key value propositions: truly revolutionary wafer level packaging technology and industry-leading manufacturing efficiency," said T.J. Rodgers, chairman of Deca’s board of directors. "Chris brings a wealth of manufacturing experience to the position. He directly managed Cypress’ manufacturing for 14 years, building up its reputation for world-class efficiency. We are confident Chris will successfully build upon Deca’s strong inroads with top customers and lay the groundwork for the next level of the company’s growth."

"This is an exciting time to be joining Deca," said Seams. "The company is poised for rapid growth with the continued development of its offerings. I welcome the opportunity to lead Deca’s efforts to bring the potential of our wafer scale packaging capabilities to reality. In so doing, we will transform the way our customers­the leading semiconductor manufacturers around the world­approach wafer level packaging."

Seams joined Cypress in 1990, where other assignments included technical and operational management in manufacturing, development, and operations. Prior to joining Cypress, he worked in process development for Advanced Micro Devices and Philips Research Laboratories.

Seams is a senior member of IEEE, serves on the Engineering Advisory Council for Texas A&M University, and is on the board of directors of Tessera Technologies, Inc. Seams earned his bachelor’s degree in electrical engineering from Texas A&M University and his master’s degree in electrical and computer engineering from the University of Texas at Austin.