Category Archives: Wafer Level Packaging

Dr. Deepak Sekar is a senior principal engineer at Rambus Labs. He is the author or co-author of a book, two invited book chapters, 30 publications and 100 issued or pending patents (50 issued). He is a program committee chair at the International Interconnect Technology Conference, has received two best paper awards and serves on the committee of the International Technology Roadmap for Semiconductors. 

 In a keynote at the IEEE International Interconnect Technology Conference (IITC), Douglas Yu from TSMC talked about Moore’s Law scaling becoming increasingly difficult. The solution, he said, is to supplement VLSI with what he called a Wafer Level System Integration (WLSI) paradigm. Advances in wafer level packaging and through-silicon via technology could allow systems to scale and reduce the dependence on transistor/chip scaling, according to Yu.

Figure 1: Douglas Yu of TSMC talked about WLSI

Techniques for WLSI

Yu then described TSMC’s efforts towards WLSI.

Fan-in wafer level packages, where the package is the same size as the chip, were shown with sizes as high as 52 sq. mm (see Figure 2(a)). These could be used for low pin count applications such as WiFi.

Fan-out wafer level packages, where individual die are embedded in a molding compound, could be used for higher pin count applications, said Yu. These allow placing one or more die within the same package. TSMC has qualified large 225 sq. mm fan-out wafer level packages with tight 20um pitch redistribution layer wiring (see Figure 2(b)). These fan-out wafer level packages could be used for medium to high pin count applications and also for multi-chip packages.

Figure 2: (a) A 52 sq. mm fan-in wafer level package (b) A 225 sq. mm fan-out wafer level package where the die is surrounded by a molding compound

Yu then showed TSMC’s silicon interposer and 3D-TSV technology, called CoWoS (chip-on-wafer-on-substrate). Figure 3 depicts the process flow for CoWoS and finished systems built with the technology. It is just a matter of time before TSV technologies are prevalent, he said.

Figure 3: Chip-on-Wafer-on-Substrate technology used for interposer and 3D systems

How WLSI could allow system scaling despite the increasing challenges with Moore’s Law

Significant reductions in system size are possible with wafer level packaging, interposer and 3D stacking technologies, said Yu. This is particularly beneficial to mobile applications, which show the fastest growth in the industry today. This would allow packing more and more functionality within the same form factor, something Moore’s Law is finding increasingly difficult to do.

Smart system partitioning with WLSI can benefit electronic products quite a bit, said Yu. He gave an example of partitioning digital and analog components. With finFETs moving to production, designing analog components on the same chip as logic becomes difficult due to high parasitic capacitance. Analog blocks take up more and more percentage of the chip area since they don’t scale well. In this scenario, placing analog components on a separate chip and using fan-out wafer level packaging or TSV technology to build competitive systems is beneficial, he said. This allows systems to combine analog at a trailing edge node (eg. 65nm) and logic at a leading edge node (eg. 14nm). IP blocks can be reused, time-to-market can be accelerated with smart system partitioning and yields can be improved due to the lower die size, said Yu.

System performance per watt improvement, one of the benefits of Moore’s Law scaling, can also be obtained with WLSI, according to Yu. Memory (access) power is now a key component of total system power and this is increasing with every generation. By using fan-out wafer level packaging or TSV technology, memory power can be significantly reduced due to the shorter wire lengths (Figure 4).

Figure 4: WLSI could reduce logic to DRAM wire lengths from 20mm to 0.03mm.

During the question and answer session, Yu mentioned that all of the technologies he described used pure wafer-based processes, which allowed larger packages and lower cost. Audience members, when asked about the keynote, mentioned that cost will determine how prevalent the technologies presented in Yu’s talk will become. 3D chip technologies are still considered a few years away from mass adoption.

The International Interconnect Technology Conference, held in Kyoto this year, is IEEE’s flagship conference in the interconnect field.

Advanced packaging technology is undergoing dramatic changes as the smart phones and new sensor technologies demand continued improvements in form and function.  To address these massive changes, SEMICON West will feature a number of programs on new packaging technologies and processes with speakers from leading chip makers, equipment manufacturers, and material suppliers.

According to IDC, forecasts semiconductor revenues will log a compound annual growth rate (CAGR) of 4.1 percent from 2011-2016, but revenues for 4G phones will experience annual growth over 100 percent for the same period. NanoMarkets estimates that the global market for “Internet of Things” sensors will reach $1.6 billion this year and grow to a value of $17.6 billion by the end of the decade as sensors become increasingly connected to the Internet directly or through hubs.  Both trends will significantly impact semiconductor and microelectronics packaging.  Demand for equipment and related tools in the 3D-IC and wafer-level packaging area alone is forecasted to grow from approximately $370 million in 2010 to over $2.5 billion by 2016, according to Yole Developpment.

To address these changes, SEMICON West 2013 (register at www.semiconwest.org/registration), held on July 9-11 in San Francisco, will feature a number of programs on new packaging applications, requirements, technologies, and products, including:

  • Generation Mobile:  Enabled by IC Packaging Technologies — Speakers from ASE, UBM Tech Insights, Amkor Technology, SK Hynix, and Universal Scientific Industrial will present on the latest advances in wafer-level packaging, new materials, and multi-die integration, including new System-in-Package (SiP) and Package-on-Package (PoP) methods. Location: Moscone Center (North Hall), TechXPOT North, Tuesday, July 9, 10:30am-12:30pm.
  • “THIN IS IN": Thin Chip & Packaging Technologies as Enablers for Innovations in the Mobility Era — IEEE/CPMT will hold a technical workshop on the overall trend of maximum functional integration in the smallest and thinnest package with lowest packaging costs with speakers from Intel, Cisco, ASE, Micron, SK Hynix, Nanium, Kyocera and more. Location: San Francisco Marriott Marquis, Tuesday, July 9, 1:30-4:45pm.
  • Advancing 2.5D and 3D Packaging through Value Engineering — Speakers from Altera, Amkor, ASE, ASET, KPMG, UMC, STATS ChipPAC and more will take a critical look at 2.5D implementations and the current outlook for 3D packages, including tools and technologies for heterogeneous stacks. Location: Moscone Center (North Hall), TechXPOT North, Wednesday, July 10, 1:00-3:30pm.
  • MEMS & Sensor Packaging for the Internet of Things— This session will feature speakers from all parts of the ecosystem to address how future visions of a pervasive interconnected world will be realized through the heterogeneous integration of MEMS and ICs.  The program will feature keynote speaker Janusz Bryzek from Fairchild Semiconductor, and speakers from VTT Research, Fraunhofer IZM, Robert Bosche, EV Group, Dai Nippon Printing, and more. Location: Moscone Center (North Hall), TechXPOT North, Thursday, July 11, 10:30am-1:00pm.

In addition to the packaging programs, SEMICON West 2013 will also feature over 560 exhibitors with the latest innovation on microelectronics manufacturing, including over 150 exhibitors with equipment and technology solutions for advanced packaging.  Other programs and exhibitors at West will address lithography, advanced materials and processes, silicon photonics, test, LED and MEMS manufacturing, and other subjects.  For more information on SEMICON West and to register, visit www.semiconwest.org

Fab equipment spending will grow two percent year-over-year  (US$ 32.5 billion) for 2013 and about 23 to 27 percent in 2014 ($41 billion) according to the May edition of the SEMI World Fab Forecast. Fab construction spending, which can be a strong indicator for future equipment spending, is expected to grow 6.5 percent ($6.6 billion) in 2013, followed by a decline of 18 percent ($5.4 billion) in 2014. The new World Fab Forecast report covers fab information on over 1,140 facilities, including such details as capacities, technology nodes, product types, and spending for construction and equipment for any cleanroom wafer facility by quarter.

Fab equipment spending for the second half of 2013 is expected to be much stronger with a 32 percent growth rate or $18.5 billion compared to the first half of 2013. The equipment spending increase in the second half is attributed to growing semiconductor demand and improving average selling price for chips. 2014 is expected to have about 23 to 27 percent growth year-over-year (YoY) to reach about $41 billion, which would be an all-time record.

Looking at product types, the largest amounts of spending on fab equipment in 2013 will come from the foundry sector, which increases by about 21 percent. This is driven mainly by capex increases by TSMC. The memory sector is expected to have an increase of only one percent — after a 35 percent decline in the previous year. The MPU sector is expected to grow by about five percent. A double-digit increase in the Analog sector in 2013 will still translate into low absolute dollar amounts, compared to the other sectors.  

 

Construction spending is a good indicator for more equipment spending.  Fab construction spending in 2013 is expected to be almost 15 percent growth YoY ($6.6 billion) with 38 known construction projects. Top spenders for fab construction in 2013 are TSMC and Samsung, who plan to spend between $1.5 and $2 billion each, followed by Intel, Globalfoundries and UMC. The SEMI World Fab Forecast report reveals more detail.

2014 shows a decline of about 18 percent ($5.4 billion) in construction spending with only 21 construction projects expected to be on-going. These construction projects include large fabs; some are 450mm-ready. 

Since the last fab database publication at the end February 2013 SEMI’s worldwide dedicated analysis team has made 389 updates to 324 facilities (including Opto/LED fabs) in the database. The latest edition of the World Fab Forecast lists 1,144 facilities (including 310 Opto/LED facilities), with 61 facilities with various probabilities starting production this year and in the near future. Seventeen new facilities were added and 8 facilities were closed.

The SEMI World Fab Forecast uses a bottom-up approach methodology, providing high-level summaries and graphs; and in-depth analyses of capital expenditures, capacities, technology and products by fab. Additionally, the database provides forecasts for the next 18 months by quarter.

The semiconductor industry’s march toward broader 3D IC integration marked an important milestone this week at the 2013 Electronic Components & Technology Conference (ECTC), with the report of an advanced new temporary bonding solution for 3D Through-Silicone-Via (TSV) semiconductor packaging. The breakthrough was unveiled during ECTC’s 3D Materials and Processing session, when Ranjith John, materials development and integration engineer at Dow Corning, presented a paper co-authored by Dow Corning, a developer of silicones, silicon-based technology and innovation, and SÜSS MicroTec, a supplier of semiconductor processing equipment.

The paper, titled Low Cost, Room Temperature Debondable Spin on Temporary Bonding Solution:  A Key Enabler for 2.5D/3D IC Packaging, details the development of a bi-layer spin-on temporary bonding solution that eliminates the need for specialized equipment for wafer pretreatment to enable bonding or wafer post-treatment for debonding. Thus, it greatly increases the throughput of the temporary bonding/debonding process to help lower the total cost of ownership. 

“This advance underscores why Dow Corning values collaborative innovation. Combining our advanced silicone expertise with SÜSS MicroTec’s knowledgeable leadership in processing equipment, we were able to develop a temporary bonding solution that met all critical performance criteria for TSV fabrication processes. Importantly, the spin coat-bond-debond process we detailed in our co-authored paper takes less than 15 minutes, with room for further improvement,” said John. “Based on these results, we are confident that this technology contributes an important step toward high-volume manufacturing of 2.5D and 3D IC stacking.”

Both 2.5D and 3D IC integration offer significant potential for reducing the form factor of microelectronic devices targeting next-generation communication devices, while improving their electrical and thermal performance. Cost-effective temporary bonding solutions are a key enabler for this advanced technology by bonding today’s ultra-thin active device wafers to thicker carrier wafers for subsequent thinning and TSV formation. However, in order to be competitive, candidate temporary bonding solutions must deliver a uniformly thick adhesive coat, and be able to withstand the mechanical, thermal and chemical processes of TSV fabrication. In addition, they must subsequently debond the active and carrier wafers without damaging the high-value fabricated devices.

Through their collaboration, Dow Corning and SÜSS MicroTec were able to develop a temporary bonding solution that met all of these application requirements. Comprising an adhesive and release layer, Dow Corning’s silicon-based material is optimized for simple processing with a bi-layer spin coating and bonding process. Combined with SÜSS MicroTec equipment, the total solution offers the benefits of simple bonding using standard manufacturing methods. In their co-published paper, the collaborators report a solution exhibiting a total thickness variation of less than 2 µm for spin-coated films on either 200- or 300-mm wafers. The bonding material exhibited strong chemical stability when exposed to phosphoric acid, nitric acid, organic solvents and other chemicals familiar to TSV fabrication. In addition, the bonding solution and paired wafers showed good thermal stability when exposed to the 300°C temperatures common to the TSV process.

Dow Corning builds on a long history of silicon-based innovation and collaboration in semiconductor packaging. From die encapsulants for stress relief, to adhesives for sealing and bonding, to thermal interface materials for performance and reliability, Dow Corning’s well-established global infrastructure ensures reliable supply, quality and support, no matter where you are in the world.

OMRON Corporation today announced that they have finished development work on the world’s first infrared sensor manufactured with wafer-level vacuum packaging technology to create a 16×16 element MEMS non-contact infrared thermal sensor capable of highly precise 90-degree area detection. OMRON says it will ship test samples beginning in October 2013.

In recent years, the demand for human presence sensors has been growing in tandem with the demand for energy-efficient "smart home" and "smart office" environments, in which lighting, heating, etc. is automatically controlled according to where people are positioned. Since conventional pyroelectric human presence sensors (motion sensors) are only able to detect people when they are in motion, they are not as suitable for detecting the number of people in a certain space or their relative positions as Omron’s new thermal sensor.

MEMS non-contact thermal sensors measure temperature by converting infrared energy radiated from target objects into heat with MEMS thermopiles and then measuring the thermoelectromotive force resulting from temperature differences that occur across the contact points of two different types of metal. However, up till now it has not been possible to create large temperature differences across the metal contact points because much of the heat generated by the thermopiles dissipates into the surrounding air, meaning that the resulting thermoelectromotive force is reduced thereby limiting sensitivity. Omron believes they solved this heat dissipation problem by vacuum sealing the thermopiles inside the chip – the first time this has been achieved. The reduction in heat dissipation leads to a greater temperature difference across the metal contacts thereby increasing sensitivity.

How non-contact thermal sensors work

MEMS thermal sensor wafer level packaging

Thermal sensors utilize the Seebeck effect in which thermoelectric force is generated due to the temperature difference at the contact points between two different kinds of metal. Thermopiles are created by serially connecting thermocouples consisting of N+ poly Si, P+ poly Si, and Al. By creating hot junctions on highly heat-resistant dielectric membranes, and cold junctions on highly heat-conductive silicon, it is possible to achieve high-energy conversion efficiency. Sealing thermopiles in a vacuum prevents the heat they create from dissipating into the air thereby increasing sensitivity. 

Omron will now also work on commercializing stand-alone human presence sensor modules by combining non-contact thermal sensors with algorithms that can accurately distinguish the number of people and their positions within a detected space.

Model versions of Omron’s new human presence sensors will be displayed at the "Nanomicro Biz" Exhibition at Tokyo Big Sight on July 3, 4, and 5.

The development of this new sensor was the result of research carried out in collaboration with Japan’s New Energy and Industrial Technology Development Organization.

 

Mentor Graphics Corp. today announced significant achievements in its continued collaboration with TSMC on 20nm physical verification kit optimizations. This joint effort has reduced Calibre nmDRC 20nm signoff runtimes by at least a factor of 3X and memory requirements by 60 percent compared to initial design kits released last year. In addition, Calibre PERC N20 design kits are now available to TSMC customers as part of the companies’ ongoing collaboration for IC reliability improvement. The collaboration will continue as mutual customer’s ramp their releases of N20 production designs, with the goal of maintaining rapid turnaround on full-chip signoff runs for the largest SoC designs in the industry.

The Calibre PERC kit for N20 includes new checks for latch-up prevention and IO-ESD protection, and a number of multiple power domain checks, which represent a significant step forward in automating procedures that previously had to be done manually. Moreover, by using both the Calibre PERC and Calibre nmDRC kits, customers are able to quickly identify and correct voltage-aware DRC violations, which is critical for today’s multi-voltage advanced process designs.

Other ongoing collaboration between TSMC and Mentor is focusing on optimizing the Calibre DFM product family, which incorporates TSMC’s unified DFM (UDFM) engine. Improvements are expected to result in runtime reduction in TSMC’s latest DDK release, and customers who use any DFM tools compliant with TSMC UDFM engine will benefit.

“Our work with TSMC demonstrates the advantage of close collaboration among the foundry, EDA vendor and lead customers to bring new process nodes to market more efficiently,” said Michael Buehler-Garcia, senior director of Calibre Design Solutions Marketing at Mentor Graphics. “Our efforts don’t stop when tools are qualified. We continue to work with TSMC to optimize the design kits as the process matures, resulting in overall shorter design cycle times.”

“The close working relationship between TSMC and Mentor has existed for many years and continues to result in new solutions and rapid performance optimization,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “With N20 we have taken our efforts to the next level to deliver optimized Calibre DRC decks, which include multi-patterning, on an even faster timetable than for prior nodes. Building on this success we have already extended performance improvements to the first-release Calibre N16 decks.”

TSMC and Mentor will speak about their recent optimization efforts in a session titled “Best Practices for Verification at Advanced 20nm Process Nodes” at the Design Automation Conference (DAC), Austin, Texas, June 2-5.

Signetics Corporation today announced that it has again approved capex plans that will further expand their capacity for flip chip package assembly at their factory in Paju, South Korea. The new Flip Chip expansion will be ready for volume production in July 2013 and will increase assembly capacity by more than twenty percent. This line is capable of handling boat type flip chip ball grid arrays (FCBGA) including Signetics’ new high density Super Wide Boat, as well as flip chip fine pitch BGAs (FCFBGA) with substrates as wide as 95mm.

"In the first half of this year, we have continued to see an increase in the forecasts for Flip Chip packaging from our established tier 1 and high growth customers," stated JI Kim, CEO and president of Signetics. "The growth in flip chip continues to be driven by applications such as Smart TVs, SSD and WiFi", continued Kim.

Signetics offers a range of flip chip packaging options that use industry standard bumping technologies as well as the finer pitch copper pillar bumping technology.  Substrates used for flip chip packaging at Signetics include both PBGA and FBGA as well as leadframe technologies such as QFN.  Flip chip assembly is offered in multi die or system-in-package configurations and hybrid configurations with both wirebond and flip chip connectivity for today’s new applications that require more and more system integration in a single package.

Mentor Graphics Corp. and Tezzaron Semiconductor Corp. today announced they are collaborating to integrate the Mentor Calibre 3DSTACK product into Tezzaron’s 3D-IC offerings. The new integration will focus on fast, automated verification of die-to-die interactions in 2.5D and 3D stacked die configurations by verifying individual dies in the usual manner, while verifying die-to-die interfaces in a separate procedure with specialized automation features. The two companies plan to extend their collaboration to include development of solutions for the silicon photonics market.

 “Tezzaron specializes in 3D wafer stacking and TSV processes. We work with dozens of customers to create custom 3D-ICs for prototyping and commercialization, including recent 3D-ICs in 40nm and 65nm, the first at these small nodes,” said Robert Patti, CTO and VP of design engineering at Tezzaron Semiconductor. “By collaborating with Mentor Graphics, we can offer our mutual customers a comprehensive design verification solution. It creates the highest value for them with the least disruption to their existing flows. Using Calibre, our customers get the best possible turnaround time. Even better, there is no need to generate a ‘Frankenstein’ GDS file combining all the individual dies in a 3D-IC assembly, and no need to deal with a ‘monster’ rule file combining different die processes. Calibre makes the process very fast and relatively easy.”

Tezzaron works with industry, academia, and government to create advanced 3D-ICs. Their offerings include wafer stacking and die stacking technology with TSVs, Bi-STAR built in self-test and repair circuitry for continuous error detection and recovery, and extremely fast memory devices for both standalone and stacked applications.

Complementing Tezzaron’s 3D-IC design capabilities, the Calibre 3DSTACK signoff solution provides DRC, LVS, and parasitic extraction (PEX) capabilities. It verifies physical offset, rotation, and scaling at the die interfaces. It also enables connectivity tracing and extraction of interface parasitic elements needed for multi-die performance simulation. The Calibre 3DSTACK product is a fully compatible extension to the standard Calibre signoff platform, so it can be easily added to existing verification flows to support flexible stacking configurations of multiple dies, including dies based on different technologies or process nodes.

“Over the last two years, the relationship between Mentor Graphics and Tezzaron has really blossomed as we work together to bring volume 3D-IC applications to the IC industry mainstream,” said Michael Buehler-Garcia, senior director of marketing for Calibre Design Solutions at Mentor Graphics.

Tezzaron Semiconductor Corporation is a designer and producer of 3D-ICs built with through-silicon vias (TSVs). Tezzaron also builds patented ultra-high-speed memory products. Tezzaron’s products and technologies have applications in defense, super-computing, high speed telecommunications, and anywhere that speed, reliability, and power optimization are needed. Corporate headquarters are located at 1415 Bond Street, Suite 111, Naperville, Illinois.

Ed Korczynski, Senior Technical Editor, Solid State Technology/SemiMD

The most functionality at the least cost is the promise of wafer-level packaging (WLP) when dealing with complex integrated circuits (IC) with a high number of input/output connections to the outside world. Integration of heterogeneous circuit functions—such as micro- and graphics-processing, field-programmable gate array (FPGA) logic, dynamic and static memory, radio-frequency (RF) and analog, and sensing and actuating—may also be needed at the package-level to be able to deliver complete systems (Figure 1).

FIGURE 1: Heterogeneous System-in-Package (SiP) as an extension of proven flip-chip (FC) packaging technology. (Source: Amkor)

In particular, electronic systems for high-growth mobile applications require low-power and low-volume per element which dis-allows circuit integration at the printed-circuit board (PCB) level. Instead, heterogeneous integration must occur as either a system-in-package (SIP) or a system on-chip (SOC). Dr. Eric Mounier of Yole Développement, presented at the recent European 3D TSV Summit 2014 held in Grenoble, and showed Yole forecasts that total world-wide semiconductor IC wafers packaged at the wafer-scale will be 19% this year, raising to 20% in 2015.

One way of looking at the history of the IC industry is to examine the dynamic between SIP and SOC approaches. New functionalities tend to be first integrated into hardware as dedicated additional chips, to be connected in to the rest of the system as part of a PCB or SIP. Since different functionalities often require different fab processes, it is generally less expensive at the chip-level to divide functionalities into different chips, but then the packaging costs tend to be higher. Relatively low-volume parts may be most economically delivered as SIP, while higher-volume parts can often justify the additional design and test expenses of delivering the same functionality as a single SOC.

The other major reason to go with an SIP is to improve the yield of large area chips at the leading edge of fab processing. Since defects/area tend to be relatively high with a new fab process, very large chip designs will have relatively low yield at first but then will improve as the fab learns how to reduce both random and systematic yield limiters. The recent excellent example of this trend is the Xilinx Vertex-7 FPGA which splits the chip into four sub-chips and then uses a silicon interposer for SIP re-integration. We may expect that a next-generation of the product would be build in a single SOC after the yield improves, at which point Xilinx would be expected to extend the product line with additional functionality added in using multi-chip SIP.

Fan-Out WLP

Steffen Kroehnert, director of technology for Nanium S.A., gave a recent presentation at SEMICON/Singapore 2014 entitled “Wafer Level Fan-Out as Fine-Pitch Interposer.” Fan-In WLP uses layout package connections within the chip area, and when the scale and count of on-chip bond pads does not match with standard packaging scales, a Re-Distribution Layer (RDL) of metal interconnect  can be used to Fan-In to ball-grid or pillar-grid arrays (BGA/PGA) within the chip-area. However, when the needed number of connections cannot be made within the chip area, packaging filler materials can be used to provide physical area adjacent to an original chip such that package connections can be arranged to Fan-Out WLP solutions use “Fan-Out” out from the chip center when seen from above.

Chip-Package-Board simultaneous co-design and co-development are becoming import instead of serial work according to Kroehnert. The penalty for re-design costs and losing strategic time-to-market for a new SiP is too high for allow for iterative R&D, such that products must be co-designed properly the first time.

 

FO-WLP Leveraging PV Fab Tricks

Deca Technologies, the electronic interconnect solutions provider to the semiconductor industry owned by Cypress Semiconductor, recently announced that it has shipped its 100-millionth component. The company attributes this milestone to strong demand from portable electronics manufacturers for wafer-level chip scale packages (WLCSP) manufactured using Deca’s unique, integrated Autoline production platform, which is designed to achieve faster time-to-market at lower cost.

Leveraging volume production technologies from leading silicon PV manufacturer SunPower Corp., Deca quickly achieved this milestone by addressing cycle time and capital cost challenges that semiconductor device manufacturers have struggled with using conventional approaches to WLCSP manufacturing. Deca claims that other FO-WLP technologies suffer from inherent manufacturing and reliability issues due to discontinuity at the silicon:mold-compound interface, which are avoided by the company’s use of copper-pillars and an over-mold approach (Figure 2).

FIGURE 2: Cross-section of edge of FO-WLP using Cu-pillars and over-mold approach. (Source: Deca Technologies)

Demand for WLCSP is being driven by manufacturers of wireless connectivity, audio, and power management components for mobile markets. Demand fluctuations in these markets can lead to challenges in managing inventories. “Congratulations to the Deca team on achieving this significant milestone,” said Brent Wilson, senior vice president of the Global Supply Chain Organization at ON Semiconductor. “Deca’s innovative technologies and focus on customer service have made the company a valuable part of our supply chain.”

“Reaching 100 million units is an important milestone for Deca because it validates our unique approach to WLCSP manufacturing,” said Chris Seams, CEO of Deca Technologies. “Based on the demand forecasted by our customers, we anticipate passing the half-billion mark in unit shipments this year.”

FO-WLP for the future

As thoroughly covered in our sister blog Insights From The Leading Edge, STATSChipPAC (SCP) recently announced FlexLine™ FO-WLP. The FlexLine flow dices and reconstitutes incoming wafers of various sizes to a standard size, which results in wafer level packaging equipment becoming independent of incoming silicon wafer size. The SCP FlexLine process flow is based on the SCP commercial eWLB FO-WLP process (Figure 3). Single and multi die fan-out package solutions have been in high-volume manufacturing since 2009 with more than a half-billion units shipped.

 

FIGURE 3: Schematic cross-sections of various Fan-Out WLP packages. (Source: STATSChipPAC)

Earlier this month, Digitimes provided a brief English translation of some Chinese-language Economic Daily News (EDN) saying that Taiwan Semiconductor Manufacturing Company (TSMC) plans to increase IC packaging revenues to US$1 billion in 2015 and to US$2 billion in 2016. TSMC co-CEO CC Wei reportedly acknowledged that the production cost for silicon-substrate SIP (TSMC’s variant termed “chip-on-wafer-on-substrate” or “CoWoS”) packages is relatively high, and so the world’s leading IC foundry intends to invest in FO-WLP technologies to be able to offer advanced packaging at a reduced price.

Wafer-level packaging continues to gain slow IC market share, and novel fan-out redistribution drives the need for improvements in existing packaging materials within tight cost and reliability constraints. With silicon-interposers and copper-interconnects part of WLP technology, the lines between chip and package have never been less clear. Managing all of this complexity is business as usual when designing mobile systems of the future.

‒E.K.

 

 

Yole Développement announced its 2.5D, 3DIC and TSV Interconnect Patent Investigation report. Yole Développement’s investigation aims at providing statistical analysis of existing IP to give a landscape overview together with an in-depth investigation on five player portfolios selected by the analyst.

2.5D, 3DIC and TSV patent landscape

A very young patent landscape dominated by 10 companies

For this analysis of 3D packaging technology patents, more than 1800 patent families were screened. Fifty-two percent of the families have been classified as relevant and further studied.

“The in-depth analysis quickly revealed that the overall patent landscape was pretty young with 82 percent of patents filed since 2006,” explained Lionel Cadix, technology and market analyst of the Advanced Packaging division at Yole Développement. “Actually about 260 players are involved in 3DIC technology while the top 10 assignees represents 48 percent of patents filed in the 3DIC domain.”

In this report, Yole Développement selected five companies from these 10 most active players to focus on and lead an accurate analysis of their patent portfolios.

Yole Développement also found main types of business models among the top 10 assignees involved in this mutating middle end area:

  • Foundries and IDM: IBM, Samsung, Intel
  • OSATs: STATS ChipPAC, Amkor
  • Memory IDM/Foundries: Micron, SK Hynix, Elpida
  • Research centers: ITRI

It is also interesting to notice that the USA is the early player increasingly involved in 3DIC since 1969. China and Korea are new players since 2005.

This complete description of the patent landscape is included in the first part of the report and provides all the background materials for the 3DIC patent landscape analysis. Yole Développement’s report provides a complete analysis of the patent landscape including geographical origins of the patents, companies or R&D organizations that have been granted the patents, historical data on when the companies that have applied for patents in the last 20 years, inventors of the patents, expiration status, R&D collaborations.

Understanding the patent portfolio of the top 10 3DIC assignees

The report also provides a deep dive into each of the patent portfolios of assignees selected by Yole Développement, including Intel, Samsung, Micron, IBM and TSMC.

For each of these companies, Yole’s report provides an in-depth analysis of its patent portfolio, highlighting the following points:

  • Company patent portfolio evolution
  • Countries of deposition and origin of the patents
  • Top inventors
  • Technical segmentation of each patent portfolio
  • Patent portfolio analysis for each manufacturing process steps and architecture
  • Main technical innovations

This analysis of each company provides an in-depth view of the strengths and weaknesses of the patent portfolio of each company and the developments that are now implemented by these companies.