Category Archives: Wafer Level Packaging

wafer bonding and packagingEV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that it is developing equipment and process technology to enable covalent bonds at room temperature. This technology will be available on a new equipment platform, called EVG580 ComBond, which will include process modules that are designed to perform surface preparation processes on both semiconductor materials and metals. EVG built on its decades of experience with plasma activated wafer bonding to create a novel process through which the treated surfaces form strong bonds at room temperature instantaneously without the need for annealing.

"In response to market needs for more sophisticated integration processes for combining materials with different coefficients of thermal expansion, we have developed a revolutionary process technology that enables the formation of bond interfaces between heterogeneous materials at room temperature," stated Markus Wimplinger, corporate technology development and IP director for EV Group. "Our expertise in wafer bonding process technology will allow us to provide different variants of the new process according to the requirements of different substrate materials and applications."

EV Group’s new process solutions will enable covalent combinations of compound semiconductors, other engineered substrates and heterogeneous materials integration for applications such as silicon photonics, high mobility transistors, high-performance/low-power logic devices and novel RF devices. The process technology and equipment that enables this room temperature covalent wafer bonding will be applied to EVG’s wafer bonding solutions for MEMS wafer-level packaging as well as to the integration of MEMS and CMOS devices.

Equipment systems based on a 200-mm modular platform, tailored for the specific needs of the new processes, will be available in 2013.

Peregrine Semiconductor Corporation (NASDAQ: PSMI), a fabless provider of high-performance radio frequency integrated circuits (RFICs), yesterday announced plans to collaborate with Murata Manufacturing Company on a multisource arrangement for RF switches and other components based on Peregrine’s proprietary UltraCMOS technology. Under the proposed collaboration agreement, Murata would be granted a license to design and manufacture RF switches and other switch-related components utilizing Peregrine’s technology and intellectual property (IP). The parties expect this agreement to result in an expanded source of supply for these critical RF components, and to assure global OEMs broad access to RF CMOS products.

ultra cmos process for high performance RFThe UltraCMOS process is a patented Silicon-on-Sapphire technology (SOS). The UltraCMOS process is the industry’s first and only commercially qualified use of Ultra-Thin-Silicon (UTSi) on sapphire substrates, enabling the combination of high-performance RF, mixed-signal, passive elements, nonvolatile memory and digital functions on a single device. This integration provides significant performance advantages over other mixed-signal processes such as GaAs, SiGe, BiCMOS and bulk silicon CMOS in applications where RF performance, low power and integration are paramount.

Murata is a supplier of RF front-end modules for the global mobile wireless marketplace. RF front-end modules are products that incorporate RF switches and tuning devices with SAW filters, passive components, and advanced packaging techniques.

“Global OEM customers of both Peregrine and Murata have for some time requested that the companies implement an independent source of supply for the critical switching elements that are widely utilized in today’s smart phones and other wireless-communications products,” said Jim Cable, Peregrine’s President and CEO. “This agreement marks the first license of Peregrine’s core switch-based intellectual property to a third party and we look forward to entering into this collaborative arrangement with Murata.”

Regarding yesterday’s announcement, Norio Nakajima, Murata’s Vice President, Communication Business Unit, said, “Peregrine has fundamental IP in CMOS-based switches and tuning products with its UltraCMOS technology. This IP licensing arrangement solidifies our existing relationship and future collaboration with Peregrine. We believe that the combination of Murata’s filter and packaging technology with Peregrine’s UltraCMOS switch and tuning technology is a formidable RF front-end solution.”

Despite its high 19% CAGR, Flip-chip is not new – in fact, it was first introduced by IBM over 30 years ago. As such, it would be easy to consider it an old, uninteresting, mature technology, but this is far from true. Instead, Flip-Chip is keeping up with the times and developing new bumping solutions to serve the most advanced technologies, like 3D IC and 2.5D. No matter what packaging technology you’re using, a bumping step is always required at the end. In 2012, bumping technologies accounted for 81% of the total installed capacity in the middle end area. That’s big. Really big. So big that it represents 14M+ 12’’eq wafers – and fab loading rates are high as well, especially for the Cu pillar platform (88%). Flip-Chip is also big on value: in 2012 it was a $20B market (making it the biggest market in the middle-end area), and Yole Développement expects it to continue growing at a 9% clip, ultimately reaching $35 billion by 2018.

Flip-Chip capacity is expected to grow over the next five years to meet large demand from three main areas:

1) CMOS 28nm IC, including new applications like APE and BB

2) The next generation of DDR Memory

3) 3DIC/2.5D interposer using micro-bumping.

Driven by these applications, Cu pillar is on its way to becoming the interconnect of choice for Flip-Chip.

In addition to traditional applications which have used Flip-Chip for a while now (laptop, desktop and their CPUs, GPUs & Chipsets – which are growing slowly but still represent significant production volumes for Flip-Chip), Yole Développement’s analyst expects to see strong demand from mobile & wireless (smartphones), consumer applications (tablets, smart TV, set top box), computing and high performance/ industrial applications such as network, servers, data centers and HPC.

The new “Flip-Chip packaged ICs” are expected to radically alter the market landscape with new specific motivations that will drive demand for wafer bumping.

“In the context of 3D integration and the ‘More than Moore’ approach, Flip-Chip is one of the key technology bricks and will help enable more sophisticated system on chip integration than ever before,” says Lionel Cadix, Market & Technology Analyst, Advanced Packaging, at Yole Développement.

Flip-Chip is being reshaped by a new kind of demand that is hungry for Cu pillars and micro-bumps, which are on their way to becoming the new mainstream bumping metallurgy for die interconnection.

Meanwhile, Cu pillar is fast becoming the interconnect of choice for advanced CMOS (≤28nm), memory, and micro-bumping for 2.5D interposer and 3D IC.

In addition to studying mainstream bumping technologies, the Yole Développement report focuses on Cu pillar bumping, which is becoming increasingly popular for a wide variety of applications. The massive adoption of Cu pillars is motivated by a combination of several drivers, including very fine pitch, no UBM needed, high Z standoff, etc. Cu pillar Flip-Chip is expected to grow at a 35% CAGR between 2010-2018 in terms of wafer count. Production is already high at Intel – and by 2014, more than 50% of bumped wafers for Flip-Chip will be equipped with Cu pillars.

As early as 2013, micro-bumping for 2.5D & 3D IC, in conjunction with new applications like APE, DDR memory, etc., will boost Flip-Chip demand and create new challenges and new technological developments (see figure on the left). Today, Flip- Chip is available in a wide range of pitches to answer the specific needs of every application. The ultimate evolution in bumping technologies will consist of directly bonding IC with copper pads. 3D integration of ICs using this bump-less Cu-Cu bonding is expected to provide an IC-to-IC connection density higher than 4 x 105 cm-2, making it suitable for future wafer-level 3D integration of IC in order to augment Moore’s Law scaling.

Taiwan is the #1 location for Flip-Chip bumping

The major OSATs are preparing to produce fcBGA based Cu pillar packages and won’t limit the reach of cu pillar bumping to fcCSP. This will allow every company involved in CPU, GPU Chipset, APE, BB, ASIC, FPGA and Memory to access Cu pillar Flip-Chip technology. Cu pillar capacity is expected to grow rapidly over the 2010 – 2014 timeframe (31% CAGR), hitting ~9M wspy by 2014 and supporting the growing demand for micro-bumping and advanced CMOS IC bumping.

In the mutating middle-end area, CMOS foundries now propose wafer bumping services (TSMC, GLOBALFOUNDRIES, etc.), as opposed to bumping houses, which are dedicated to bumping operations (FCI, Nepes, etc.), and OSATs, which keep investing in advanced bumping technologies. In 2012, OSATs owned 31% of installed capacity in ECD solder bumping and 22% of installed capacity in Cu pillar bumping. A full overview of 2012 installed capacities for all bumping platforms is provided in this report.

Concerning geography, Taiwan has the biggest overall bumping capacity (regardless of the metallurgy), with important capacity coming from foundries and OSAT factories. Taiwan currently leads the outsourcing “solder & copper” Flip-Chip wafer bumping market. Flip-Chip market growth, spurred on by the emergence of the “middle-end” environment, has challenged traditional “IDM vs. fabless” supply chain possibilities more than ever before.

This week, India’s Finance Minister P Chidambaram offered incentives to chip makers to set up headquarters in India, in an effort to encourage local electronics manufacturing. However, the response from the industry has been less than positive. Many believe that it is a good start, but far from sufficient.

While presenting the Union Budget for 2013-14, Chidambaram said the Indian government will waive customs duty for plants and machinery in the semiconductor sector.

"We recognize the pivotal role of semiconductor wafer fabs in the ecosystem of manufacture of electronics. I propose to provide appropriate incentives to semiconductor wafer fab manufacturing facilities, including zero customs duty for plant and machinery," Chidambaram said, while presenting the budget.

"A company investing Rs.100 crore or more in plant and machinery during the (next fiscal) period will be entitled to deduct an allowance of 15 percent of the investment," he continued. "This will be in addition to the current rates of depreciation. There will be enormous spill-over benefits to small and medium enterprises."

While India has held its own in terms of semiconductor design, very little manufacturing is currently done in the country. Today, India has close to 4,000 electronics manufacturing units and about 300,000 units directly or indirectly supporting the electronics manufacturing industry. The Indian semiconductor design market is anticipated to grow to $14.5 billion by 2015, according to a report, but India’s electronic products manufacturing sector could shrink by as much as 7% in revenue during that same time, indicating that government efforts may not succeed.

As many in the industry know, the semiconductor industry lives and dies by Moore’s law, making fab-launching business ventures a risky move for any start-up.  With the need for constant equipment upgrades, many companies have turned to “fabless” business models, farming out their chip-making to established foundries.

“Building and running a fab is a complex business that is very sensitive to utilization and improvements in technology,” says Satya Gupta, chairman of the Indian Semiconductor Association. “Somebody who knows the fab business has to run it, not the government.”

Many experts point to India’s rising middle class as the main reason to consider India as a potential location for fabs. Much of India’s electronics are imported, meaning India is currently footing a huge import bill to meet the growing demand. As much as 65% of electronic products demand is currently met by imports, which is estimated to grow from $28 billion in 2011 to $42 billion in 2015, according to industry body Indian Electronics and Semiconductor Association, which also report that local manufacturers could lose out on nearly $200 billion of potential revenue by 2015.

But the import bill isn’t the only factor discouraging potential fab-owners.

"I wish it was as simple as offering an import duty exemption. What about availability of land, power and all other government clearances?" said a senior executive at one of the large computer manufacturers told the India Times, requesting anonymity.

What do you think of India’s efforts to encourage fabs? Let us know your thoughts in the comment section below.

GaN Systems Inc., a developer of gallium nitride power switching semiconductors, announced today the opening of a new office facility located in Reading, England. This expansion of the Company’s European operations will aid the Company in continuing to impact key industries, like manufacturing and automotive, where the need for clean technology power conversion applications continue to grow. GaN Systems’ head office is currently located in Ottawa, Canada.

"GaN Systems new office facility comes in response to a strong pull from our growing base of European customer partners," said Geoff Haynes, the Company’s UK based VP Business Development. "The Company has a strong focus on collaborating across the manufacturing value chains for global power electronics markets to accelerate the adoption, and drive the cost of manufacture of GaN components. That can only be achieved through a strong local technical presence."

In addition to sales offices, the new location will include technical support and seminar facilities.

GaN Systems expands
GaN Systems is a developer of gallium nitride power switching semiconductors

 

ultra-low power processorAt this week’s International Solid State Circuits Conference (ISSCC 2013), imec and Holst Centre presented an ultra-low power processor that operates reliably at near-threshold voltages. The processor delivers clock speeds up to 1MHz at voltages down to 0.4 V. In tests based on a Fast Fourier Transform use case, it consumed only 79 µW – a fraction of the power consumption at standard voltages.

“Energy-efficient data processing will be vital for a wide range of emerging applications from Body Area Networks to building automation and equipment monitoring. Reducing active power consumption and standby leakage are thus increasingly important considerations for digital design,” said Harmke de Groot, Program Director at Holst Centre/imec. “Yet much of the industry’s research is still aimed at improving performance rather than increasing battery lifetime by higher energy efficiency.  At Holst Centre, we focus on low power and low voltage to enable battery-powered and energy scavenging smart devices.”

The new energy-efficient processor platform is customized for biomedical applications such as ECG and EEG monitoring. This was realized by creating an interface architecture around a general-purpose processor core to enable ultra-low voltage operation and automatic scaling of performance to improve energy efficiency, plus in-situ monitoring to guarantee reliability and high yield.

One of the key developments was the ability to reduce the operating voltage while delivering enough performance to meet application needs, and maintaining that performance over a range of operating voltages and temperatures. That was achieved by forward biasing the transistors within the processor, allowing it to operate at voltages just above the threshold for the CMOS process used.  The operating voltage can be adjusted between the processor’s nominal voltage of 1.1 V and a minimum voltage of 0.4 V depending on the current performance requirements.

Natural variations in manufacturing processes can lead to voltage fluctuations when a processor is being used. At near-threshold voltages, these fluctuations can be enough to stop the processer working. To avoid this and ensure reliability, the team connected “canary flip-flops” to the most timing-critical parts of the processor. These are designed to fail before the processor’s circuits do and can be monitored – allowing the operating voltage to be scaled up before noise affects the processor. In addition, automatic bias control eliminates the usual voltage drop across the power switches that control the processor, further enhancing energy efficiency and reliability under near-threshold conditions.

To reduce energy consumption even further, the interface can control the state of individual components on the chip separately, for example turning off the processor core or reducing the voltage in the memory when these components are not required. The software interface can also dynamically switch the processor between various performance modes, optimizing the number of active functional units in the core to suit the algorithm being performed. Unused functional units are switched off to reduce power consumption.

Leti to coordinate European supply chain in silicon photonicsCEA-Leti today announced that it will coordinate a four-year project aimed at building a European-based supply chain in silicon photonics and speeding industrialization of the technology.

The PLAT4M (Photonic Libraries And Technology for Manufacturing) project will focus on bringing the existing silicon photonics research platform to a level that enables seamless transition to industry, suitable for different application fields and levels of production volume.

PLAT4M, which is funded by a European Commission grant of 10.2 million euros, includes 15 leading European research and development institutes and CMOS companies, key industrial and research organizations in design and packaging, as well as end users in different application fields to build the complete supply chain.

“Silicon with its mature integration platform has brought electronic circuits to mass-market applications – our vision is that silicon photonics will follow this evolution,” said Laurent Fulbert, Integrated Photonics Program Manager at CEA-Leti, coordinator of PLAT4M. “Upgrading existing platforms to become compatible with industrialization is now essential and this requires streamlining and stabilizing the design and process flows by taking into account design robustness, process variability and integration constraints. The PLAT4M partners bring a combination of expertise to the challenge of building a complete supply chain for commercializing silicon photonics in Europe.”

A surge in output of silicon photonics research in recent years has significantly boosted the potential for commercial exploitation of the technology. However, most of this R&D has been devoted to developing elementary building blocks, rather than fabricating complete photonic integrated circuits, which are needed to support large potential markets.

 The PLAT4M consortium will make technologies and tools mature by building a coherent design flow, demonstrating manufacturability of elementary devices and process integration and developing a packaging toolkit. The project will validate the complete supply chain through application-driven test vehicles representing various application fields, such as telecom and datacom, gas sensing and light detection and ranging (LiDAR) and vibrometry. It also will focus on preparing the next-generation platform by setting up a roadmap for performance evolution and assessing scalability to high-volume production.

The supply chain will be based on technology platforms of Leti, imec and STMicroelectronics, supported by a unified design environment.

 The multiple benefits of PLAT4M for the European photonic industry will include:

  • Preparing the supply chain for silicon photonics technology, from chip-level technology to packaged circuits
  • Making integration technologies accessible to a broad circle of users in a fabless model
  • Contributing to the development of a design environment that facilitates photonics/electronics convergence
  • Moving the emphasis from the component to the architecture, and thus concentrate efforts on new products or new functionalities rather than the technology level
  • Aggregating competencies in photonics/electronics design and fabrication, and
  • Retaining the key added value in components in Europe through optoelectronic integration, with little added value in offshore assembly

PLAT4M Consortium Members

The consortium consists of technology providers, research institutes, end users and SMEs with excellent track records in advanced photonics technologies. At the design and process level, CEA and imec have been the most prominent European players in silicon photonics for a decade. Together with University of Paris-Sud, III-V Lab and TNO, they have demonstrated numerous scientific and technological breakthroughs.

For building a complete design flow, Mentor Graphics, PhoeniX BV and Si2 are world leaders in EDA tools and will work together to develop a common reference platform.

STMicroelectronics (France and Italy) brings its experience in microelectronics, and it has been engaged for the past year in the development of silicon photonics at the industrial level. Tyndall-UCC and Aifotec are renowned experts in the field of optoelectronic packaging and will work together on the implementation of packaging technologies developed within PLAT4M in a manufacturing environment.

End-users like Polytec, Thales Research & Technology and NXP will drive the demonstrators development and assess the use of silicon photonics in their applications fields.

STMicroelectronics (NYSE: STM) announced today another milestone in its testing of its 28nm FD-SOI Technology Platform. Following the Company’s December announcement of the successful manufacturing of System on Chip (SoC) integrated circuits, ST today announced that application-processor engine devices manufactured at the Company’s Crolles, France fab, were capable of operating at 3GHz with even greater power efficiency at a given operating frequency than alternate technologies.

This announcement follows on the heels of recent announcements from other organizations to utilize FD-SOI technologies. Moore’s Law—the observation that the number of transistors on a chip doubled about every two years—has driven the semiconductor industry over the past 50 years to shrink the size of the transistors, which are essentially miniature on/off switches. The increased density from these size reductions have given consumers the explosion of new and more exciting features at lower-cost that we’ve come to expect. In parallel, these new features are able to operate at clock speeds that allow the phones to respond to your commands—by keypad, touchpad, and now voice—almost before you finish expressing the command.

Now, as those transistors shrink to nanoscale dimensions where about 450 transistors can fit within the diameter of a human hair, physics are challenging the traditional high-speed and low-power advantages of planar CMOS technology manufactured on bulk silicon wafers. FD-SOI technology is a major breakthrough in the pursuit of miniaturization of electronic circuits, and the achievement of 3GHz operating speed for an application-processor engine presages the adoption of FD-SOI in portable equipment, digital still cameras, gaming and ASICs for a range of applications. Of the next-generation process technologies, FD-SOI alone has proven its ability to meet the industry’s highest performance and lowest power demands that are vital to delivering graphics and multimedia that amaze without sacrificing battery life.

“As we had anticipated, FD-SOI is proving to be fast, simple and cool; we had fully expected to see 3GHz operating speeds, the design approach is very consistent with what we had been doing in bulk CMOS, and, with the benefits of fully depleted channels and back biasing, the low-power requirements are also meeting our expectations,” said Jean-Marc Chery, Executive Vice President, General Manager Digital Sector, and Chief Technology and Manufacturing Officer of STMicroelectronics.

Reinforcing the point of simplicity, ST has found porting Libraries and Physical IPs from 28nm Bulk CMOS to 28nm FD-SOI to be straightforward, and the process of designing digital SoCs with conventional CAD tools and methods in FD-SOI to be identical to Bulk, due to the absence of MOS-history-effect. FD-SOI enables production of highly energy-efficient devices, with the dynamic body-bias allowing instant switch to high-performance mode when needed and return to a very-low-leakage state for the rest of the time – all in a totally transparent fashion for the application software, operating system, and the cache systems. Finally, FD-SOI can operate at significant performance at low voltage with superior energy efficiency versus Bulk CMOS.

It is a fact that semiconductor industry capital spending is becoming more concentrated with a greater percentage of spending coming from a shrinking number of companies.  As a result, IC industry capacity is also becoming more concentrated and this trend is especially prevalent in 300mm wafer technology.  The figure below lists the 300mm installed capacity leaders for 2012 and IC Insights’ forecast for 2013.  The list was compiled and included in IC Insights’ updated report titled, Global Wafer Capacity 2013—Detailed Analysis and Forecast of the IC Industry’s Wafer Fab Capacity.    As shown, Samsung was by far the leader in 2012 having about 61% more 300mm capacity than second-place SK Hynix. Intel was the only other company that held a double-digit share of 300mm capacity at the end of 2012.  Assuming Micron is successful in acquiring Elpida in 1H13, the combined 300mm wafer capacity of the two companies will make the merged company the second-largest holder of 300mm capacity in the world behind Samsung.

 Of the top 10 companies on the list, half are primarily memory suppliers, two are pure-play foundries, and one company, Intel, is focused on MPUs.  Samsung is expected to maintain its lead in installed capacity through 2017, with aggressive capital spending plans seen over the past few years continuing over the next five years.  However, in terms of growth rate, IC Insights expects the largest increase in 300mm capacity to come from the pure-play foundries—TSMC, GlobalFoundries, UMC, and SMIC.  In total, IC Insights expects these four companies to more than double their collective 300mm wafer starts per month by 2017.

 IC Insights believes that the companies listed will represent essentially all the advanced 300mm IC production and capacity in the future.  IC Insights believes that the top seven or eight companies—Samsung, “Micron-Elpida,” TSMC, SK Hynix, Intel, Toshiba/SanDisk, and GlobalFoundries—can be considered an “elite” group that is just about guaranteed to be a driving force in 300mm capacity additions.  The remaining companies are likely to participate in future 300mm capacity expansion, but all have varying degrees of risk associated with fully realizing their long-term 300mm IC production capacity goals.

Meanwhile, there is still much uncertainty as to when the industry will make the next wafer-size transition—from 300mm to 450mm—and how much it will cost to do so, but momentum continues to build and the transition can now be considered certain to happen.  IC manufacturers have yet to fully optimize the high-volume manufacturing cost structure for the 300mm wafer size.  However, the potential per-die cost savings that the larger wafer can provide is enough of a motivating factor to make the transition happen.

Infineon Technologies AG (FSE: IFX / OTCQX: IFNNY) has achieved a breakthrough in the manufacturing of power semiconductors on 300-millimeter thin wafers. In February, the company received the first customer go-aheads for products of the CoolMOS family produced by the 300-millimeter line at their site in Villach, Austria. The production process based on the new technology has completed qualification from start to finish and customers have given the go-ahead.

"Infineon put its faith in this manufacturing technology very early on and continued to invest even in economically difficult times. The qualification of our entire 300-millimeter line represents a veritable leap ahead of the competition," says Dr. Reinhard Ploss, CEO of Infineon Technologies AG. "300-millimeter thin-wafer manufacturing for power semiconductors will enable us, with the corresponding demand, to seize the opportunities that the market offers."

Infineon is the first and only company worldwide to produce power semiconductors on 300-millimeter thin wafers. Thanks to their larger diameter compared to standard 200-millimeter wafers, two-and-a-half times as many chips can be made from each one. Power semiconductors from Infineon feature low energy loss and compact design. Although not much thicker than a sheet of paper, the chips have electrically active structures on the front and back.

The next step is for the present manufacturing concept for CoolMOS products, qualified from start to finish, with the front-end site Villach and assembly of the thin chips at the back-end site Malacca, Malaysia, to be expanded to the front-end site Dresden. Here the focus is on high-volume production in a fully automated 300-millimeter line. The basis for the processes required and the manufacturing technology is currently being developed in research projects in Dresden. The technology transfer to Dresden is running on schedule and qualification of the first CoolMOS products will be completed in March. Shortly, in Villach more power semiconductor technologies will be transferred to the 300-millimeter line and produced. The development of the next power technology generation will focus on 300 instead of 200-millimeter technology.

"Our ability to innovate is the basis of our success – good ideas are turned into reality,” says Ploss. “In both Austria and in Saxony, we have the necessary conditions for this: technological know-how, well-educated and highly motivated specialists and exemplary support from government policy."

Last year, the independent research institute IMS Research (an IHS company) named Infineon as a market leader in power semiconductors. Infineon develops semiconductor and system solutions addressing three central challenges to modern society: energy efficiency, mobility, and security. In the 2012 fiscal year, ending September 30, the Company reported sales of Euro 3.9 billion with close to 26,700 employees worldwide.